ASoC: ux500: ux500_msp_i2s: Remove unused variables 'reg_val_DR' and 'reg_val_TSTDR'
Looks like these have been unchecked since the driver's inception in 2012. Fixes the following W=1 kernel build warning(s): sound/soc/ux500/ux500_msp_i2s.c: In function ‘flush_fifo_rx’: sound/soc/ux500/ux500_msp_i2s.c:398:6: warning: variable ‘reg_val_DR’ set but not used [-Wunused-but-set-variable] sound/soc/ux500/ux500_msp_i2s.c: In function ‘flush_fifo_tx’: sound/soc/ux500/ux500_msp_i2s.c:415:6: warning: variable ‘reg_val_TSTDR’ set but not used [-Wunused-but-set-variable] Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Cc: zhong jiang <zhongjiang@huawei.com> Cc: Ola Lilja <ola.o.lilja@stericsson.com> Cc: Roger Nilsson <roger.xr.nilsson@stericsson.com> Cc: Sandeep Kaushik <sandeep.kaushik@st.com> Link: https://lore.kernel.org/r/20200709162328.259586-7-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -395,7 +395,7 @@ static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config)
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static void flush_fifo_rx(struct ux500_msp *msp)
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static void flush_fifo_rx(struct ux500_msp *msp)
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{
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{
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u32 reg_val_DR, reg_val_GCR, reg_val_FLR;
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u32 reg_val_GCR, reg_val_FLR;
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u32 limit = 32;
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u32 limit = 32;
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reg_val_GCR = readl(msp->registers + MSP_GCR);
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reg_val_GCR = readl(msp->registers + MSP_GCR);
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@ -403,7 +403,7 @@ static void flush_fifo_rx(struct ux500_msp *msp)
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reg_val_FLR = readl(msp->registers + MSP_FLR);
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reg_val_FLR = readl(msp->registers + MSP_FLR);
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while (!(reg_val_FLR & RX_FIFO_EMPTY) && limit--) {
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while (!(reg_val_FLR & RX_FIFO_EMPTY) && limit--) {
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reg_val_DR = readl(msp->registers + MSP_DR);
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readl(msp->registers + MSP_DR);
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reg_val_FLR = readl(msp->registers + MSP_FLR);
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reg_val_FLR = readl(msp->registers + MSP_FLR);
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}
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}
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@ -412,7 +412,7 @@ static void flush_fifo_rx(struct ux500_msp *msp)
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static void flush_fifo_tx(struct ux500_msp *msp)
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static void flush_fifo_tx(struct ux500_msp *msp)
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{
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{
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u32 reg_val_TSTDR, reg_val_GCR, reg_val_FLR;
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u32 reg_val_GCR, reg_val_FLR;
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u32 limit = 32;
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u32 limit = 32;
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reg_val_GCR = readl(msp->registers + MSP_GCR);
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reg_val_GCR = readl(msp->registers + MSP_GCR);
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@ -421,7 +421,7 @@ static void flush_fifo_tx(struct ux500_msp *msp)
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reg_val_FLR = readl(msp->registers + MSP_FLR);
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reg_val_FLR = readl(msp->registers + MSP_FLR);
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while (!(reg_val_FLR & TX_FIFO_EMPTY) && limit--) {
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while (!(reg_val_FLR & TX_FIFO_EMPTY) && limit--) {
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reg_val_TSTDR = readl(msp->registers + MSP_TSTDR);
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readl(msp->registers + MSP_TSTDR);
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reg_val_FLR = readl(msp->registers + MSP_FLR);
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reg_val_FLR = readl(msp->registers + MSP_FLR);
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}
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}
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writel(0x0, msp->registers + MSP_ITCR);
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writel(0x0, msp->registers + MSP_ITCR);
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