arm64: dts: qcom: sc7280: Add basic dts/dtsi files for sc7280 soc
Add initial device tree support for the sc7280 SoC and the IDP boards based on this SoC Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615461961-17716-4-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Rajendra Nayak
Bjorn Andersson
parent
36dc1681c9
commit
7a1f4e7f74
@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2-lte.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb
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47
arch/arm64/boot/dts/qcom/sc7280-idp.dts
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47
arch/arm64/boot/dts/qcom/sc7280-idp.dts
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@ -0,0 +1,47 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* sc7280 IDP board device tree source
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*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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/dts-v1/;
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#include "sc7280.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. sc7280 IDP platform";
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compatible = "qcom,sc7280-idp", "qcom,sc7280";
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aliases {
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serial0 = &uart5;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&qupv3_id_0 {
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status = "okay";
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};
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&uart5 {
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status = "okay";
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};
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/* PINCTRL - additions to nodes defined in sc7280.dtsi */
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&qup_uart5_default {
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tx {
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pins = "gpio46";
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drive-strength = <2>;
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bias-disable;
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};
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rx {
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pins = "gpio47";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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299
arch/arm64/boot/dts/qcom/sc7280.dtsi
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299
arch/arm64/boot/dts/qcom/sc7280.dtsi
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@ -0,0 +1,299 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* sc7280 SoC device tree source
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*
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,gcc-sc7280.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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clock-frequency = <76800000>;
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#clock-cells = <0>;
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "cache";
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_100>;
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L2_100: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,kryo";
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reg = <0x0 0x200>;
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enable-method = "psci";
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next-level-cache = <&L2_200>;
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L2_200: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,kryo";
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reg = <0x0 0x300>;
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enable-method = "psci";
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next-level-cache = <&L2_300>;
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L2_300: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,kryo";
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reg = <0x0 0x400>;
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enable-method = "psci";
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next-level-cache = <&L2_400>;
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L2_400: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,kryo";
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reg = <0x0 0x500>;
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enable-method = "psci";
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next-level-cache = <&L2_500>;
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L2_500: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,kryo";
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reg = <0x0 0x600>;
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enable-method = "psci";
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next-level-cache = <&L2_600>;
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L2_600: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,kryo";
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reg = <0x0 0x700>;
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enable-method = "psci";
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next-level-cache = <&L2_700>;
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L2_700: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0 0x80000000 0 0>;
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};
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firmware {
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scm {
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compatible = "qcom,scm-sc7280", "qcom,scm";
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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soc: soc@0 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0 0x10 0>;
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dma-ranges = <0 0 0 0 0x10 0>;
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compatible = "simple-bus";
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gcc: clock-controller@100000 {
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compatible = "qcom,gcc-sc7280";
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reg = <0 0x00100000 0 0x1f0000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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qupv3_id_0: geniqup@9c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0 0x009c0000 0 0x2000>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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uart5: serial@994000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0 0x00994000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_uart5_default>;
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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tlmm: pinctrl@f100000 {
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compatible = "qcom,sc7280-pinctrl";
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reg = <0 0x0f100000 0 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 175>;
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qup_uart5_default: qup-uart5-default {
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pins = "gpio46", "gpio47";
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function = "qup13";
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};
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};
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0 0x17a00000 0 0x10000>, /* GICD */
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<0 0x17a60000 0 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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gic-its@17a40000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0 0x17a40000 0 0x20000>;
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status = "disabled";
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};
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};
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timer@17c20000 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0 0x17c20000 0 0x1000>;
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frame@17c21000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0 0x17c21000 0 0x1000>,
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<0 0x17c22000 0 0x1000>;
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};
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frame@17c23000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0 0x17c23000 0 0x1000>;
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status = "disabled";
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};
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frame@17c25000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0 0x17c25000 0 0x1000>;
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status = "disabled";
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};
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frame@17c27000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0 0x17c27000 0 0x1000>;
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status = "disabled";
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};
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frame@17c29000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0 0x17c29000 0 0x1000>;
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status = "disabled";
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};
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frame@17c2b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0 0x17c2b000 0 0x1000>;
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status = "disabled";
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};
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frame@17c2d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0 0x17c2d000 0 0x1000>;
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status = "disabled";
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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