[ALSA] soc - Support PXA3xx AC97
The PXA3xx does not support the use of interrupts during reset and access to the GPIO status requires similar handling to that for PXA27x. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
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@ -61,7 +61,7 @@ static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97,
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mutex_lock(&car_mutex);
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/* set up primary or secondary codec/modem space */
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#ifdef CONFIG_PXA27x
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#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
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#else
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if (reg == AC97_GPIO_STATUS)
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@ -111,7 +111,7 @@ static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
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mutex_lock(&car_mutex);
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/* set up primary or secondary codec/modem space */
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#ifdef CONFIG_PXA27x
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#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
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#else
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if (reg == AC97_GPIO_STATUS)
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@ -134,6 +134,9 @@ static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
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static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97)
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{
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#ifdef CONFIG_PXA3xx
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int timeout = 100;
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#endif
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gsr_bits = 0;
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#ifdef CONFIG_PXA27x
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@ -144,6 +147,11 @@ static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97)
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GCR |= GCR_WARM_RST;
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pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
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udelay(500);
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#elif defined(CONFIG_PXA3xx)
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/* Can't use interrupts */
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GCR |= GCR_WARM_RST;
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while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
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mdelay(1);
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#else
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GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
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wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
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@ -159,6 +167,16 @@ static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97)
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static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97)
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{
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#ifdef CONFIG_PXA3xx
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int timeout = 1000;
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/* Hold CLKBPB for 100us */
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GCR = 0;
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GCR = GCR_CLKBPB;
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udelay(100);
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GCR = 0;
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#endif
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GCR &= GCR_COLD_RST; /* clear everything but nCRST */
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GCR &= ~GCR_COLD_RST; /* then assert nCRST */
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@ -170,6 +188,13 @@ static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97)
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clk_disable(ac97conf_clk);
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GCR = GCR_COLD_RST;
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udelay(50);
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#elif defined(CONFIG_PXA3xx)
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/* Can't use interrupts on PXA3xx */
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GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
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GCR = GCR_WARM_RST | GCR_COLD_RST;
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while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
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mdelay(10);
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#else
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GCR = GCR_COLD_RST;
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GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
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