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x86/mm/pae: Don't (ab)use atomic64

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PAE implies CX8, write readable code.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20221022114424.971450128%40infradead.org
This commit is contained in:
Peter Zijlstra 2020-11-26 17:38:42 +01:00 committed by Dave Hansen
parent 1180e732c9
commit 7a9b8bdb6a
1 changed files with 4 additions and 5 deletions
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9
arch/x86/include/asm/pgtable-3level.h
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@ -2,8 +2,6 @@
#ifndef _ASM_X86_PGTABLE_3LEVEL_H
#define _ASM_X86_PGTABLE_3LEVEL_H
#include <asm/atomic64_32.h>
/*
* Intel Physical Address Extension (PAE) Mode - three-level page
* tables on PPro+ CPUs.
@ -95,11 +93,12 @@ static inline void pud_clear(pud_t *pudp)
#ifdef CONFIG_SMP
static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
{
pte_t res;
pte_t old = *ptep;
res.pte = (pteval_t)arch_atomic64_xchg((atomic64_t *)ptep, 0);
do {
} while (!try_cmpxchg64(&ptep->pte, &old.pte, 0ULL));
return res;
return old;
}
#else
#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)