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Merge branch 'next/cleanup3' of git://git.linaro.org/people/arnd/arm-soc

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* 'next/cleanup3' of git://git.linaro.org/people/arnd/arm-soc: (79 commits)
  ARM: SAMSUNG: Move fimc plat. device from board files to plat-samsung
  ARM: SAMSUNG: Cleanup resources by using macro
  ARM: SAMSUNG: Cleanup plat-samsung/devs.c and devs.h
  ARM: S5P: To merge devs.c files to one devs.c
  ARM: S3C64XX: To merge devs.c files to one devs.c
  ARM: S3C24XX: To merge s3c24xx devs.c files to one devs.c
  ARM: S5P64X0: Add Power Management support
  ARM: S5P: Make the sleep code common for S5P series SoCs
  ARM: S5P: Make the common S5P PM code conditionally compile
  ARM: SAMSUNG: Move S5P header files to plat-samsung
  ARM: SAMSUNG: Move S3C24XX header files to plat-samsung
  ARM: SAMSUNG: Moving each SoC support header files
  ARM: SAMSUNG: Consolidate plat/pll.h
  ARM: SAMSUNG: Consolidate plat/pwm-clock.h
  ARM: SAMSUNG: Cleanup mach/clkdev.h
  ARM: SAMSUNG: remove sdhci default configuration setup platform helper
  ARM: EXYNOS4: Add FIMC device on SMDKV310 board
  ARM: EXYNOS4: Add header file protection macros
  ARM: EXYNOS4: Add usb ehci device to the SMDKV310
  ARM: S3C2443: Add hsspi-clock from pclk and rename S3C2443 hsspi sclk
  ...

Fix up conflicts in
 - arch/arm/mach-exynos4/{Kconfig,clock.c}
	ARM_CPU_SUSPEND, various random device tables (gah!)
 - drivers/gpio/Makefile
	sa1100 gpio added, samsung gpio drivers merged
This commit is contained in:
Linus Torvalds 2011-11-05 18:18:05 -07:00
commit 7abec10c62
226 changed files with 8020 additions and 7209 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/Kconfig
View File

@ -777,9 +777,6 @@ config ARCH_S3C64XX
select SAMSUNG_CLKSRC
select SAMSUNG_IRQ_VIC_TIMER
select S3C_GPIO_TRACK
select S3C_GPIO_PULL_UPDOWN
select S3C_GPIO_CFG_S3C24XX
select S3C_GPIO_CFG_S3C64XX
select S3C_DEV_NAND
select USB_ARCH_HAS_OHCI
select SAMSUNG_GPIOLIB_4BIT
@ -2212,7 +2209,7 @@ menu "Power management options"
source "kernel/power/Kconfig"
config ARCH_SUSPEND_POSSIBLE
depends on !ARCH_S5P64X0 && !ARCH_S5PC100
depends on !ARCH_S5PC100
depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
def_bool y

38
arch/arm/mach-exynos4/Kconfig
View File

@ -13,11 +13,16 @@ config CPU_EXYNOS4210
bool
select SAMSUNG_DMADEV
select ARM_CPU_SUSPEND if PM
select S5P_PM if PM
select S5P_SLEEP if PM
help
Enable EXYNOS4210 CPU support
config SOC_EXYNOS4212
bool
select ARM_CPU_SUSPEND if PM
select S5P_PM if PM
select S5P_SLEEP if PM
help
Enable EXYNOS4212 SoC support
@ -137,6 +142,14 @@ config MACH_SMDKV310
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_I2C1
select S5P_DEV_FIMC0
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
select S5P_DEV_FIMC3
select S5P_DEV_I2C_HDMIPHY
select S5P_DEV_MFC
select S5P_DEV_TV
select S5P_DEV_USB_EHCI
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
@ -151,6 +164,7 @@ config MACH_SMDKV310
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_KEYPAD
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
help
Machine support for Samsung SMDKV310
@ -176,19 +190,26 @@ config MACH_UNIVERSAL_C210
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
select S5P_DEV_FIMC3
select S5P_DEV_CSIS0
select S5P_DEV_FIMD0
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S3C_DEV_I2C1
select S3C_DEV_I2C3
select S3C_DEV_I2C5
select S5P_DEV_I2C_HDMIPHY
select S5P_DEV_MFC
select S5P_DEV_ONENAND
select S5P_DEV_TV
select EXYNOS4_DEV_PD
select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_FIMC
select S5P_SETUP_MIPIPHY
help
Machine support for Samsung Mobile Universal S5PC210 Reference
Board.
@ -197,6 +218,8 @@ config MACH_NURI
bool "Mobile NURI Board"
select CPU_EXYNOS4210
select S3C_DEV_WDT
select S3C_DEV_RTC
select S5P_DEV_FIMD0
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
@ -206,6 +229,7 @@ config MACH_NURI
select S5P_DEV_MFC
select S5P_DEV_USB_EHCI
select EXYNOS4_DEV_PD
select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5
@ -221,8 +245,22 @@ config MACH_ORIGEN
select CPU_EXYNOS4210
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S5P_DEV_FIMC0
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
select S5P_DEV_FIMC3
select S5P_DEV_FIMD0
select S5P_DEV_I2C_HDMIPHY
select S5P_DEV_TV
select S5P_DEV_USB_EHCI
select EXYNOS4_DEV_PD
select SAMSUNG_DEV_BACKLIGHT
select SAMSUNG_DEV_PWM
select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
help
Machine support for ORIGEN based on Samsung EXYNOS4210

2
arch/arm/mach-exynos4/Makefile
View File

@ -16,7 +16,7 @@ obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o

204
arch/arm/mach-exynos4/clock.c
View File

@ -151,6 +151,11 @@ static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
}
static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
}
static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
@ -191,6 +196,16 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
}
static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
}
static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
}
/* Core list of CMU_CPU side */
static struct clksrc_clk clk_mout_apll = {
@ -507,14 +522,44 @@ static struct clk init_clocks_off[] = {
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "dac",
.devname = "s5p-sdo",
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "mixer",
.devname = "s5p-mixer",
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "vp",
.devname = "s5p-mixer",
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "hdmi",
.devname = "exynos4-hdmi",
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "hdmiphy",
.devname = "exynos4-hdmi",
.enable = exynos4_clk_hdmiphy_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "dacphy",
.devname = "s5p-sdo",
.enable = exynos4_clk_dac_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "dma",
.devname = "s3c-pl330.0",
.devname = "dma-pl330.0",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "dma",
.devname = "s3c-pl330.1",
.devname = "dma-pl330.1",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 1),
}, {
@ -634,6 +679,12 @@ static struct clk init_clocks_off[] = {
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "i2c",
.devname = "s3c2440-hdmiphy-i2c",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = "SYSMMU_MDMA",
.enable = exynos4_clk_ip_image_ctrl,
@ -836,6 +887,81 @@ static struct clksrc_sources clkset_mout_mfc = {
.nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
};
static struct clk *clkset_sclk_dac_list[] = {
[0] = &clk_sclk_vpll.clk,
[1] = &clk_sclk_hdmiphy,
};
static struct clksrc_sources clkset_sclk_dac = {
.sources = clkset_sclk_dac_list,
.nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
};
static struct clksrc_clk clk_sclk_dac = {
.clk = {
.name = "sclk_dac",
.enable = exynos4_clksrc_mask_tv_ctrl,
.ctrlbit = (1 << 8),
},
.sources = &clkset_sclk_dac,
.reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
};
static struct clksrc_clk clk_sclk_pixel = {
.clk = {
.name = "sclk_pixel",
.parent = &clk_sclk_vpll.clk,
},
.reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
};
static struct clk *clkset_sclk_hdmi_list[] = {
[0] = &clk_sclk_pixel.clk,
[1] = &clk_sclk_hdmiphy,
};
static struct clksrc_sources clkset_sclk_hdmi = {
.sources = clkset_sclk_hdmi_list,
.nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
};
static struct clksrc_clk clk_sclk_hdmi = {
.clk = {
.name = "sclk_hdmi",
.enable = exynos4_clksrc_mask_tv_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &clkset_sclk_hdmi,
.reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
};
static struct clk *clkset_sclk_mixer_list[] = {
[0] = &clk_sclk_dac.clk,
[1] = &clk_sclk_hdmi.clk,
};
static struct clksrc_sources clkset_sclk_mixer = {
.sources = clkset_sclk_mixer_list,
.nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
};
static struct clksrc_clk clk_sclk_mixer = {
.clk = {
.name = "sclk_mixer",
.enable = exynos4_clksrc_mask_tv_ctrl,
.ctrlbit = (1 << 4),
},
.sources = &clkset_sclk_mixer,
.reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
};
static struct clksrc_clk *sclk_tv[] = {
&clk_sclk_dac,
&clk_sclk_pixel,
&clk_sclk_hdmi,
&clk_sclk_mixer,
};
static struct clksrc_clk clk_dout_mmc0 = {
.clk = {
.name = "dout_mmc0",
@ -1162,6 +1288,71 @@ static struct clk_ops exynos4_fout_apll_ops = {
.get_rate = exynos4_fout_apll_get_rate,
};
static u32 vpll_div[][8] = {
{ 54000000, 3, 53, 3, 1024, 0, 17, 0 },
{ 108000000, 3, 53, 2, 1024, 0, 17, 0 },
};
static unsigned long exynos4_vpll_get_rate(struct clk *clk)
{
return clk->rate;
}
static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
{
unsigned int vpll_con0, vpll_con1 = 0;
unsigned int i;
/* Return if nothing changed */
if (clk->rate == rate)
return 0;
vpll_con0 = __raw_readl(S5P_VPLL_CON0);
vpll_con0 &= ~(0x1 << 27 | \
PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
vpll_con1 = __raw_readl(S5P_VPLL_CON1);
vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
if (vpll_div[i][0] == rate) {
vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
vpll_con0 |= vpll_div[i][7] << 27;
break;
}
}
if (i == ARRAY_SIZE(vpll_div)) {
printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
__func__);
return -EINVAL;
}
__raw_writel(vpll_con0, S5P_VPLL_CON0);
__raw_writel(vpll_con1, S5P_VPLL_CON1);
/* Wait for VPLL lock */
while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
continue;
clk->rate = rate;
return 0;
}
static struct clk_ops exynos4_vpll_ops = {
.get_rate = exynos4_vpll_get_rate,
.set_rate = exynos4_vpll_set_rate,
};
void __init_or_cpufreq exynos4_setup_clocks(void)
{
struct clk *xtal_clk;
@ -1219,6 +1410,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
clk_fout_apll.ops = &exynos4_fout_apll_ops;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_vpll.ops = &exynos4_vpll_ops;
clk_fout_vpll.rate = vpll;
printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
@ -1246,7 +1438,10 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
}
static struct clk *clks[] __initdata = {
/* Nothing here yet */
&clk_sclk_hdmi27m,
&clk_sclk_hdmiphy,
&clk_sclk_usbphy0,
&clk_sclk_usbphy1,
};
#ifdef CONFIG_PM_SLEEP
@ -1280,6 +1475,9 @@ void __init exynos4_register_clocks(void)
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
s3c_register_clksrc(sclk_tv[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));

2
arch/arm/mach-exynos4/cpu.c
View File

@ -28,6 +28,7 @@
#include <plat/fimc-core.h>
#include <plat/iic-core.h>
#include <plat/reset.h>
#include <plat/tv-core.h>
#include <mach/regs-irq.h>
#include <mach/regs-pmu.h>
@ -182,6 +183,7 @@ void __init exynos4_map_io(void)
s3c_i2c2_setname("s3c2440-i2c");
s5p_fb_setname(0, "exynos4-fb");
s5p_hdmi_setname("exynos4-hdmi");
}
void __init exynos4_init_clocks(int xtal)

1
arch/arm/mach-exynos4/dma.c
View File

@ -243,6 +243,7 @@ struct amba_device exynos4_device_pdma1 = {
static int __init exynos4_dma_init(void)
{
amba_device_register(&exynos4_device_pdma0, &iomem_resource);
amba_device_register(&exynos4_device_pdma1, &iomem_resource);
return 0;
}

7
arch/arm/mach-exynos4/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

4
arch/arm/mach-exynos4/include/mach/irqs.h
View File

@ -95,7 +95,11 @@
#define IRQ_2D IRQ_SPI(89)
#define IRQ_PCIE IRQ_SPI(90)
#define IRQ_MIXER IRQ_SPI(91)
#define IRQ_HDMI IRQ_SPI(92)
#define IRQ_IIC_HDMIPHY IRQ_SPI(93)
#define IRQ_MFC IRQ_SPI(94)
#define IRQ_SDO IRQ_SPI(95)
#define IRQ_AUDIO_SS IRQ_SPI(96)
#define IRQ_I2S0 IRQ_SPI(97)

12
arch/arm/mach-exynos4/include/mach/map.h
View File

@ -112,6 +112,12 @@
#define EXYNOS4_PA_UART 0x13800000
#define EXYNOS4_PA_VP 0x12C00000
#define EXYNOS4_PA_MIXER 0x12C10000
#define EXYNOS4_PA_SDO 0x12C20000
#define EXYNOS4_PA_HDMI 0x12D00000
#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
#define EXYNOS4_PA_ADC 0x13910000
@ -161,6 +167,12 @@
#define S5P_PA_TIMER EXYNOS4_PA_TIMER
#define S5P_PA_EHCI EXYNOS4_PA_EHCI
#define S5P_PA_SDO EXYNOS4_PA_SDO
#define S5P_PA_VP EXYNOS4_PA_VP
#define S5P_PA_MIXER EXYNOS4_PA_MIXER
#define S5P_PA_HDMI EXYNOS4_PA_HDMI
#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
/* UART */

8
arch/arm/mach-exynos4/include/mach/pm-core.h
View File

@ -14,6 +14,10 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_PM_CORE_H
#define __ASM_ARCH_PM_CORE_H __FILE__
#include <mach/regs-pmu.h>
static inline void s3c_pm_debug_init_uart(void)
@ -53,7 +57,9 @@ static inline void s3c_pm_restored_gpios(void)
/* nothing here yet */
}
static inline void s3c_pm_saved_gpios(void)
static inline void samsung_pm_saved_gpios(void)
{
/* nothing here yet */
}
#endif /* __ASM_ARCH_PM_CORE_H */

7
arch/arm/mach-exynos4/include/mach/pmu.h
View File

@ -13,6 +13,8 @@
#ifndef __ASM_ARCH_PMU_H
#define __ASM_ARCH_PMU_H __FILE__
#define PMU_TABLE_END NULL
enum sys_powerdown {
SYS_AFTR,
SYS_LPA,
@ -20,6 +22,11 @@ enum sys_powerdown {
NUM_SYS_POWERDOWN,
};
struct exynos4_pmu_conf {
void __iomem *reg;
unsigned int val[NUM_SYS_POWERDOWN];
};
extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
#endif /* __ASM_ARCH_PMU_H */

74
arch/arm/mach-exynos4/include/mach/regs-pmu.h
View File

@ -25,9 +25,10 @@
#define S5P_USE_STANDBY_WFI0 (1 << 16)
#define S5P_USE_STANDBY_WFI1 (1 << 17)
#define S5P_USE_STANDBYWFI_ISP_ARM (1 << 18)
#define S5P_USE_STANDBY_WFE0 (1 << 24)
#define S5P_USE_STANDBY_WFE1 (1 << 25)
#define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24))
#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
#define S5P_SWRESET S5P_PMUREG(0x0400)
@ -35,15 +36,17 @@
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708)
#define S5P_USBHOST_PHY_ENABLE (1 << 0)
#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700)
#define S5P_HDMI_PHY_ENABLE (1 << 0)
#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C)
#define S5P_DAC_PHY_ENABLE (1 << 0)
#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4)
#define S5P_MIPI_DPHY_ENABLE (1 << 0)
#define S5P_MIPI_DPHY_SRESETN (1 << 1)
#define S5P_MIPI_DPHY_MRESETN (1 << 2)
#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
#define S5P_INFORM0 S5P_PMUREG(0x0800)
#define S5P_INFORM1 S5P_PMUREG(0x0804)
#define S5P_INFORM2 S5P_PMUREG(0x0808)
@ -76,7 +79,6 @@
#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
@ -84,7 +86,6 @@
#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
@ -92,14 +93,11 @@
#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
@ -120,7 +118,6 @@
#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
@ -156,7 +153,6 @@
#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
@ -165,4 +161,60 @@
#define S5P_CHECK_SLEEP 0x00000BAD
/* Only for EXYNOS4210 */
#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708)
#define S5P_USBHOST_PHY_ENABLE (1 << 0)
#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
/* Only for EXYNOS4212 */
#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110)
#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114)
#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C)
#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130)
#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154)
#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174)
#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190)
#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194)
#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198)
#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4)
#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0)
#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4)
#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4)
#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC)
#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C)
#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250)
#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320)
#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344)
#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348)
#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394)
#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0)
#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4)
#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8)
#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC)
#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0)
#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608)
#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628)
#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08)
#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28)
#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48)
#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68)
#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88)
#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8)
#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
#endif /* __ASM_ARCH_REGS_PMU_H */

34
arch/arm/mach-exynos4/mach-nuri.c
View File

@ -32,10 +32,12 @@
#include <asm/mach-types.h>
#include <plat/adc.h>
#include <plat/regs-fb-v4.h>
#include <plat/regs-serial.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/fb.h>
#include <plat/sdhci.h>
#include <plat/ehci.h>
#include <plat/clock.h>
@ -199,6 +201,33 @@ static struct platform_device nuri_gpio_keys = {
},
};
/* Frame Buffer */
static struct s3c_fb_pd_win nuri_fb_win0 = {
.win_mode = {
.left_margin = 64,
.right_margin = 16,
.upper_margin = 64,
.lower_margin = 1,
.hsync_len = 48,
.vsync_len = 3,
.xres = 1280,
.yres = 800,
.refresh = 60,
},
.max_bpp = 24,
.default_bpp = 16,
.virtual_x = 1280,
.virtual_y = 800,
};
static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
.win[0] = &nuri_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
VIDCON0_CLKSEL_LCD,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
};
static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
{
int gpio = EXYNOS4_GPE1(5);
@ -1092,6 +1121,7 @@ static struct platform_device *nuri_devices[] __initdata = {
/* Samsung Platform Devices */
&s3c_device_i2c5, /* PMIC should initialize first */
&emmc_fixed_voltage,
&s5p_device_fimd0,
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
@ -1106,6 +1136,7 @@ static struct platform_device *nuri_devices[] __initdata = {
&s5p_device_mfc_l,
&s5p_device_mfc_r,
&exynos4_device_pd[PD_MFC],
&exynos4_device_pd[PD_LCD0],
/* NURI Devices */
&nuri_gpio_keys,
@ -1142,12 +1173,15 @@ static void __init nuri_machine_init(void)
i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
s5p_fimd0_set_platdata(&nuri_fb_pdata);
nuri_ehci_init();
clk_xusbxti.rate = 24000000;
/* Last */
platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
}
MACHINE_START(NURI, "NURI")

579
arch/arm/mach-exynos4/mach-origen.c
View File

@ -14,16 +14,31 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/input.h>
#include <linux/pwm_backlight.h>
#include <linux/gpio_keys.h>
#include <linux/i2c.h>
#include <linux/regulator/machine.h>
#include <linux/mfd/max8997.h>
#include <linux/lcd.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <video/platform_lcd.h>
#include <plat/regs-serial.h>
#include <plat/regs-fb-v4.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/sdhci.h>
#include <plat/iic.h>
#include <plat/ehci.h>
#include <plat/clock.h>
#include <plat/gpio-cfg.h>
#include <plat/backlight.h>
#include <plat/pd.h>
#include <plat/fb.h>
#include <mach/map.h>
@ -72,19 +87,543 @@ static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
},
};
static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = EXYNOS4_GPK2(2),
.ext_cd_gpio_invert = 1,
static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
};
static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
};
static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
};
static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
};
static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
};
static struct regulator_consumer_supply __initdata ldo11_consumer[] = {
REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */
};
static struct regulator_consumer_supply __initdata ldo14_consumer[] = {
REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
};
static struct regulator_consumer_supply __initdata ldo17_consumer[] = {
REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
};
static struct regulator_consumer_supply __initdata buck1_consumer[] = {
REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
};
static struct regulator_consumer_supply __initdata buck2_consumer[] = {
REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
};
static struct regulator_consumer_supply __initdata buck3_consumer[] = {
REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */
};
static struct regulator_consumer_supply __initdata buck7_consumer[] = {
REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */
};
static struct regulator_init_data __initdata max8997_ldo1_data = {
.constraints = {
.name = "VDD_ABB_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data __initdata max8997_ldo2_data = {
.constraints = {
.name = "VDD_ALIVE_1.1V",
.min_uV = 1100000,
.max_uV = 1100000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.enabled = 1,
},
},
};
static struct regulator_init_data __initdata max8997_ldo3_data = {
.constraints = {
.name = "VMIPI_1.1V",
.min_uV = 1100000,
.max_uV = 1100000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(ldo3_consumer),
.consumer_supplies = ldo3_consumer,
};
static struct regulator_init_data __initdata max8997_ldo4_data = {
.constraints = {
.name = "VDD_RTC_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data __initdata max8997_ldo6_data = {
.constraints = {
.name = "VMIPI_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(ldo6_consumer),
.consumer_supplies = ldo6_consumer,
};
static struct regulator_init_data __initdata max8997_ldo7_data = {
.constraints = {
.name = "VDD_AUD_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(ldo7_consumer),
.consumer_supplies = ldo7_consumer,
};
static struct regulator_init_data __initdata max8997_ldo8_data = {
.constraints = {
.name = "VADC_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(ldo8_consumer),
.consumer_supplies = ldo8_consumer,
};
static struct regulator_init_data __initdata max8997_ldo9_data = {
.constraints = {
.name = "DVDD_SWB_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(ldo9_consumer),
.consumer_supplies = ldo9_consumer,
};
static struct regulator_init_data __initdata max8997_ldo10_data = {
.constraints = {
.name = "VDD_PLL_1.1V",
.min_uV = 1100000,
.max_uV = 1100000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data __initdata max8997_ldo11_data = {
.constraints = {
.name = "VDD_AUD_3V",
.min_uV = 3000000,
.max_uV = 3000000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(ldo11_consumer),
.consumer_supplies = ldo11_consumer,
};
static struct regulator_init_data __initdata max8997_ldo14_data = {
.constraints = {
.name = "AVDD18_SWB_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(ldo14_consumer),
.consumer_supplies = ldo14_consumer,
};
static struct regulator_init_data __initdata max8997_ldo17_data = {
.constraints = {
.name = "VDD_SWB_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(ldo17_consumer),
.consumer_supplies = ldo17_consumer,
};
static struct regulator_init_data __initdata max8997_ldo21_data = {
.constraints = {
.name = "VDD_MIF_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data __initdata max8997_buck1_data = {
.constraints = {
.name = "VDD_ARM_1.2V",
.min_uV = 950000,
.max_uV = 1350000,
.always_on = 1,
.boot_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(buck1_consumer),
.consumer_supplies = buck1_consumer,
};
static struct regulator_init_data __initdata max8997_buck2_data = {
.constraints = {
.name = "VDD_INT_1.1V",
.min_uV = 900000,
.max_uV = 1100000,
.always_on = 1,
.boot_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(buck2_consumer),
.consumer_supplies = buck2_consumer,
};
static struct regulator_init_data __initdata max8997_buck3_data = {
.constraints = {
.name = "VDD_G3D_1.1V",
.min_uV = 900000,
.max_uV = 1100000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(buck3_consumer),
.consumer_supplies = buck3_consumer,
};
static struct regulator_init_data __initdata max8997_buck5_data = {
.constraints = {
.name = "VDDQ_M1M2_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data __initdata max8997_buck7_data = {
.constraints = {
.name = "VDD_LCD_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.boot_on = 1,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1
},
},
.num_consumer_supplies = ARRAY_SIZE(buck7_consumer),
.consumer_supplies = buck7_consumer,
};
static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
{ MAX8997_LDO1, &max8997_ldo1_data },
{ MAX8997_LDO2, &max8997_ldo2_data },
{ MAX8997_LDO3, &max8997_ldo3_data },
{ MAX8997_LDO4, &max8997_ldo4_data },
{ MAX8997_LDO6, &max8997_ldo6_data },
{ MAX8997_LDO7, &max8997_ldo7_data },
{ MAX8997_LDO8, &max8997_ldo8_data },
{ MAX8997_LDO9, &max8997_ldo9_data },
{ MAX8997_LDO10, &max8997_ldo10_data },
{ MAX8997_LDO11, &max8997_ldo11_data },
{ MAX8997_LDO14, &max8997_ldo14_data },
{ MAX8997_LDO17, &max8997_ldo17_data },
{ MAX8997_LDO21, &max8997_ldo21_data },
{ MAX8997_BUCK1, &max8997_buck1_data },
{ MAX8997_BUCK2, &max8997_buck2_data },
{ MAX8997_BUCK3, &max8997_buck3_data },
{ MAX8997_BUCK5, &max8997_buck5_data },
{ MAX8997_BUCK7, &max8997_buck7_data },
};
struct max8997_platform_data __initdata origen_max8997_pdata = {
.num_regulators = ARRAY_SIZE(origen_max8997_regulators),
.regulators = origen_max8997_regulators,
.wakeup = true,
.buck1_gpiodvs = false,
.buck2_gpiodvs = false,
.buck5_gpiodvs = false,
.irq_base = IRQ_GPIO_END + 1,
.ignore_gpiodvs_side_effect = true,
.buck125_default_idx = 0x0,
.buck125_gpios[0] = EXYNOS4_GPX0(0),
.buck125_gpios[1] = EXYNOS4_GPX0(1),
.buck125_gpios[2] = EXYNOS4_GPX0(2),
.buck1_voltage[0] = 1350000,
.buck1_voltage[1] = 1300000,
.buck1_voltage[2] = 1250000,
.buck1_voltage[3] = 1200000,
.buck1_voltage[4] = 1150000,
.buck1_voltage[5] = 1100000,
.buck1_voltage[6] = 1000000,
.buck1_voltage[7] = 950000,
.buck2_voltage[0] = 1100000,
.buck2_voltage[1] = 1100000,
.buck2_voltage[2] = 1100000,
.buck2_voltage[3] = 1100000,
.buck2_voltage[4] = 1000000,
.buck2_voltage[5] = 1000000,
.buck2_voltage[6] = 1000000,
.buck2_voltage[7] = 1000000,
.buck5_voltage[0] = 1200000,
.buck5_voltage[1] = 1200000,
.buck5_voltage[2] = 1200000,
.buck5_voltage[3] = 1200000,
.buck5_voltage[4] = 1200000,
.buck5_voltage[5] = 1200000,
.buck5_voltage[6] = 1200000,
.buck5_voltage[7] = 1200000,
};
/* I2C0 */
static struct i2c_board_info i2c0_devs[] __initdata = {
{
I2C_BOARD_INFO("max8997", (0xCC >> 1)),
.platform_data = &origen_max8997_pdata,
.irq = IRQ_EINT(4),
},
};
static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_INTERNAL,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_INTERNAL,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
/* USB EHCI */
static struct s5p_ehci_platdata origen_ehci_pdata;
static void __init origen_ehci_init(void)
{
struct s5p_ehci_platdata *pdata = &origen_ehci_pdata;
s5p_ehci_set_platdata(pdata);
}
static struct gpio_keys_button origen_gpio_keys_table[] = {
{
.code = KEY_MENU,
.gpio = EXYNOS4_GPX1(5),
.desc = "gpio-keys: KEY_MENU",
.type = EV_KEY,
.active_low = 1,
.wakeup = 1,
.debounce_interval = 1,
}, {
.code = KEY_HOME,
.gpio = EXYNOS4_GPX1(6),
.desc = "gpio-keys: KEY_HOME",
.type = EV_KEY,
.active_low = 1,
.wakeup = 1,
.debounce_interval = 1,
}, {
.code = KEY_BACK,
.gpio = EXYNOS4_GPX1(7),
.desc = "gpio-keys: KEY_BACK",
.type = EV_KEY,
.active_low = 1,
.wakeup = 1,
.debounce_interval = 1,
}, {
.code = KEY_UP,
.gpio = EXYNOS4_GPX2(0),
.desc = "gpio-keys: KEY_UP",
.type = EV_KEY,
.active_low = 1,
.wakeup = 1,
.debounce_interval = 1,
}, {
.code = KEY_DOWN,
.gpio = EXYNOS4_GPX2(1),
.desc = "gpio-keys: KEY_DOWN",
.type = EV_KEY,
.active_low = 1,
.wakeup = 1,
.debounce_interval = 1,
},
};
static struct gpio_keys_platform_data origen_gpio_keys_data = {
.buttons = origen_gpio_keys_table,
.nbuttons = ARRAY_SIZE(origen_gpio_keys_table),
};
static struct platform_device origen_device_gpiokeys = {
.name = "gpio-keys",
.dev = {
.platform_data = &origen_gpio_keys_data,
},
};
static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
{
int ret;
if (power)
ret = gpio_request_one(EXYNOS4_GPE3(4),
GPIOF_OUT_INIT_HIGH, "GPE3_4");
else
ret = gpio_request_one(EXYNOS4_GPE3(4),
GPIOF_OUT_INIT_LOW, "GPE3_4");
gpio_free(EXYNOS4_GPE3(4));
if (ret)
pr_err("failed to request gpio for LCD power: %d\n", ret);
}
static struct plat_lcd_data origen_lcd_hv070wsa_data = {
.set_power = lcd_hv070wsa_set_power,
};
static struct platform_device origen_lcd_hv070wsa = {
.name = "platform-lcd",
.dev.parent = &s5p_device_fimd0.dev,
.dev.platform_data = &origen_lcd_hv070wsa_data,
};
static struct s3c_fb_pd_win origen_fb_win0 = {
.win_mode = {
.left_margin = 64,
.right_margin = 16,
.upper_margin = 64,
.lower_margin = 16,
.hsync_len = 48,
.vsync_len = 3,
.xres = 1024,
.yres = 600,
},
.max_bpp = 32,
.default_bpp = 24,
};
static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
.win[0] = &origen_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
};
static struct platform_device *origen_devices[] __initdata = {
&s3c_device_hsmmc2,
&s3c_device_hsmmc0,
&s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_wdt,
&s5p_device_ehci,
&s5p_device_fimc0,
&s5p_device_fimc1,
&s5p_device_fimc2,
&s5p_device_fimc3,
&s5p_device_fimd0,
&s5p_device_hdmi,
&s5p_device_i2c_hdmiphy,
&s5p_device_mixer,
&exynos4_device_pd[PD_LCD0],
&exynos4_device_pd[PD_TV],
&origen_device_gpiokeys,
&origen_lcd_hv070wsa,
};
/* LCD Backlight data */
static struct samsung_bl_gpio_info origen_bl_gpio_info = {
.no = EXYNOS4_GPD0(0),
.func = S3C_GPIO_SFN(2),
};
static struct platform_pwm_backlight_data origen_bl_data = {
.pwm_id = 0,
.pwm_period_ns = 1000,
};
static void s5p_tv_setup(void)
{
/* Direct HPD to HDMI chip */
gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
}
static void __init origen_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@ -92,10 +631,42 @@ static void __init origen_map_io(void)
s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
}
static void __init origen_power_init(void)
{
gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ");
s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE);
}
static void __init origen_machine_init(void)
{
origen_power_init();
s3c_i2c0_set_platdata(NULL);
i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
/*
* Since sdhci instance 2 can contain a bootable media,
* sdhci instance 0 is registered after instance 2.
*/
s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
origen_ehci_init();
clk_xusbxti.rate = 24000000;
s5p_tv_setup();
s5p_i2c_hdmiphy_set_platdata(NULL);
s5p_fimd0_set_platdata(&origen_lcd_pdata);
platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
}
MACHINE_START(ORIGEN, "ORIGEN")

49
arch/arm/mach-exynos4/mach-smdkv310.c
View File

@ -37,6 +37,9 @@
#include <plat/pd.h>
#include <plat/gpio-cfg.h>
#include <plat/backlight.h>
#include <plat/mfc.h>
#include <plat/ehci.h>
#include <plat/clock.h>
#include <mach/map.h>
@ -232,17 +235,36 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
{I2C_BOARD_INFO("wm8994", 0x1a),},
};
/* USB EHCI */
static struct s5p_ehci_platdata smdkv310_ehci_pdata;
static void __init smdkv310_ehci_init(void)
{
struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
s5p_ehci_set_platdata(pdata);
}
static struct platform_device *smdkv310_devices[] __initdata = {
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
&s3c_device_i2c1,
&s5p_device_i2c_hdmiphy,
&s3c_device_rtc,
&s3c_device_wdt,
&s5p_device_ehci,
&s5p_device_fimc0,
&s5p_device_fimc1,
&s5p_device_fimc2,
&s5p_device_fimc3,
&exynos4_device_ac97,
&exynos4_device_i2s0,
&samsung_device_keypad,
&s5p_device_mfc,
&s5p_device_mfc_l,
&s5p_device_mfc_r,
&exynos4_device_pd[PD_MFC],
&exynos4_device_pd[PD_G3D],
&exynos4_device_pd[PD_LCD0],
@ -258,6 +280,8 @@ static struct platform_device *smdkv310_devices[] __initdata = {
&smdkv310_lcd_lte480wv,
&smdkv310_smsc911x,
&exynos4_device_ahci,
&s5p_device_hdmi,
&s5p_device_mixer,
};
static void __init smdkv310_smsc911x_init(void)
@ -294,6 +318,18 @@ static struct platform_pwm_backlight_data smdkv310_bl_data = {
.pwm_period_ns = 1000,
};
static void s5p_tv_setup(void)
{
/* direct HPD to HDMI chip */
WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
/* setup dependencies between TV devices */
s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
}
static void __init smdkv310_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@ -301,6 +337,11 @@ static void __init smdkv310_map_io(void)
s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
}
static void __init smdkv310_reserve(void)
{
s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
}
static void __init smdkv310_machine_init(void)
{
s3c_i2c1_set_platdata(NULL);
@ -313,12 +354,19 @@ static void __init smdkv310_machine_init(void)
s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
s5p_tv_setup();
s5p_i2c_hdmiphy_set_platdata(NULL);
samsung_keypad_set_platdata(&smdkv310_keypad_data);
samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
smdkv310_ehci_init();
clk_xusbxti.rate = 24000000;
platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
}
MACHINE_START(SMDKV310, "SMDKV310")
@ -329,6 +377,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
.map_io = smdkv310_map_io,
.init_machine = smdkv310_machine_init,
.timer = &exynos4_timer,
.reserve = &smdkv310_reserve,
MACHINE_END
MACHINE_START(SMDKC210, "SMDKC210")

307
arch/arm/mach-exynos4/mach-universal_c210.c
View File

@ -13,6 +13,7 @@
#include <linux/i2c.h>
#include <linux/gpio_keys.h>
#include <linux/gpio.h>
#include <linux/fb.h>
#include <linux/mfd/max8998.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
@ -31,12 +32,21 @@
#include <plat/devs.h>
#include <plat/iic.h>
#include <plat/gpio-cfg.h>
#include <plat/fb.h>
#include <plat/mfc.h>
#include <plat/sdhci.h>
#include <plat/pd.h>
#include <plat/regs-fb-v4.h>
#include <plat/fimc-core.h>
#include <plat/camport.h>
#include <plat/mipi_csis.h>
#include <mach/map.h>
#include <media/v4l2-mediabus.h>
#include <media/s5p_fimc.h>
#include <media/m5mols.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
@ -110,6 +120,9 @@ static struct regulator_consumer_supply lp3974_buck1_consumer =
static struct regulator_consumer_supply lp3974_buck2_consumer =
REGULATOR_SUPPLY("vddg3d", NULL);
static struct regulator_consumer_supply lp3974_buck3_consumer =
REGULATOR_SUPPLY("vdet", "s5p-sdo");
static struct regulator_init_data lp3974_buck1_data = {
.constraints = {
.name = "VINT_1.1V",
@ -153,6 +166,8 @@ static struct regulator_init_data lp3974_buck3_data = {
.enabled = 1,
},
},
.num_consumer_supplies = 1,
.consumer_supplies = &lp3974_buck3_consumer,
};
static struct regulator_init_data lp3974_buck4_data = {
@ -181,6 +196,12 @@ static struct regulator_init_data lp3974_ldo2_data = {
},
};
static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"),
};
static struct regulator_init_data lp3974_ldo3_data = {
.constraints = {
.name = "VUSB+MIPI_1.1V",
@ -192,6 +213,12 @@ static struct regulator_init_data lp3974_ldo3_data = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer),
.consumer_supplies = lp3974_ldo3_consumer,
};
static struct regulator_consumer_supply lp3974_ldo4_consumer[] = {
REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
};
static struct regulator_init_data lp3974_ldo4_data = {
@ -205,6 +232,8 @@ static struct regulator_init_data lp3974_ldo4_data = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer),
.consumer_supplies = lp3974_ldo4_consumer,
};
static struct regulator_init_data lp3974_ldo5_data = {
@ -233,6 +262,10 @@ static struct regulator_init_data lp3974_ldo6_data = {
},
};
static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"),
};
static struct regulator_init_data lp3974_ldo7_data = {
.constraints = {
.name = "VLCD+VMIPI_1.8V",
@ -244,6 +277,12 @@ static struct regulator_init_data lp3974_ldo7_data = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(lp3974_ldo7_consumer),
.consumer_supplies = lp3974_ldo7_consumer,
};
static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
};
static struct regulator_init_data lp3974_ldo8_data = {
@ -257,6 +296,8 @@ static struct regulator_init_data lp3974_ldo8_data = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer),
.consumer_supplies = lp3974_ldo8_consumer,
};
static struct regulator_init_data lp3974_ldo9_data = {
@ -286,6 +327,9 @@ static struct regulator_init_data lp3974_ldo10_data = {
},
};
static struct regulator_consumer_supply lp3974_ldo11_consumer =
REGULATOR_SUPPLY("dig_28", "0-001f");
static struct regulator_init_data lp3974_ldo11_data = {
.constraints = {
.name = "CAM_AF_3.3V",
@ -297,6 +341,8 @@ static struct regulator_init_data lp3974_ldo11_data = {
.disabled = 1,
},
},
.num_consumer_supplies = 1,
.consumer_supplies = &lp3974_ldo11_consumer,
};
static struct regulator_init_data lp3974_ldo12_data = {
@ -325,6 +371,9 @@ static struct regulator_init_data lp3974_ldo13_data = {
},
};
static struct regulator_consumer_supply lp3974_ldo14_consumer =
REGULATOR_SUPPLY("dig_18", "0-001f");
static struct regulator_init_data lp3974_ldo14_data = {
.constraints = {
.name = "CAM_I_HOST_1.8V",
@ -336,8 +385,14 @@ static struct regulator_init_data lp3974_ldo14_data = {
.disabled = 1,
},
},
.num_consumer_supplies = 1,
.consumer_supplies = &lp3974_ldo14_consumer,
};
static struct regulator_consumer_supply lp3974_ldo15_consumer =
REGULATOR_SUPPLY("dig_12", "0-001f");
static struct regulator_init_data lp3974_ldo15_data = {
.constraints = {
.name = "CAM_S_DIG+FM33_CORE_1.2V",
@ -349,6 +404,12 @@ static struct regulator_init_data lp3974_ldo15_data = {
.disabled = 1,
},
},
.num_consumer_supplies = 1,
.consumer_supplies = &lp3974_ldo15_consumer,
};
static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
REGULATOR_SUPPLY("a_sensor", "0-001f"),
};
static struct regulator_init_data lp3974_ldo16_data = {
@ -362,6 +423,8 @@ static struct regulator_init_data lp3974_ldo16_data = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(lp3974_ldo16_consumer),
.consumer_supplies = lp3974_ldo16_consumer,
};
static struct regulator_init_data lp3974_ldo17_data = {
@ -472,6 +535,43 @@ static struct max8998_platform_data universal_lp3974_pdata = {
.wakeup = true,
};
enum fixed_regulator_id {
FIXED_REG_ID_MMC0,
FIXED_REG_ID_HDMI_5V,
FIXED_REG_ID_CAM_S_IF,
FIXED_REG_ID_CAM_I_CORE,
FIXED_REG_ID_CAM_VT_DIO,
};
static struct regulator_consumer_supply hdmi_fixed_consumer =
REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi");
static struct regulator_init_data hdmi_fixed_voltage_init_data = {
.constraints = {
.name = "HDMI_5V",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &hdmi_fixed_consumer,
};
static struct fixed_voltage_config hdmi_fixed_voltage_config = {
.supply_name = "HDMI_EN1",
.microvolts = 5000000,
.gpio = EXYNOS4_GPE0(1),
.enable_high = true,
.init_data = &hdmi_fixed_voltage_init_data,
};
static struct platform_device hdmi_fixed_voltage = {
.name = "reg-fixed-voltage",
.id = FIXED_REG_ID_HDMI_5V,
.dev = {
.platform_data = &hdmi_fixed_voltage_config,
},
};
/* GPIO I2C 5 (PMIC) */
static struct i2c_board_info i2c5_devs[] __initdata = {
{
@ -573,6 +673,11 @@ static void __init universal_touchkey_init(void)
gpio_direction_output(gpio, 1);
}
static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
.frequency = 300 * 1000,
.sda_delay = 200,
};
/* GPIO KEYS */
static struct gpio_keys_button universal_gpio_keys_tables[] = {
{
@ -658,7 +763,7 @@ static struct fixed_voltage_config mmc0_fixed_voltage_config = {
static struct platform_device mmc0_fixed_voltage = {
.name = "reg-fixed-voltage",
.id = 0,
.id = FIXED_REG_ID_MMC0,
.dev = {
.platform_data = &mmc0_fixed_voltage_config,
},
@ -692,18 +797,165 @@ static void __init universal_sdhci_init(void)
s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
}
/* I2C0 */
static struct i2c_board_info i2c0_devs[] __initdata = {
/* Camera, To be updated */
};
/* I2C1 */
static struct i2c_board_info i2c1_devs[] __initdata = {
/* Gyro, To be updated */
};
/* Frame Buffer */
static struct s3c_fb_pd_win universal_fb_win0 = {
.win_mode = {
.left_margin = 16,
.right_margin = 16,
.upper_margin = 2,
.lower_margin = 28,
.hsync_len = 2,
.vsync_len = 1,
.xres = 480,
.yres = 800,
.refresh = 55,
},
.max_bpp = 32,
.default_bpp = 16,
};
static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
.win[0] = &universal_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
VIDCON0_CLKSEL_LCD,
.vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
| VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
};
static struct regulator_consumer_supply cam_i_core_supply =
REGULATOR_SUPPLY("core", "0-001f");
static struct regulator_init_data cam_i_core_reg_init_data = {
.constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
.num_consumer_supplies = 1,
.consumer_supplies = &cam_i_core_supply,
};
static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
.supply_name = "CAM_I_CORE_1.2V",
.microvolts = 1200000,
.gpio = EXYNOS4_GPE2(2), /* CAM_8M_CORE_EN */
.enable_high = 1,
.init_data = &cam_i_core_reg_init_data,
};
static struct platform_device cam_i_core_fixed_reg_dev = {
.name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE,
.dev = { .platform_data = &cam_i_core_fixed_voltage_cfg },
};
static struct regulator_consumer_supply cam_s_if_supply =
REGULATOR_SUPPLY("d_sensor", "0-001f");
static struct regulator_init_data cam_s_if_reg_init_data = {
.constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
.num_consumer_supplies = 1,
.consumer_supplies = &cam_s_if_supply,
};
static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
.supply_name = "CAM_S_IF_1.8V",
.microvolts = 1800000,
.gpio = EXYNOS4_GPE3(0), /* CAM_PWR_EN1 */
.enable_high = 1,
.init_data = &cam_s_if_reg_init_data,
};
static struct platform_device cam_s_if_fixed_reg_dev = {
.name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF,
.dev = { .platform_data = &cam_s_if_fixed_voltage_cfg },
};
static struct s5p_platform_mipi_csis mipi_csis_platdata = {
.clk_rate = 166000000UL,
.lanes = 2,
.alignment = 32,
.hs_settle = 12,
.phy_enable = s5p_csis_phy_enable,
};
#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3)
#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5) /* XEINT_13 */
#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5)
static int m5mols_set_power(struct device *dev, int on)
{
gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on);
gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
return 0;
}
static struct m5mols_platform_data m5mols_platdata = {
.gpio_reset = GPIO_CAM_MEGA_nRST,
.reset_polarity = 0,
.set_power = m5mols_set_power,
};
static struct i2c_board_info m5mols_board_info = {
I2C_BOARD_INFO("M5MOLS", 0x1F),
.platform_data = &m5mols_platdata,
};
static struct s5p_fimc_isp_info universal_camera_sensors[] = {
{
.mux_id = 0,
.flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
V4L2_MBUS_VSYNC_ACTIVE_LOW,
.bus_type = FIMC_MIPI_CSI2,
.board_info = &m5mols_board_info,
.i2c_bus_num = 0,
.clk_frequency = 21600000UL,
.csi_data_align = 32,
},
};
static struct s5p_platform_fimc fimc_md_platdata = {
.isp_info = universal_camera_sensors,
.num_clients = ARRAY_SIZE(universal_camera_sensors),
};
static struct gpio universal_camera_gpios[] = {
{ GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" },
{ GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW, "CAM_LVL_EN2" },
{ GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
{ GPIO_CAM_MEGA_nRST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
};
static void universal_camera_init(void)
{
s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
&s5p_device_mipi_csis0);
s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata),
&s5p_device_fimc_md);
if (gpio_request_array(universal_camera_gpios,
ARRAY_SIZE(universal_camera_gpios))) {
pr_err("%s: GPIO request failed\n", __func__);
return;
}
if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf)))
m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT);
else
pr_err("Failed to configure 8M_ISP_INT GPIO\n");
/* Free GPIOs controlled directly by the sensor drivers. */
gpio_free(GPIO_CAM_MEGA_nRST);
gpio_free(GPIO_CAM_8M_ISP_INT);
if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
pr_err("Camera port A setup failed\n");
}
static struct platform_device *universal_devices[] __initdata = {
/* Samsung Platform Devices */
&s5p_device_mipi_csis0,
&s5p_device_fimc0,
&s5p_device_fimc1,
&s5p_device_fimc2,
@ -712,17 +964,30 @@ static struct platform_device *universal_devices[] __initdata = {
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
&s3c_device_i2c0,
&s3c_device_i2c3,
&s3c_device_i2c5,
&s5p_device_i2c_hdmiphy,
&hdmi_fixed_voltage,
&exynos4_device_pd[PD_TV],
&s5p_device_hdmi,
&s5p_device_sdo,
&s5p_device_mixer,
/* Universal Devices */
&i2c_gpio12,
&universal_gpio_keys,
&s5p_device_onenand,
&s5p_device_fimd0,
&s5p_device_mfc,
&s5p_device_mfc_l,
&s5p_device_mfc_r,
&exynos4_device_pd[PD_MFC],
&exynos4_device_pd[PD_LCD0],
&exynos4_device_pd[PD_CAM],
&cam_i_core_fixed_reg_dev,
&cam_s_if_fixed_reg_dev,
&s5p_device_fimc_md,
};
static void __init universal_map_io(void)
@ -732,6 +997,20 @@ static void __init universal_map_io(void)
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
}
void s5p_tv_setup(void)
{
/* direct HPD to HDMI chip */
gpio_request(EXYNOS4_GPX3(7), "hpd-plug");
gpio_direction_input(EXYNOS4_GPX3(7));
s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
/* setup dependencies between TV devices */
s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
}
static void __init universal_reserve(void)
{
s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
@ -740,8 +1019,9 @@ static void __init universal_reserve(void)
static void __init universal_machine_init(void)
{
universal_sdhci_init();
s5p_tv_setup();
i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
s3c_i2c0_set_platdata(&universal_i2c0_platdata);
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
universal_tsp_init();
@ -749,15 +1029,28 @@ static void __init universal_machine_init(void)
i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
s3c_i2c5_set_platdata(NULL);
s5p_i2c_hdmiphy_set_platdata(NULL);
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
s5p_fimd0_set_platdata(&universal_lcd_pdata);
universal_touchkey_init();
i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
ARRAY_SIZE(i2c_gpio12_devs));
universal_camera_init();
/* Last */
platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
}
MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")

7
arch/arm/mach-exynos4/pm.c
View File

@ -339,6 +339,13 @@ static int exynos4_pm_suspend(void)
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
if (soc_is_exynos4212()) {
tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
S5P_USE_STANDBYWFE_ISP_ARM);
__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
}
/* Save Power control register */
asm ("mrc p15, 0, %0, c15, c0, 0"
: "=r" (tmp) : : "cc");

353
arch/arm/mach-exynos4/pmu.c
View File

@ -16,160 +16,215 @@
#include <mach/regs-clock.h>
#include <mach/pmu.h>
static void __iomem *sys_powerdown_reg[] = {
S5P_ARM_CORE0_LOWPWR,
S5P_DIS_IRQ_CORE0,
S5P_DIS_IRQ_CENTRAL0,
S5P_ARM_CORE1_LOWPWR,
S5P_DIS_IRQ_CORE1,
S5P_DIS_IRQ_CENTRAL1,
S5P_ARM_COMMON_LOWPWR,
S5P_L2_0_LOWPWR,
S5P_L2_1_LOWPWR,
S5P_CMU_ACLKSTOP_LOWPWR,
S5P_CMU_SCLKSTOP_LOWPWR,
S5P_CMU_RESET_LOWPWR,
S5P_APLL_SYSCLK_LOWPWR,
S5P_MPLL_SYSCLK_LOWPWR,
S5P_VPLL_SYSCLK_LOWPWR,
S5P_EPLL_SYSCLK_LOWPWR,
S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
S5P_CMU_RESET_GPSALIVE_LOWPWR,
S5P_CMU_CLKSTOP_CAM_LOWPWR,
S5P_CMU_CLKSTOP_TV_LOWPWR,
S5P_CMU_CLKSTOP_MFC_LOWPWR,
S5P_CMU_CLKSTOP_G3D_LOWPWR,
S5P_CMU_CLKSTOP_LCD0_LOWPWR,
S5P_CMU_CLKSTOP_LCD1_LOWPWR,
S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
S5P_CMU_CLKSTOP_GPS_LOWPWR,
S5P_CMU_RESET_CAM_LOWPWR,
S5P_CMU_RESET_TV_LOWPWR,
S5P_CMU_RESET_MFC_LOWPWR,
S5P_CMU_RESET_G3D_LOWPWR,
S5P_CMU_RESET_LCD0_LOWPWR,
S5P_CMU_RESET_LCD1_LOWPWR,
S5P_CMU_RESET_MAUDIO_LOWPWR,
S5P_CMU_RESET_GPS_LOWPWR,
S5P_TOP_BUS_LOWPWR,
S5P_TOP_RETENTION_LOWPWR,
S5P_TOP_PWR_LOWPWR,
S5P_LOGIC_RESET_LOWPWR,
S5P_ONENAND_MEM_LOWPWR,
S5P_MODIMIF_MEM_LOWPWR,
S5P_G2D_ACP_MEM_LOWPWR,
S5P_USBOTG_MEM_LOWPWR,
S5P_HSMMC_MEM_LOWPWR,
S5P_CSSYS_MEM_LOWPWR,
S5P_SECSS_MEM_LOWPWR,
S5P_PCIE_MEM_LOWPWR,
S5P_SATA_MEM_LOWPWR,
S5P_PAD_RETENTION_DRAM_LOWPWR,
S5P_PAD_RETENTION_MAUDIO_LOWPWR,
S5P_PAD_RETENTION_GPIO_LOWPWR,
S5P_PAD_RETENTION_UART_LOWPWR,
S5P_PAD_RETENTION_MMCA_LOWPWR,
S5P_PAD_RETENTION_MMCB_LOWPWR,
S5P_PAD_RETENTION_EBIA_LOWPWR,
S5P_PAD_RETENTION_EBIB_LOWPWR,
S5P_PAD_RETENTION_ISOLATION_LOWPWR,
S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
S5P_XUSBXTI_LOWPWR,
S5P_XXTI_LOWPWR,
S5P_EXT_REGULATOR_LOWPWR,
S5P_GPIO_MODE_LOWPWR,
S5P_GPIO_MODE_MAUDIO_LOWPWR,
S5P_CAM_LOWPWR,
S5P_TV_LOWPWR,
S5P_MFC_LOWPWR,
S5P_G3D_LOWPWR,
S5P_LCD0_LOWPWR,
S5P_LCD1_LOWPWR,
S5P_MAUDIO_LOWPWR,
S5P_GPS_LOWPWR,
S5P_GPS_ALIVE_LOWPWR,
static struct exynos4_pmu_conf *exynos4_pmu_config;
static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
{ S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
{ S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
{ S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } },
{ S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } },
{ S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
{ S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
{ S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
{ S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
{ S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
{ S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
{ S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
{ S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } },
{ S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
{ S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
{ S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
{ PMU_TABLE_END,},
};
static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
/* { AFTR, LPA, SLEEP }*/
{ 0, 0, 2 }, /* ARM_CORE0 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */
{ 0, 0, 2 }, /* ARM_CORE1 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */
{ 0, 0, 2 }, /* ARM_COMMON */
{ 2, 2, 3 }, /* ARM_CPU_L2_0 */
{ 2, 2, 3 }, /* ARM_CPU_L2_1 */
{ 1, 0, 0 }, /* CMU_ACLKSTOP */
{ 1, 0, 0 }, /* CMU_SCLKSTOP */
{ 1, 1, 0 }, /* CMU_RESET */
{ 1, 0, 0 }, /* APLL_SYSCLK */
{ 1, 0, 0 }, /* MPLL_SYSCLK */
{ 1, 0, 0 }, /* VPLL_SYSCLK */
{ 1, 1, 0 }, /* EPLL_SYSCLK */
{ 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */
{ 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */
{ 1, 1, 0 }, /* CMU_CLKSTOP_CAM */
{ 1, 1, 0 }, /* CMU_CLKSTOP_TV */
{ 1, 1, 0 }, /* CMU_CLKSTOP_MFC */
{ 1, 1, 0 }, /* CMU_CLKSTOP_G3D */
{ 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */
{ 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */
{ 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */
{ 1, 1, 0 }, /* CMU_CLKSTOP_GPS */
{ 1, 1, 0 }, /* CMU_RESET_CAM */
{ 1, 1, 0 }, /* CMU_RESET_TV */
{ 1, 1, 0 }, /* CMU_RESET_MFC */
{ 1, 1, 0 }, /* CMU_RESET_G3D */
{ 1, 1, 0 }, /* CMU_RESET_LCD0 */
{ 1, 1, 0 }, /* CMU_RESET_LCD1 */
{ 1, 1, 0 }, /* CMU_RESET_MAUDIO */
{ 1, 1, 0 }, /* CMU_RESET_GPS */
{ 3, 0, 0 }, /* TOP_BUS */
{ 1, 0, 1 }, /* TOP_RETENTION */
{ 3, 0, 3 }, /* TOP_PWR */
{ 1, 1, 0 }, /* LOGIC_RESET */
{ 3, 0, 0 }, /* ONENAND_MEM */
{ 3, 0, 0 }, /* MODIMIF_MEM */
{ 3, 0, 0 }, /* G2D_ACP_MEM */
{ 3, 0, 0 }, /* USBOTG_MEM */
{ 3, 0, 0 }, /* HSMMC_MEM */
{ 3, 0, 0 }, /* CSSYS_MEM */
{ 3, 0, 0 }, /* SECSS_MEM */
{ 3, 0, 0 }, /* PCIE_MEM */
{ 3, 0, 0 }, /* SATA_MEM */
{ 1, 0, 0 }, /* PAD_RETENTION_DRAM */
{ 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */
{ 1, 0, 0 }, /* PAD_RETENTION_GPIO */
{ 1, 0, 0 }, /* PAD_RETENTION_UART */
{ 1, 0, 0 }, /* PAD_RETENTION_MMCA */
{ 1, 0, 0 }, /* PAD_RETENTION_MMCB */
{ 1, 0, 0 }, /* PAD_RETENTION_EBIA */
{ 1, 0, 0 }, /* PAD_RETENTION_EBIB */
{ 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */
{ 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */
{ 1, 1, 0 }, /* XUSBXTI */
{ 1, 1, 0 }, /* XXTI */
{ 1, 1, 0 }, /* EXT_REGULATOR */
{ 1, 0, 0 }, /* GPIO_MODE */
{ 1, 1, 0 }, /* GPIO_MODE_MAUDIO */
{ 7, 0, 0 }, /* CAM */
{ 7, 0, 0 }, /* TV */
{ 7, 0, 0 }, /* MFC */
{ 7, 0, 0 }, /* G3D */
{ 7, 0, 0 }, /* LCD0 */
{ 7, 0, 0 }, /* LCD1 */
{ 7, 7, 0 }, /* MAUDIO */
{ 7, 0, 0 }, /* GPS */
{ 7, 0, 0 }, /* GPS_ALIVE */
static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
{ S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
{ S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
{ S5P_ISP_ARM_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR, { 0x0, 0x0, 0x0 } },
{ S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR, { 0x0, 0x0, 0x0 } },
{ S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_L2_0_LOWPWR, { 0x0, 0x0, 0x3 } },
/* XXX_OPTION register should be set other field */
{ S5P_ARM_L2_0_OPTION, { 0x10, 0x10, 0x0 } },
{ S5P_L2_1_LOWPWR, { 0x0, 0x0, 0x3 } },
{ S5P_ARM_L2_1_OPTION, { 0x10, 0x10, 0x0 } },
{ S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_DRAM_FREQ_DOWN_LOWPWR, { 0x1, 0x1, 0x1 } },
{ S5P_DDRPHY_DLLOFF_LOWPWR, { 0x1, 0x1, 0x1 } },
{ S5P_LPDDR_PHY_DLL_LOCK_LOWPWR, { 0x1, 0x1, 0x1 } },
{ S5P_CMU_ACLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_SCLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_MPLLUSER_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_CLKSTOP_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
{ S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
{ S5P_TOP_BUS_COREBLK_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_TOP_RETENTION_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
{ S5P_TOP_PWR_COREBLK_LOWPWR, { 0x3, 0x0, 0x3 } },
{ S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_OSCCLK_GATE_LOWPWR, { 0x1, 0x0, 0x1 } },
{ S5P_LOGIC_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_OSCCLK_GATE_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
{ S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_ONENAND_MEM_OPTION, { 0x10, 0x10, 0x0 } },
{ S5P_HSI_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_HSI_MEM_OPTION, { 0x10, 0x10, 0x0 } },
{ S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_G2D_ACP_MEM_OPTION, { 0x10, 0x10, 0x0 } },
{ S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_USBOTG_MEM_OPTION, { 0x10, 0x10, 0x0 } },
{ S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_HSMMC_MEM_OPTION, { 0x10, 0x10, 0x0 } },
{ S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_CSSYS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
{ S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_SECSS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
{ S5P_ROTATOR_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
{ S5P_ROTATOR_MEM_OPTION, { 0x10, 0x10, 0x0 } },
{ S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_ISOLATION_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_GPIO_MODE_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_TOP_ASB_RESET_LOWPWR, { 0x1, 0x1, 0x1 } },
{ S5P_TOP_ASB_ISOLATION_LOWPWR, { 0x1, 0x0, 0x1 } },
{ S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
{ S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
{ S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
{ S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
{ S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
{ S5P_ISP_LOWPWR, { 0x7, 0x0, 0x0 } },
{ S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
{ S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
{ S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
{ S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
{ PMU_TABLE_END,},
};
void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
{
unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
unsigned int i;
for (; count > 0; count--)
__raw_writel(sys_powerdown_val[count - 1][mode],
sys_powerdown_reg[count - 1]);
for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
__raw_writel(exynos4_pmu_config[i].val[mode],
exynos4_pmu_config[i].reg);
}
static int __init exynos4_pmu_init(void)
{
exynos4_pmu_config = exynos4210_pmu_config;
if (soc_is_exynos4210()) {
exynos4_pmu_config = exynos4210_pmu_config;
pr_info("EXYNOS4210 PMU Initialize\n");
} else if (soc_is_exynos4212()) {
exynos4_pmu_config = exynos4212_pmu_config;
pr_info("EXYNOS4212 PMU Initialize\n");
} else {
pr_info("EXYNOS4: PMU not supported\n");
}
return 0;
}
arch_initcall(exynos4_pmu_init);

47
arch/arm/mach-exynos4/setup-sdhci.c
View File

@ -10,16 +10,7 @@
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <plat/regs-sdhci.h>
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
@ -29,41 +20,3 @@ char *exynos4_hsmmc_clksrcs[4] = {
[2] = "sclk_mmc", /* mmc_bus */
[3] = NULL,
};
void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
struct mmc_ios *ios, struct mmc_card *card)
{
u32 ctrl2, ctrl3;
/* don't need to alter anything according to card-type */
ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
/* select base clock source to HCLK */
ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
/*
* clear async mode, enable conflict mask, rx feedback ctrl, SD
* clk hold and no use debounce count
*/
ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
S3C_SDHCI_CTRL2_ENFBCLKRX |
S3C_SDHCI_CTRL2_DFCNT_NONE |
S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
/* Tx and Rx feedback clock delay control */
if (ios->clock < 25 * 1000000)
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
S3C_SDHCI_CTRL3_FCSEL2 |
S3C_SDHCI_CTRL3_FCSEL1 |
S3C_SDHCI_CTRL3_FCSEL0);
else
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
writel(ctrl2, r + S3C_SDHCI_CONTROL2);
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
}

1
arch/arm/mach-s3c2410/Kconfig
View File

@ -6,7 +6,6 @@ config CPU_S3C2410
bool
depends on ARCH_S3C2410
select CPU_ARM920T
select S3C_GPIO_PULL_UP
select S3C2410_CLOCK
select CPU_LLSERIAL_S3C2410
select S3C2410_PM if PM

75
arch/arm/mach-s3c2410/include/mach/fb.h
View File

@ -1,74 +1 @@
/* arch/arm/mach-s3c2410/include/mach/fb.h
*
* Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
*
* Inspired by pxafb.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_FB_H
#define __ASM_ARM_FB_H
#include <mach/regs-lcd.h>
struct s3c2410fb_hw {
unsigned long lcdcon1;
unsigned long lcdcon2;
unsigned long lcdcon3;
unsigned long lcdcon4;
unsigned long lcdcon5;
};
/* LCD description */
struct s3c2410fb_display {
/* LCD type */
unsigned type;
/* Screen size */
unsigned short width;
unsigned short height;
/* Screen info */
unsigned short xres;
unsigned short yres;
unsigned short bpp;
unsigned pixclock; /* pixclock in picoseconds */
unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */
unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */
unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */
unsigned short upper_margin; /* value in lines (TFT) or 0 (STN) */
unsigned short lower_margin; /* value in lines (TFT) or 0 (STN) */
unsigned short vsync_len; /* value in lines (TFT) or 0 (STN) */
/* lcd configuration registers */
unsigned long lcdcon5;
};
struct s3c2410fb_mach_info {
struct s3c2410fb_display *displays; /* attached diplays info */
unsigned num_displays; /* number of defined displays */
unsigned default_display;
/* GPIOs */
unsigned long gpcup;
unsigned long gpcup_mask;
unsigned long gpccon;
unsigned long gpccon_mask;
unsigned long gpdup;
unsigned long gpdup_mask;
unsigned long gpdcon;
unsigned long gpdcon_mask;
/* lpc3600 control register */
unsigned long lpcsel;
};
extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
#endif /* __ASM_ARM_FB_H */
#include <plat/fb-s3c2410.h>

99
arch/arm/mach-s3c2410/include/mach/gpio-fns.h
View File

@ -1,98 +1 @@
/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
*
* Copyright (c) 2003-2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - hardware
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MACH_GPIO_FNS_H
#define __MACH_GPIO_FNS_H __FILE__
/* These functions are in the to-be-removed category and it is strongly
* encouraged not to use these in new code. They will be marked deprecated
* very soon.
*
* Most of the functionality can be either replaced by the gpiocfg calls
* for the s3c platform or by the generic GPIOlib API.
*
* As of 2.6.35-rc, these will be removed, with the few drivers using them
* either replaced or given a wrapper until the calls can be removed.
*/
#include <plat/gpio-cfg.h>
static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg)
{
/* 1:1 mapping between cfgpin and setcfg calls at the moment */
s3c_gpio_cfgpin(pin, cfg);
}
/* external functions for GPIO support
*
* These allow various different clients to access the same GPIO
* registers without conflicting. If your driver only owns the entire
* GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
*/
extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
/* s3c2410_gpio_getirq
*
* turn the given pin number into the corresponding IRQ number
*
* returns:
* < 0 = no interrupt for this pin
* >=0 = interrupt number for the pin
*/
extern int s3c2410_gpio_getirq(unsigned int pin);
/* s3c2410_gpio_irqfilter
*
* set the irq filtering on the given pin
*
* on = 0 => disable filtering
* 1 => enable filtering
*
* config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
* width of filter (0 through 63)
*
*
*/
extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
unsigned int config);
/* s3c2410_gpio_pullup
*
* This call should be replaced with s3c_gpio_setpull().
*
* As a note, there is currently no distinction between pull-up and pull-down
* in the s3c24xx series devices with only an on/off configuration.
*/
/* s3c2410_gpio_pullup
*
* configure the pull-up control on the given pin
*
* to = 1 => disable the pull-up
* 0 => enable the pull-up
*
* eg;
*
* s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
* s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
*/
extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
#endif /* __MACH_GPIO_FNS_H */
#include <plat/gpio-fns.h>

6
arch/arm/mach-s3c2410/include/mach/gpio-track.h
View File

@ -17,11 +17,11 @@
#include <mach/regs-gpio.h>
extern struct s3c_gpio_chip s3c24xx_gpios[];
extern struct samsung_gpio_chip s3c24xx_gpios[];
static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin)
{
struct s3c_gpio_chip *chip;
struct samsung_gpio_chip *chip;
if (pin > S3C_GPIO_END)
return NULL;

4
arch/arm/mach-s3c2410/include/mach/irqs.h
View File

@ -191,9 +191,9 @@
#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2
#ifdef CONFIG_CPU_S3C2440
#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97
#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97
#else
#define IRQ_S3C244x_AC97 IRQ_S3C2443_AC97
#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97
#endif
/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */

1
arch/arm/mach-s3c2410/include/mach/map.h
View File

@ -149,6 +149,7 @@
#define S3C24XX_PA_RTC S3C2410_PA_RTC
#define S3C24XX_PA_ADC S3C2410_PA_ADC
#define S3C24XX_PA_SPI S3C2410_PA_SPI
#define S3C24XX_PA_SPI1 (S3C2410_PA_SPI + S3C2410_SPI1)
#define S3C24XX_PA_SDI S3C2410_PA_SDI
#define S3C24XX_PA_NAND S3C2410_PA_NAND

2
arch/arm/mach-s3c2410/include/mach/pm-core.h
View File

@ -64,4 +64,4 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
}
static inline void s3c_pm_restored_gpios(void) { }
static inline void s3c_pm_saved_gpios(void) { }
static inline void samsung_pm_saved_gpios(void) { }

1
arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
View File

@ -102,6 +102,7 @@
#define S3C2443_PCLKCON_UART3 (1<<3)
#define S3C2443_PCLKCON_IIC (1<<4)
#define S3C2443_PCLKCON_SDI (1<<5)
#define S3C2443_PCLKCON_HSSPI (1<<6)
#define S3C2443_PCLKCON_ADC (1<<7)
#define S3C2443_PCLKCON_AC97 (1<<8)
#define S3C2443_PCLKCON_IIS (1<<9)

6
arch/arm/mach-s3c2410/mach-h1940.c
View File

@ -696,9 +696,9 @@ static void __init h1940_init(void)
S3C2410_MISCCR_USBSUSPND0 |
S3C2410_MISCCR_USBSUSPND1, 0x0);
tmp = (0x78 << S3C24XX_PLLCON_MDIVSHIFT)
| (0x02 << S3C24XX_PLLCON_PDIVSHIFT)
| (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
tmp = (0x78 << S3C24XX_PLL_MDIV_SHIFT)
| (0x02 << S3C24XX_PLL_PDIV_SHIFT)
| (0x03 << S3C24XX_PLL_SDIV_SHIFT);
writel(tmp, S3C2410_UPLLCON);
gpio_request(S3C2410_GPC(0), "LCD power");

1
arch/arm/mach-s3c2410/mach-qt2410.c
View File

@ -49,6 +49,7 @@
#include <mach/regs-gpio.h>
#include <mach/leds-gpio.h>
#include <mach/regs-lcd.h>
#include <plat/regs-serial.h>
#include <mach/fb.h>
#include <plat/nand.h>

4
arch/arm/mach-s3c2410/s3c2410.c
View File

@ -72,8 +72,8 @@ void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
void __init s3c2410_map_io(void)
{
s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;
iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
}

62
arch/arm/mach-s3c2412/gpio.c Normal file
View File

@ -0,0 +1,62 @@
/* linux/arch/arm/mach-s3c2412/gpio.c
*
* Copyright (c) 2007 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* http://armlinux.simtec.co.uk/.
*
* S3C2412/S3C2413 specific GPIO support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/regs-gpio.h>
#include <mach/hardware.h>
#include <plat/gpio-core.h>
int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
{
struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
unsigned long offs = pin - chip->chip.base;
unsigned long flags;
unsigned long slpcon;
offs *= 2;
if (pin < S3C2410_GPB(0))
return -EINVAL;
if (pin >= S3C2410_GPF(0) &&
pin <= S3C2410_GPG(16))
return -EINVAL;
if (pin > S3C2410_GPH(16))
return -EINVAL;
local_irq_save(flags);
slpcon = __raw_readl(chip->base + 0x0C);
slpcon &= ~(3 << offs);
slpcon |= state << offs;
__raw_writel(slpcon, chip->base + 0x0C);
local_irq_restore(flags);
return 0;
}
EXPORT_SYMBOL(s3c2412_gpio_set_sleepcfg);

1
arch/arm/mach-s3c2416/Kconfig
View File

@ -13,7 +13,6 @@ config CPU_S3C2416
select CPU_ARM926T
select S3C2416_DMA if S3C2410_DMA
select CPU_LLSERIAL_S3C2440
select S3C_GPIO_PULL_UPDOWN
select SAMSUNG_CLKSRC
select S3C2443_CLOCK
help

29
arch/arm/mach-s3c2416/clock.c
View File

@ -21,7 +21,6 @@
#include <plat/cpu.h>
#include <plat/cpu-freq.h>
#include <plat/pll6553x.h>
#include <plat/pll.h>
#include <asm/mach/map.h>
@ -38,6 +37,32 @@ static unsigned int armdiv[8] = {
[7] = 8,
};
static struct clksrc_clk hsspi_eplldiv = {
.clk = {
.name = "hsspi-eplldiv",
.parent = &clk_esysclk.clk,
.ctrlbit = (1 << 14),
.enable = s3c2443_clkcon_enable_s,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
};
static struct clk *hsspi_sources[] = {
[0] = &hsspi_eplldiv.clk,
[1] = NULL, /* to fix */
};
static struct clksrc_clk hsspi_mux = {
.clk = {
.name = "hsspi-if",
},
.sources = &(struct clksrc_sources) {
.sources = hsspi_sources,
.nr_sources = ARRAY_SIZE(hsspi_sources),
},
.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
};
static struct clksrc_clk hsmmc_div[] = {
[0] = {
.clk = {
@ -114,6 +139,8 @@ void __init_or_cpufreq s3c2416_setup_clocks(void)
static struct clksrc_clk *clksrcs[] __initdata = {
&hsspi_eplldiv,
&hsspi_mux,
&hsmmc_div[0],
&hsmmc_div[1],
&hsmmc_mux[0],

4
arch/arm/mach-s3c2416/s3c2416.c
View File

@ -120,8 +120,8 @@ void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
void __init s3c2416_map_io(void)
{
s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
s3c24xx_gpiocfg_default.set_pull = samsung_gpio_setpull_updown;
s3c24xx_gpiocfg_default.get_pull = samsung_gpio_getpull_updown;
/* initialize device information early */
s3c2416_default_sdhci0();

37
arch/arm/mach-s3c2416/setup-sdhci.c
View File

@ -12,17 +12,7 @@
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <plat/regs-sdhci.h>
#include <plat/sdhci.h>
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
@ -32,30 +22,3 @@ char *s3c2416_hsmmc_clksrcs[4] = {
[2] = "hsmmc-if",
/* [3] = "48m", - note not successfully used yet */
};
void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card)
{
u32 ctrl2, ctrl3;
ctrl2 = __raw_readl(r + S3C_SDHCI_CONTROL2);
ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
S3C_SDHCI_CTRL2_ENFBCLKRX |
S3C_SDHCI_CTRL2_DFCNT_NONE |
S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
if (ios->clock < 25 * 1000000)
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
S3C_SDHCI_CTRL3_FCSEL2 |
S3C_SDHCI_CTRL3_FCSEL1 |
S3C_SDHCI_CTRL3_FCSEL0);
else
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
__raw_writel(ctrl2, r + S3C_SDHCI_CONTROL2);
__raw_writel(ctrl3, r + S3C_SDHCI_CONTROL3);
}

2
arch/arm/mach-s3c2440/Kconfig
View File

@ -5,7 +5,6 @@
config CPU_S3C2440
bool
select CPU_ARM920T
select S3C_GPIO_PULL_UP
select S3C2410_CLOCK
select S3C2410_PM if PM
select S3C2440_DMA if S3C2410_DMA
@ -17,7 +16,6 @@ config CPU_S3C2440
config CPU_S3C2442
bool
select CPU_ARM920T
select S3C_GPIO_PULL_DOWN
select S3C2410_CLOCK
select S3C2410_PM if PM
select CPU_S3C244X

1
arch/arm/mach-s3c2440/mach-rx1950.c
View File

@ -43,6 +43,7 @@
#include <mach/regs-gpio.h>
#include <mach/regs-gpioj.h>
#include <mach/regs-lcd.h>
#include <mach/h1940.h>
#include <mach/fb.h>

4
arch/arm/mach-s3c2440/s3c2440.c
View File

@ -70,6 +70,6 @@ void __init s3c2440_map_io(void)
{
s3c244x_map_io();
s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;
}

4
arch/arm/mach-s3c2440/s3c2442.c
View File

@ -182,6 +182,6 @@ void __init s3c2442_map_io(void)
{
s3c244x_map_io();
s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1down;
s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1down;
s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1down;
s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1down;
}

1
arch/arm/mach-s3c2443/Kconfig
View File

@ -10,7 +10,6 @@ config CPU_S3C2443
select CPU_LLSERIAL_S3C2440
select SAMSUNG_CLKSRC
select S3C2443_CLOCK
select S3C_GPIO_PULL_S3C2443
help
Support for the S3C2443 SoC from the S3C24XX line

55
arch/arm/mach-s3c2443/clock.c
View File

@ -57,10 +57,6 @@
/* clock selections */
static struct clk clk_i2s_ext = {
.name = "i2s-ext",
};
/* armdiv
*
* this clock is sourced from msysclk and can have a number of
@ -173,7 +169,7 @@ static struct clksrc_clk clk_arm = {
static struct clksrc_clk clk_hsspi = {
.clk = {
.name = "hsspi",
.name = "hsspi-if",
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_HSSPICLK,
.enable = s3c2443_clkcon_enable_s,
@ -235,48 +231,6 @@ static struct clk clk_hsmmc = {
},
};
/* i2s_eplldiv
*
* This clock is the output from the I2S divisor of ESYSCLK, and is separate
* from the mux that comes after it (cannot merge into one single clock)
*/
static struct clksrc_clk clk_i2s_eplldiv = {
.clk = {
.name = "i2s-eplldiv",
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
};
/* i2s-ref
*
* i2s bus reference clock, selectable from external, esysclk or epllref
*
* Note, this used to be two clocks, but was compressed into one.
*/
struct clk *clk_i2s_srclist[] = {
[0] = &clk_i2s_eplldiv.clk,
[1] = &clk_i2s_ext,
[2] = &clk_epllref.clk,
[3] = &clk_epllref.clk,
};
static struct clksrc_clk clk_i2s = {
.clk = {
.name = "i2s-if",
.ctrlbit = S3C2443_SCLKCON_I2SCLK,
.enable = s3c2443_clkcon_enable_s,
},
.sources = &(struct clksrc_sources) {
.sources = clk_i2s_srclist,
.nr_sources = ARRAY_SIZE(clk_i2s_srclist),
},
.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
};
/* standard clock definitions */
static struct clk init_clocks_off[] = {
@ -285,11 +239,6 @@ static struct clk init_clocks_off[] = {
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SDI,
}, {
.name = "iis",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_IIS,
}, {
.name = "spi",
.devname = "s3c2410-spi.0",
@ -312,8 +261,6 @@ static struct clk init_clocks[] = {
static struct clksrc_clk *clksrcs[] __initdata = {
&clk_arm,
&clk_i2s_eplldiv,
&clk_i2s,
&clk_hsspi,
&clk_hsmmc_div,
};

4
arch/arm/mach-s3c2443/s3c2443.c
View File

@ -90,8 +90,8 @@ void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no)
void __init s3c2443_map_io(void)
{
s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_s3c2443;
s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_s3c2443;
s3c24xx_gpiocfg_default.set_pull = s3c2443_gpio_setpull;
s3c24xx_gpiocfg_default.get_pull = s3c2443_gpio_getpull;
iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
}

1
arch/arm/mach-s3c64xx/Kconfig
View File

@ -288,5 +288,6 @@ config MACH_WLF_CRAGG_6410
select S3C_DEV_RTC
select S3C64XX_DEV_SPI
select S3C24XX_GPIO_EXTRA128
select I2C
help
Machine support for the Wolfson Cragganmore S3C6410 variant.

5
arch/arm/mach-s3c64xx/Makefile
View File

@ -13,7 +13,6 @@ obj- :=
# Core files
obj-y += cpu.o
obj-y += clock.o
obj-y += gpiolib.o
# Core support for S3C6400 system
@ -55,12 +54,10 @@ obj-$(CONFIG_MACH_HMT) += mach-hmt.o
obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o
obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o
obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o
obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o
obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
# device support
obj-y += dev-uart.o
obj-y += dev-audio.o
obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
obj-$(CONFIG_S3C64XX_DEV_TS) += dev-ts.o
obj-$(CONFIG_S3C64XX_DEV_ONENAND1) += dev-onenand1.o

13
arch/arm/mach-s3c64xx/clock.c
View File

@ -25,13 +25,13 @@
#include <mach/regs-sys.h>
#include <mach/regs-clock.h>
#include <mach/pll.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/clock-clksrc.h>
#include <plat/pll.h>
/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
* ext_xtal_mux for want of an actual name from the manual.
@ -735,7 +735,8 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
/* For now assume the mux always selects the crystal */
clk_ext_xtal_mux.parent = xtal_clk;
epll = s3c6400_get_epll(xtal);
epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
__raw_readl(S3C_EPLL_CON1));
mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
@ -744,7 +745,13 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
apll, mpll, epll);
hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
/* Synchronous mode */
hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
else
/* Asynchronous mode */
hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);

4
arch/arm/mach-s3c64xx/cpu.c
View File

@ -34,8 +34,8 @@
#include <plat/devs.h>
#include <plat/clock.h>
#include <mach/s3c6400.h>
#include <mach/s3c6410.h>
#include <plat/s3c6400.h>
#include <plat/s3c6410.h>
/* table of supported CPUs */

53
arch/arm/mach-s3c64xx/dev-onenand1.c
View File

@ -1,53 +0,0 @@
/*
* linux/arch/arm/mach-s3c64xx/dev-onenand1.c
*
* Copyright (c) 2008-2010 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* S3C64XX series device definition for OneNAND devices
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
#include <mach/irqs.h>
#include <mach/map.h>
#include <plat/devs.h>
static struct resource s3c64xx_onenand1_resources[] = {
[0] = {
.start = S3C64XX_PA_ONENAND1,
.end = S3C64XX_PA_ONENAND1 + 0x400 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = S3C64XX_PA_ONENAND1_BUF,
.end = S3C64XX_PA_ONENAND1_BUF + S3C64XX_SZ_ONENAND1_BUF - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = IRQ_ONENAND1,
.end = IRQ_ONENAND1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device s3c64xx_device_onenand1 = {
.name = "samsung-onenand",
.id = 1,
.num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
.resource = s3c64xx_onenand1_resources,
};
void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
{
s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
&s3c64xx_device_onenand1);
}

2
arch/arm/mach-s3c64xx/dma.c
View File

@ -740,7 +740,7 @@ static int __init s3c64xx_dma_init(void)
}
/* Set all DMA configuration to be DMA, not SDMA */
writel(0xffffff, S3C_SYSREG(0x110));
writel(0xffffff, S3C64XX_SDMA_SEL);
/* Register standard DMA controllers */
s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);

290
arch/arm/mach-s3c64xx/gpiolib.c
View File

@ -1,290 +0,0 @@
/* arch/arm/plat-s3c64xx/gpiolib.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX - GPIOlib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <mach/map.h>
#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
#include <mach/regs-gpio.h>
/* GPIO bank summary:
*
* Bank GPIOs Style SlpCon ExtInt Group
* A 8 4Bit Yes 1
* B 7 4Bit Yes 1
* C 8 4Bit Yes 2
* D 5 4Bit Yes 3
* E 5 4Bit Yes None
* F 16 2Bit Yes 4 [1]
* G 7 4Bit Yes 5
* H 10 4Bit[2] Yes 6
* I 16 2Bit Yes None
* J 12 2Bit Yes None
* K 16 4Bit[2] No None
* L 15 4Bit[2] No None
* M 6 4Bit No IRQ_EINT
* N 16 2Bit No IRQ_EINT
* O 16 2Bit Yes 7
* P 15 2Bit Yes 8
* Q 9 2Bit Yes 9
*
* [1] BANKF pins 14,15 do not form part of the external interrupt sources
* [2] BANK has two control registers, GPxCON0 and GPxCON1
*/
static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.get_config = s3c_gpio_getcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
.cfg_eint = 7,
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.get_config = s3c_gpio_getcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
.cfg_eint = 3,
.get_config = s3c_gpio_getcfg_s3c64xx_4bit,
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
{
return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
}
static struct s3c_gpio_chip gpio_4bit[] = {
{
.base = S3C64XX_GPA_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPA(0),
.ngpio = S3C64XX_GPIO_A_NR,
.label = "GPA",
},
}, {
.base = S3C64XX_GPB_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPB(0),
.ngpio = S3C64XX_GPIO_B_NR,
.label = "GPB",
},
}, {
.base = S3C64XX_GPC_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPC(0),
.ngpio = S3C64XX_GPIO_C_NR,
.label = "GPC",
},
}, {
.base = S3C64XX_GPD_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPD(0),
.ngpio = S3C64XX_GPIO_D_NR,
.label = "GPD",
},
}, {
.base = S3C64XX_GPE_BASE,
.config = &gpio_4bit_cfg_noint,
.chip = {
.base = S3C64XX_GPE(0),
.ngpio = S3C64XX_GPIO_E_NR,
.label = "GPE",
},
}, {
.base = S3C64XX_GPG_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPG(0),
.ngpio = S3C64XX_GPIO_G_NR,
.label = "GPG",
},
}, {
.base = S3C64XX_GPM_BASE,
.config = &gpio_4bit_cfg_eint0011,
.chip = {
.base = S3C64XX_GPM(0),
.ngpio = S3C64XX_GPIO_M_NR,
.label = "GPM",
.to_irq = s3c64xx_gpio2int_gpm,
},
},
};
static int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
{
return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
}
static struct s3c_gpio_chip gpio_4bit2[] = {
{
.base = S3C64XX_GPH_BASE + 0x4,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPH(0),
.ngpio = S3C64XX_GPIO_H_NR,
.label = "GPH",
},
}, {
.base = S3C64XX_GPK_BASE + 0x4,
.config = &gpio_4bit_cfg_noint,
.chip = {
.base = S3C64XX_GPK(0),
.ngpio = S3C64XX_GPIO_K_NR,
.label = "GPK",
},
}, {
.base = S3C64XX_GPL_BASE + 0x4,
.config = &gpio_4bit_cfg_eint0011,
.chip = {
.base = S3C64XX_GPL(0),
.ngpio = S3C64XX_GPIO_L_NR,
.label = "GPL",
.to_irq = s3c64xx_gpio2int_gpl,
},
},
};
static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
.set_config = s3c_gpio_setcfg_s3c24xx,
.get_config = s3c_gpio_getcfg_s3c24xx,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
.cfg_eint = 2,
.set_config = s3c_gpio_setcfg_s3c24xx,
.get_config = s3c_gpio_getcfg_s3c24xx,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
.cfg_eint = 3,
.set_config = s3c_gpio_setcfg_s3c24xx,
.get_config = s3c_gpio_getcfg_s3c24xx,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_chip gpio_2bit[] = {
{
.base = S3C64XX_GPF_BASE,
.config = &gpio_2bit_cfg_eint11,
.chip = {
.base = S3C64XX_GPF(0),
.ngpio = S3C64XX_GPIO_F_NR,
.label = "GPF",
},
}, {
.base = S3C64XX_GPI_BASE,
.config = &gpio_2bit_cfg_noint,
.chip = {
.base = S3C64XX_GPI(0),
.ngpio = S3C64XX_GPIO_I_NR,
.label = "GPI",
},
}, {
.base = S3C64XX_GPJ_BASE,
.config = &gpio_2bit_cfg_noint,
.chip = {
.base = S3C64XX_GPJ(0),
.ngpio = S3C64XX_GPIO_J_NR,
.label = "GPJ",
},
}, {
.base = S3C64XX_GPN_BASE,
.irq_base = IRQ_EINT(0),
.config = &gpio_2bit_cfg_eint10,
.chip = {
.base = S3C64XX_GPN(0),
.ngpio = S3C64XX_GPIO_N_NR,
.label = "GPN",
.to_irq = samsung_gpiolib_to_irq,
},
}, {
.base = S3C64XX_GPO_BASE,
.config = &gpio_2bit_cfg_eint11,
.chip = {
.base = S3C64XX_GPO(0),
.ngpio = S3C64XX_GPIO_O_NR,
.label = "GPO",
},
}, {
.base = S3C64XX_GPP_BASE,
.config = &gpio_2bit_cfg_eint11,
.chip = {
.base = S3C64XX_GPP(0),
.ngpio = S3C64XX_GPIO_P_NR,
.label = "GPP",
},
}, {
.base = S3C64XX_GPQ_BASE,
.config = &gpio_2bit_cfg_eint11,
.chip = {
.base = S3C64XX_GPQ(0),
.ngpio = S3C64XX_GPIO_Q_NR,
.label = "GPQ",
},
},
};
static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
{
chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
}
static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
int nr_chips,
void (*fn)(struct s3c_gpio_chip *))
{
for (; nr_chips > 0; nr_chips--, chips++) {
if (fn)
(fn)(chips);
s3c_gpiolib_add(chips);
}
}
static __init int s3c64xx_gpiolib_init(void)
{
s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
samsung_gpiolib_add_4bit);
s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
samsung_gpiolib_add_4bit2);
s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
s3c64xx_gpiolib_add_2bit);
return 0;
}
core_initcall(s3c64xx_gpiolib_init);

7
arch/arm/mach-s3c64xx/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

23
arch/arm/mach-s3c64xx/include/mach/crag6410.h Normal file
View File

@ -0,0 +1,23 @@
/* Cragganmore 6410 shared definitions
*
* Copyright 2011 Wolfson Microelectronics plc
* Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef MACH_CRAG6410_H
#define MACH_CRAG6410_H
#include <linux/gpio.h>
#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START
#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64)
#define PCA935X_GPIO_BASE GPIO_BOARD_START
#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16)
#endif

45
arch/arm/mach-s3c64xx/include/mach/pll.h
View File

@ -1,45 +0,0 @@
/* arch/arm/plat-s3c64xx/include/plat/pll.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX PLL code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
#define S3C6400_PLL_MDIV_SHIFT (16)
#define S3C6400_PLL_PDIV_SHIFT (8)
#define S3C6400_PLL_SDIV_SHIFT (0)
#include <asm/div64.h>
#include <plat/pll6553x.h>
static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
u32 pllcon)
{
u32 mdiv, pdiv, sdiv;
u64 fvco = baseclk;
mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}
static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
{
return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0),
__raw_readl(S3C_EPLL_CON1));
}

2
arch/arm/mach-s3c64xx/include/mach/pm-core.h
View File

@ -104,7 +104,7 @@ static inline void s3c_pm_restored_gpios(void)
__raw_writel(0, S3C64XX_SLPEN);
}
static inline void s3c_pm_saved_gpios(void)
static inline void samsung_pm_saved_gpios(void)
{
/* turn on the sleep mode and keep it there, as it seems that during
* suspend the xCON registers get re-set and thus you can end up with

56
arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
View File

@ -1,56 +0,0 @@
/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64xx - pwm clock and timer support
*/
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @tcfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
}
/**
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
* @tcfg1: The tcfg1 setting, shifted down.
*
* Get the divisor value for the given tcfg1 setting. We assume the
* caller has already checked to see if this is not a TCLK source.
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << tcfg1;
}
/**
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
*
* Return true if we have a /1 in the tdiv setting.
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 1;
}
/**
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
* @div: The divisor to calculate the bit information for.
*
* Turn a divisor into the necessary bit field for TCFG1.
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div);
}
#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK

3
arch/arm/mach-s3c64xx/include/mach/regs-sys.h
View File

@ -21,8 +21,11 @@
#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
#define S3C64XX_SDMA_SEL S3C_SYSREG(0x110)
#define S3C64XX_OTHERS S3C_SYSREG(0x900)
#define S3C64XX_OTHERS_USBMASK (1 << 16)
#define S3C64XX_OTHERS_SYNCMUXSEL (1 << 6)
#endif /* _PLAT_REGS_SYS_H */

2
arch/arm/mach-s3c64xx/mach-anw6410.c
View File

@ -45,7 +45,7 @@
#include <plat/fb.h>
#include <plat/regs-fb-v4.h>
#include <mach/s3c6410.h>
#include <plat/s3c6410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>

182
arch/arm/mach-s3c64xx/mach-crag6410-module.c Normal file
View File

@ -0,0 +1,182 @@
/* Speyside modules for Cragganmore - board data probing
*
* Copyright 2011 Wolfson Microelectronics plc
* Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/mfd/wm831x/irq.h>
#include <linux/mfd/wm831x/gpio.h>
#include <sound/wm8996.h>
#include <sound/wm8962.h>
#include <sound/wm9081.h>
#include <mach/crag6410.h>
static struct wm8996_retune_mobile_config wm8996_retune[] = {
{
.name = "Sub LPF",
.rate = 48000,
.regs = {
0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
},
},
{
.name = "Sub HPF",
.rate = 48000,
.regs = {
0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
},
},
};
static struct wm8996_pdata wm8996_pdata __initdata = {
.ldo_ena = S3C64XX_GPN(7),
.gpio_base = CODEC_GPIO_BASE,
.micdet_def = 1,
.inl_mode = WM8996_DIFFERRENTIAL_1,
.inr_mode = WM8996_DIFFERRENTIAL_1,
.irq_flags = IRQF_TRIGGER_RISING,
.gpio_default = {
0x8001, /* GPIO1 == ADCLRCLK1 */
0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
0x0141, /* GPIO3 == HP_SEL */
0x0002, /* GPIO4 == IRQ */
0x020e, /* GPIO5 == CLKOUT */
},
.retune_mobile_cfgs = wm8996_retune,
.num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune),
};
static struct wm8962_pdata wm8962_pdata __initdata = {
.gpio_init = {
0,
WM8962_GPIO_FN_OPCLK,
WM8962_GPIO_FN_DMICCLK,
0,
0x8000 | WM8962_GPIO_FN_DMICDAT,
WM8962_GPIO_FN_IRQ, /* Open drain mode */
},
.irq_active_low = true,
};
static struct wm9081_pdata wm9081_pdata __initdata = {
.irq_high = false,
.irq_cmos = false,
};
static const struct i2c_board_info wm1254_devs[] = {
{ I2C_BOARD_INFO("wm8996", 0x1a),
.platform_data = &wm8996_pdata,
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
},
{ I2C_BOARD_INFO("wm9081", 0x6c),
.platform_data = &wm9081_pdata, },
};
static const struct i2c_board_info wm1255_devs[] = {
{ I2C_BOARD_INFO("wm5100", 0x1a),
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
},
{ I2C_BOARD_INFO("wm9081", 0x6c),
.platform_data = &wm9081_pdata, },
};
static const struct i2c_board_info wm1259_devs[] = {
{ I2C_BOARD_INFO("wm8962", 0x1a),
.platform_data = &wm8962_pdata,
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
},
};
static __devinitdata const struct {
u8 id;
const char *name;
const struct i2c_board_info *i2c_devs;
int num_i2c_devs;
} gf_mods[] = {
{ .id = 0x01, .name = "1250-EV1 Springbank" },
{ .id = 0x02, .name = "1251-EV1 Jura" },
{ .id = 0x03, .name = "1252-EV1 Glenlivet" },
{ .id = 0x11, .name = "6249-EV2 Glenfarclas", },
{ .id = 0x21, .name = "1275-EV1 Mortlach" },
{ .id = 0x25, .name = "1274-EV1 Glencadam" },
{ .id = 0x31, .name = "1253-EV1 Tomatin", },
{ .id = 0x39, .name = "1254-EV1 Dallas Dhu",
.i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) },
{ .id = 0x3a, .name = "1259-EV1 Tobermory",
.i2c_devs = wm1259_devs, .num_i2c_devs = ARRAY_SIZE(wm1259_devs) },
{ .id = 0x3b, .name = "1255-EV1 Kilchoman",
.i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) },
{ .id = 0x3c, .name = "1273-EV1 Longmorn" },
};
static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
const struct i2c_device_id *i2c_id)
{
int ret, i, j, id, rev;
ret = i2c_smbus_read_byte_data(i2c, 0);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read ID: %d\n", ret);
return ret;
}
id = (ret & 0xfe) >> 2;
rev = ret & 0x3;
for (i = 0; i < ARRAY_SIZE(gf_mods); i++)
if (id == gf_mods[i].id)
break;
if (i < ARRAY_SIZE(gf_mods)) {
dev_info(&i2c->dev, "%s revision %d\n",
gf_mods[i].name, rev + 1);
for (j = 0; j < gf_mods[i].num_i2c_devs; j++) {
if (!i2c_new_device(i2c->adapter,
&(gf_mods[i].i2c_devs[j])))
dev_err(&i2c->dev,
"Failed to register dev: %d\n", ret);
}
} else {
dev_warn(&i2c->dev, "Unknown module ID %d revision %d\n",
id, rev);
}
return 0;
}
static const struct i2c_device_id wlf_gf_module_id[] = {
{ "wlf-gf-module", 0 },
{ }
};
static struct i2c_driver wlf_gf_module_driver = {
.driver = {
.name = "wlf-gf-module",
.owner = THIS_MODULE,
},
.probe = wlf_gf_module_probe,
.id_table = wlf_gf_module_id,
};
static int __init wlf_gf_module_register(void)
{
return i2c_add_driver(&wlf_gf_module_driver);
}
module_init(wlf_gf_module_register);

108
arch/arm/mach-s3c64xx/mach-crag6410.c
View File

@ -43,13 +43,14 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/s3c6410.h>
#include <mach/regs-sys.h>
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>
#include <mach/crag6410.h>
#include <mach/regs-gpio-memport.h>
#include <plat/s3c6410.h>
#include <plat/regs-serial.h>
#include <plat/regs-fb-v4.h>
#include <plat/fb.h>
@ -65,17 +66,6 @@
#include <plat/iic.h>
#include <plat/pm.h>
#include <sound/wm8996.h>
#include <sound/wm8962.h>
#include <sound/wm9081.h>
#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START
#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64)
#define PCA935X_GPIO_BASE GPIO_BOARD_START
#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16)
/* serial port setup */
#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
@ -287,6 +277,11 @@ static struct platform_device speyside_device = {
.id = -1,
};
static struct platform_device lowland_device = {
.name = "lowland",
.id = -1,
};
static struct platform_device speyside_wm8962_device = {
.name = "speyside-wm8962",
.id = -1,
@ -295,6 +290,8 @@ static struct platform_device speyside_wm8962_device = {
static struct regulator_consumer_supply wallvdd_consumers[] = {
REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
REGULATOR_SUPPLY("SPKVDDL", "1-001a"),
REGULATOR_SUPPLY("SPKVDDR", "1-001a"),
};
static struct regulator_init_data wallvdd_data = {
@ -342,6 +339,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
&crag6410_backlight_device,
&speyside_device,
&speyside_wm8962_device,
&lowland_device,
&wallvdd_device,
};
@ -350,6 +348,12 @@ static struct pca953x_platform_data crag6410_pca_data = {
.irq_base = 0,
};
/* VDDARM is controlled by DVS1 connected to GPK(0) */
static struct wm831x_buckv_pdata vddarm_pdata = {
.dvs_control_src = 1,
.dvs_gpio = S3C64XX_GPK(0),
};
static struct regulator_consumer_supply vddarm_consumers[] __initdata = {
REGULATOR_SUPPLY("vddarm", NULL),
};
@ -365,6 +369,7 @@ static struct regulator_init_data vddarm __initdata = {
.num_consumer_supplies = ARRAY_SIZE(vddarm_consumers),
.consumer_supplies = vddarm_consumers,
.supply_regulator = "WALLVDD",
.driver_data = &vddarm_pdata,
};
static struct regulator_init_data vddint __initdata = {
@ -500,6 +505,8 @@ static struct wm831x_pdata crag_pmic_pdata __initdata = {
.backup = &banff_backup_pdata,
.gpio_defaults = {
/* GPIO5: DVS1_REQ - CMOS, DBVDD, active high */
[4] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA | 0x8,
/* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/
[10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6,
/* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/
@ -557,8 +564,12 @@ static struct regulator_init_data pvdd_1v2 __initdata = {
};
static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
REGULATOR_SUPPLY("LDOVDD", "1-001a"),
REGULATOR_SUPPLY("PLLVDD", "1-001a"),
REGULATOR_SUPPLY("DBVDD", "1-001a"),
REGULATOR_SUPPLY("DBVDD1", "1-001a"),
REGULATOR_SUPPLY("DBVDD2", "1-001a"),
REGULATOR_SUPPLY("DBVDD3", "1-001a"),
REGULATOR_SUPPLY("CPVDD", "1-001a"),
REGULATOR_SUPPLY("AVDD2", "1-001a"),
REGULATOR_SUPPLY("DCVDD", "1-001a"),
@ -611,81 +622,16 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
.disable_touch = true,
};
static struct wm8996_retune_mobile_config wm8996_retune[] = {
{
.name = "Sub LPF",
.rate = 48000,
.regs = {
0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
},
},
{
.name = "Sub HPF",
.rate = 48000,
.regs = {
0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
},
},
};
static struct wm8996_pdata wm8996_pdata __initdata = {
.ldo_ena = S3C64XX_GPN(7),
.gpio_base = CODEC_GPIO_BASE,
.micdet_def = 1,
.inl_mode = WM8996_DIFFERRENTIAL_1,
.inr_mode = WM8996_DIFFERRENTIAL_1,
.irq_flags = IRQF_TRIGGER_RISING,
.gpio_default = {
0x8001, /* GPIO1 == ADCLRCLK1 */
0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
0x0141, /* GPIO3 == HP_SEL */
0x0002, /* GPIO4 == IRQ */
0x020e, /* GPIO5 == CLKOUT */
},
.retune_mobile_cfgs = wm8996_retune,
.num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune),
};
static struct wm8962_pdata wm8962_pdata __initdata = {
.gpio_init = {
0,
WM8962_GPIO_FN_OPCLK,
WM8962_GPIO_FN_DMICCLK,
0,
0x8000 | WM8962_GPIO_FN_DMICDAT,
WM8962_GPIO_FN_IRQ, /* Open drain mode */
},
.irq_active_low = true,
};
static struct wm9081_pdata wm9081_pdata __initdata = {
.irq_high = false,
.irq_cmos = false,
};
static struct i2c_board_info i2c_devs1[] __initdata = {
{ I2C_BOARD_INFO("wm8311", 0x34),
.irq = S3C_EINT(0),
.platform_data = &glenfarclas_pmic_pdata },
{ I2C_BOARD_INFO("wlf-gf-module", 0x24) },
{ I2C_BOARD_INFO("wlf-gf-module", 0x25) },
{ I2C_BOARD_INFO("wlf-gf-module", 0x26) },
{ I2C_BOARD_INFO("wm1250-ev1", 0x27) },
{ I2C_BOARD_INFO("wm8996", 0x1a),
.platform_data = &wm8996_pdata,
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
},
{ I2C_BOARD_INFO("wm9081", 0x6c),
.platform_data = &wm9081_pdata, },
{ I2C_BOARD_INFO("wm8962", 0x1a),
.platform_data = &wm8962_pdata,
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
},
};
static void __init crag6410_map_io(void)

2
arch/arm/mach-s3c64xx/mach-hmt.c
View File

@ -37,7 +37,7 @@
#include <plat/fb.h>
#include <plat/nand.h>
#include <mach/s3c6410.h>
#include <plat/s3c6410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>

2
arch/arm/mach-s3c64xx/mach-mini6410.c
View File

@ -32,8 +32,8 @@
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>
#include <mach/regs-srom.h>
#include <mach/s3c6410.h>
#include <plat/s3c6410.h>
#include <plat/adc.h>
#include <plat/cpu.h>
#include <plat/devs.h>

2
arch/arm/mach-s3c64xx/mach-ncp.c
View File

@ -39,7 +39,7 @@
#include <plat/iic.h>
#include <plat/fb.h>
#include <mach/s3c6410.h>
#include <plat/s3c6410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>

2
arch/arm/mach-s3c64xx/mach-real6410.c
View File

@ -33,8 +33,8 @@
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>
#include <mach/regs-srom.h>
#include <mach/s3c6410.h>
#include <plat/s3c6410.h>
#include <plat/adc.h>
#include <plat/cpu.h>
#include <plat/devs.h>

2
arch/arm/mach-s3c64xx/mach-smartq5.c
View File

@ -22,8 +22,8 @@
#include <mach/map.h>
#include <mach/regs-gpio.h>
#include <mach/s3c6410.h>
#include <plat/s3c6410.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/fb.h>

2
arch/arm/mach-s3c64xx/mach-smartq7.c
View File

@ -22,8 +22,8 @@
#include <mach/map.h>
#include <mach/regs-gpio.h>
#include <mach/s3c6410.h>
#include <plat/s3c6410.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/fb.h>

2
arch/arm/mach-s3c64xx/mach-smdk6400.c
View File

@ -31,7 +31,7 @@
#include <plat/regs-serial.h>
#include <mach/s3c6400.h>
#include <plat/s3c6400.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>

2
arch/arm/mach-s3c64xx/mach-smdk6410.c
View File

@ -63,7 +63,7 @@
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
#include <mach/s3c6410.h>
#include <plat/s3c6410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>

4
arch/arm/mach-s3c64xx/pm.c
View File

@ -29,6 +29,7 @@
#include <mach/regs-clock.h>
#include <mach/regs-syscon-power.h>
#include <mach/regs-gpio-memport.h>
#include <mach/regs-modem.h>
#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
void s3c_pm_debug_smdkled(u32 set, u32 clear)
@ -85,6 +86,9 @@ static struct sleep_save misc_save[] = {
SAVE_ITEM(S3C64XX_MEM0CONSLP0),
SAVE_ITEM(S3C64XX_MEM0CONSLP1),
SAVE_ITEM(S3C64XX_MEM1CONSLP),
SAVE_ITEM(S3C64XX_SDMA_SEL),
SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
};
void s3c_pm_configure_extint(void)

2
arch/arm/mach-s3c64xx/s3c6400.c
View File

@ -38,7 +38,7 @@
#include <plat/sdhci.h>
#include <plat/iic-core.h>
#include <plat/onenand-core.h>
#include <mach/s3c6400.h>
#include <plat/s3c6400.h>
void __init s3c6400_map_io(void)
{

4
arch/arm/mach-s3c64xx/s3c6410.c
View File

@ -41,8 +41,8 @@
#include <plat/adc-core.h>
#include <plat/iic-core.h>
#include <plat/onenand-core.h>
#include <mach/s3c6400.h>
#include <mach/s3c6410.h>
#include <plat/s3c6400.h>
#include <plat/s3c6410.h>
void __init s3c6410_map_io(void)
{

48
arch/arm/mach-s3c64xx/setup-sdhci.c
View File

@ -12,17 +12,7 @@
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <plat/regs-sdhci.h>
#include <plat/sdhci.h>
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
@ -32,41 +22,3 @@ char *s3c64xx_hsmmc_clksrcs[4] = {
[2] = "mmc_bus",
/* [3] = "48m", - note not successfully used yet */
};
void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card)
{
u32 ctrl2, ctrl3;
ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
S3C_SDHCI_CTRL2_ENFBCLKRX |
S3C_SDHCI_CTRL2_DFCNT_NONE |
S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
if (ios->clock < 25 * 1000000)
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
S3C_SDHCI_CTRL3_FCSEL2 |
S3C_SDHCI_CTRL3_FCSEL1 |
S3C_SDHCI_CTRL3_FCSEL0);
else
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
pr_debug("%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
writel(ctrl2, r + S3C_SDHCI_CONTROL2);
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
}
void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card)
{
writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
s3c6400_setup_sdhci_cfg_card(dev, r, ios, card);
}

14
arch/arm/mach-s5p64x0/Kconfig
View File

@ -11,6 +11,8 @@ config CPU_S5P6440
bool
select SAMSUNG_DMADEV
select S5P_HRT
select S5P_SLEEP if PM
select SAMSUNG_WAKEMASK if PM
help
Enable S5P6440 CPU support
@ -18,9 +20,17 @@ config CPU_S5P6450
bool
select SAMSUNG_DMADEV
select S5P_HRT
select S5P_SLEEP if PM
select SAMSUNG_WAKEMASK if PM
help
Enable S5P6450 CPU support
config S5P64X0_SETUP_FB_24BPP
bool
help
Common setup code for S5P64X0 based boards with a LCD display
through RGB interface.
config S5P64X0_SETUP_I2C1
bool
help
@ -31,6 +41,7 @@ config S5P64X0_SETUP_I2C1
config MACH_SMDK6440
bool "SMDK6440"
select CPU_S5P6440
select S3C_DEV_FB
select S3C_DEV_I2C1
select S3C_DEV_RTC
select S3C_DEV_WDT
@ -39,6 +50,7 @@ config MACH_SMDK6440
select SAMSUNG_DEV_BACKLIGHT
select SAMSUNG_DEV_PWM
select SAMSUNG_DEV_TS
select S5P64X0_SETUP_FB_24BPP
select S5P64X0_SETUP_I2C1
help
Machine support for the Samsung SMDK6440
@ -46,6 +58,7 @@ config MACH_SMDK6440
config MACH_SMDK6450
bool "SMDK6450"
select CPU_S5P6450
select S3C_DEV_FB
select S3C_DEV_I2C1
select S3C_DEV_RTC
select S3C_DEV_WDT
@ -54,6 +67,7 @@ config MACH_SMDK6450
select SAMSUNG_DEV_BACKLIGHT
select SAMSUNG_DEV_PWM
select SAMSUNG_DEV_TS
select S5P64X0_SETUP_FB_24BPP
select S5P64X0_SETUP_I2C1
help
Machine support for the Samsung SMDK6450

4
arch/arm/mach-s5p64x0/Makefile
View File

@ -12,10 +12,11 @@ obj- :=
# Core support for S5P64X0 system
obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o
obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o
obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o
obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o
obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
obj-$(CONFIG_PM) += pm.o irq-pm.o
# machine support
@ -28,3 +29,4 @@ obj-y += dev-audio.o
obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o

1
arch/arm/mach-s5p64x0/clock-s5p6440.c
View File

@ -147,6 +147,7 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 8),
}, {
.name = "dma",
.devname = "dma-pl330",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 12),

1
arch/arm/mach-s5p64x0/clock-s5p6450.c
View File

@ -180,6 +180,7 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 3),
}, {
.name = "dma",
.devname = "dma-pl330",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 12),

3
arch/arm/mach-s5p64x0/cpu.c
View File

@ -39,6 +39,7 @@
#include <plat/s5p6440.h>
#include <plat/s5p6450.h>
#include <plat/adc-core.h>
#include <plat/fb-core.h>
/* Initial IO mappings */
@ -109,6 +110,7 @@ void __init s5p6440_map_io(void)
{
/* initialize any device information early */
s3c_adc_setname("s3c64xx-adc");
s3c_fb_setname("s5p64x0-fb");
iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
@ -119,6 +121,7 @@ void __init s5p6450_map_io(void)
{
/* initialize any device information early */
s3c_adc_setname("s3c64xx-adc");
s3c_fb_setname("s5p64x0-fb");
iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));

7
arch/arm/mach-s5p64x0/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

4
arch/arm/mach-s5p64x0/include/mach/irqs.h
View File

@ -87,6 +87,10 @@
#define IRQ_I2S0 IRQ_I2SV40
#define IRQ_LCD_FIFO IRQ_DISPCON0
#define IRQ_LCD_VSYNC IRQ_DISPCON1
#define IRQ_LCD_SYSTEM IRQ_DISPCON2
/* S5P6450 EINT feature will be added */
/*

4
arch/arm/mach-s5p64x0/include/mach/map.h
View File

@ -47,6 +47,8 @@
#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
#define S5P64X0_PA_FB 0xEE000000
#define S5P64X0_PA_I2S 0xF2000000
#define S5P6450_PA_I2S1 0xF2800000
#define S5P6450_PA_I2S2 0xF2900000
@ -64,6 +66,7 @@
#define S3C_PA_IIC1 S5P6440_PA_IIC1
#define S3C_PA_RTC S5P64X0_PA_RTC
#define S3C_PA_WDT S5P64X0_PA_WDT
#define S3C_PA_FB S5P64X0_PA_FB
#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
#define S5P_PA_SROMC S5P64X0_PA_SROMC
@ -85,5 +88,6 @@
#define S5P_PA_UART5 S5P6450_PA_UART(5)
#define S5P_SZ_UART SZ_256
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#endif /* __ASM_ARCH_MAP_H */

117
arch/arm/mach-s5p64x0/include/mach/pm-core.h Normal file
View File

@ -0,0 +1,117 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c
*
* Based on PM core support for S3C64XX by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <mach/regs-gpio.h>
static inline void s3c_pm_debug_init_uart(void)
{
u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK);
/*
* As a note, since the S5P64X0 UARTs generally have multiple
* clock sources, we simply enable PCLK at the moment and hope
* that the resume settings for the UART are suitable for the
* use with PCLK.
*/
tmp |= S5P64X0_CLK_GATE_PCLK_UART0;
tmp |= S5P64X0_CLK_GATE_PCLK_UART1;
tmp |= S5P64X0_CLK_GATE_PCLK_UART2;
tmp |= S5P64X0_CLK_GATE_PCLK_UART3;
__raw_writel(tmp, S5P64X0_CLK_GATE_PCLK);
udelay(10);
}
static inline void s3c_pm_arch_prepare_irqs(void)
{
/* VIC should have already been taken care of */
/* clear any pending EINT0 interrupts */
__raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND);
}
static inline void s3c_pm_arch_stop_clocks(void) { }
static inline void s3c_pm_arch_show_resume_irqs(void) { }
/*
* make these defines, we currently do not have any need to change
* the IRQ wake controls depending on the CPU we are running on
*/
#define s3c_irqwake_eintallow ((1 << 16) - 1)
#define s3c_irqwake_intallow (~0)
static inline void s3c_pm_arch_update_uart(void __iomem *regs,
struct pm_uart_save *save)
{
u32 ucon = __raw_readl(regs + S3C2410_UCON);
u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
u32 new_ucon;
u32 delta;
/*
* S5P64X0 UART blocks only support level interrupts, so ensure that
* when we restore unused UART blocks we force the level interrupt
* settings.
*/
save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
/*
* We have a constraint on changing the clock type of the UART
* between UCLKx and PCLK, so ensure that when we restore UCON
* that the CLK field is correctly modified if the bootloader
* has changed anything.
*/
if (ucon_clk != save_clk) {
new_ucon = save->ucon;
delta = ucon_clk ^ save_clk;
/*
* change from UCLKx => wrong PCLK,
* either UCLK can be tested for by a bit-test
* with UCLK0
*/
if (ucon_clk & S3C6400_UCON_UCLK0 &&
!(save_clk & S3C6400_UCON_UCLK0) &&
delta & S3C6400_UCON_PCLK2) {
new_ucon &= ~S3C6400_UCON_UCLK0;
} else if (delta == S3C6400_UCON_PCLK2) {
/*
* as a precaution, don't change from
* PCLK2 => PCLK or vice-versa
*/
new_ucon ^= S3C6400_UCON_PCLK2;
}
S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
ucon, new_ucon, save->ucon);
save->ucon = new_ucon;
}
}
static inline void s3c_pm_restored_gpios(void)
{
/* ensure sleep mode has been cleared from the system */
__raw_writel(0, S5P64X0_SLPEN);
}
static inline void samsung_pm_saved_gpios(void)
{
/*
* turn on the sleep mode and keep it there, as it seems that during
* suspend the xCON registers get re-set and thus you can end up with
* problems between going to sleep and resuming.
*/
__raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN);
}

68
arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
View File

@ -1,68 +0,0 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S5P64X0 - pwm clock and timer support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_PWMCLK_H
#define __ASM_ARCH_PWMCLK_H __FILE__
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @tcfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return 0;
}
/**
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
* @tcfg1: The tcfg1 setting, shifted down.
*
* Get the divisor value for the given tcfg1 setting. We assume the
* caller has already checked to see if this is not a TCLK source.
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << tcfg1;
}
/**
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
*
* Return true if we have a /1 in the tdiv setting.
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 1;
}
/**
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
* @div: The divisor to calculate the bit information for.
*
* Turn a divisor into the necessary bit field for TCFG1.
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div);
}
#define S3C_TCFG1_MUX_TCLK 0
#endif /* __ASM_ARCH_PWMCLK_H */

33
arch/arm/mach-s5p64x0/include/mach/regs-clock.h
View File

@ -41,17 +41,50 @@
#define S5P6450_DPLL_CON S5P_CLKREG(0x50)
#define S5P6450_DPLL_CON_K S5P_CLKREG(0x54)
#define S5P64X0_AHB_CON0 S5P_CLKREG(0x100)
#define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C)
#define S5P64X0_SYS_ID S5P_CLKREG(0x118)
#define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C)
#define S5P64X0_PWR_CFG S5P_CLKREG(0x804)
#define S5P64X0_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
#define S5P64X0_SLEEP_CFG S5P_CLKREG(0x818)
#define S5P64X0_PWR_STABLE S5P_CLKREG(0x828)
#define S5P64X0_OTHERS S5P_CLKREG(0x900)
#define S5P64X0_WAKEUP_STAT S5P_CLKREG(0x908)
#define S5P64X0_INFORM0 S5P_CLKREG(0xA00)
#define S5P64X0_CLKDIV0_HCLK_SHIFT (8)
#define S5P64X0_CLKDIV0_HCLK_MASK (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
/* HCLK GATE Registers */
#define S5P64X0_CLK_GATE_HCLK1_FIMGVG (1 << 2)
#define S5P64X0_CLK_GATE_SCLK1_FIMGVG (1 << 2)
/* PCLK GATE Registers */
#define S5P64X0_CLK_GATE_PCLK_UART3 (1 << 4)
#define S5P64X0_CLK_GATE_PCLK_UART2 (1 << 3)
#define S5P64X0_CLK_GATE_PCLK_UART1 (1 << 2)
#define S5P64X0_CLK_GATE_PCLK_UART0 (1 << 1)
#define S5P64X0_PWR_CFG_MMC1_DISABLE (1 << 15)
#define S5P64X0_PWR_CFG_MMC0_DISABLE (1 << 14)
#define S5P64X0_PWR_CFG_RTC_TICK_DISABLE (1 << 11)
#define S5P64X0_PWR_CFG_RTC_ALRM_DISABLE (1 << 10)
#define S5P64X0_PWR_CFG_WFI_MASK (3 << 5)
#define S5P64X0_PWR_CFG_WFI_SLEEP (3 << 5)
#define S5P64X0_SLEEP_CFG_OSC_EN (1 << 0)
#define S5P64X0_PWR_STABLE_PWR_CNT_VAL4 (4 << 0)
#define S5P6450_OTHERS_DISABLE_INT (1 << 31)
#define S5P64X0_OTHERS_RET_UART (1 << 26)
#define S5P64X0_OTHERS_RET_MMC1 (1 << 25)
#define S5P64X0_OTHERS_RET_MMC0 (1 << 24)
#define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16)
/* Compatibility defines */

21
arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
View File

@ -34,14 +34,35 @@
#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
#define S5P64X0_SPCON0 (S5P_VA_GPIO + 0x1A0)
#define S5P64X0_SPCON0_LCD_SEL_MASK (0x3 << 0)
#define S5P64X0_SPCON0_LCD_SEL_RGB (0x1 << 0)
#define S5P64X0_SPCON1 (S5P_VA_GPIO + 0x2B0)
#define S5P64X0_MEM0CONSLP0 (S5P_VA_GPIO + 0x1C0)
#define S5P64X0_MEM0CONSLP1 (S5P_VA_GPIO + 0x1C4)
#define S5P64X0_MEM0DRVCON (S5P_VA_GPIO + 0x1D0)
#define S5P64X0_MEM1DRVCON (S5P_VA_GPIO + 0x1D4)
#define S5P64X0_EINT12CON (S5P_VA_GPIO + 0x200)
#define S5P64X0_EINT12FLTCON (S5P_VA_GPIO + 0x220)
#define S5P64X0_EINT12MASK (S5P_VA_GPIO + 0x240)
/* External interrupt control registers for group0 */
#define EINT0CON0_OFFSET (0x900)
#define EINT0FLTCON0_OFFSET (0x910)
#define EINT0FLTCON1_OFFSET (0x914)
#define EINT0MASK_OFFSET (0x920)
#define EINT0PEND_OFFSET (0x924)
#define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET)
#define S5P64X0_EINT0FLTCON0 (S5P_VA_GPIO + EINT0FLTCON0_OFFSET)
#define S5P64X0_EINT0FLTCON1 (S5P_VA_GPIO + EINT0FLTCON1_OFFSET)
#define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET)
#define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET)
#define S5P64X0_SLPEN (S5P_VA_GPIO + 0x930)
#define S5P64X0_SLPEN_USE_xSLP (1 << 0)
#endif /* __ASM_ARCH_REGS_GPIO_H */

2
arch/arm/mach-s5p64x0/irq-eint.c
View File

@ -20,6 +20,7 @@
#include <plat/cpu.h>
#include <plat/regs-irqtype.h>
#include <plat/gpio-cfg.h>
#include <plat/pm.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
@ -134,6 +135,7 @@ static int s5p64x0_alloc_gc(void)
ct->chip.irq_mask = irq_gc_mask_set_bit;
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
ct->chip.irq_set_wake = s3c_irqext_wake;
ct->regs.ack = EINT0PEND_OFFSET;
ct->regs.mask = EINT0MASK_OFFSET;
irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,

92
arch/arm/mach-s5p64x0/irq-pm.c Normal file
View File

@ -0,0 +1,92 @@
/* linux/arch/arm/mach-s5p64x0/irq-pm.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - Interrupt handling Power Management
*
* Based on arch/arm/mach-s3c64xx/irq-pm.c by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/syscore_ops.h>
#include <linux/serial_core.h>
#include <linux/io.h>
#include <plat/regs-serial.h>
#include <plat/pm.h>
#include <mach/regs-gpio.h>
static struct sleep_save irq_save[] = {
SAVE_ITEM(S5P64X0_EINT0CON0),
SAVE_ITEM(S5P64X0_EINT0FLTCON0),
SAVE_ITEM(S5P64X0_EINT0FLTCON1),
SAVE_ITEM(S5P64X0_EINT0MASK),
};
static struct irq_grp_save {
u32 con;
u32 fltcon;
u32 mask;
} eint_grp_save[4];
static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
static int s5p64x0_irq_pm_suspend(void)
{
struct irq_grp_save *grp = eint_grp_save;
int i;
S3C_PMDBG("%s: suspending IRQs\n", __func__);
s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4));
grp->mask = __raw_readl(S5P64X0_EINT12MASK + (i * 4));
grp->fltcon = __raw_readl(S5P64X0_EINT12FLTCON + (i * 4));
}
return 0;
}
static void s5p64x0_irq_pm_resume(void)
{
struct irq_grp_save *grp = eint_grp_save;
int i;
S3C_PMDBG("%s: resuming IRQs\n", __func__);
s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
__raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
__raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4));
__raw_writel(grp->mask, S5P64X0_EINT12MASK + (i * 4));
__raw_writel(grp->fltcon, S5P64X0_EINT12FLTCON + (i * 4));
}
S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
}
static struct syscore_ops s5p64x0_irq_syscore_ops = {
.suspend = s5p64x0_irq_pm_suspend,
.resume = s5p64x0_irq_pm_resume,
};
static int __init s5p64x0_syscore_init(void)
{
register_syscore_ops(&s5p64x0_irq_syscore_ops);
return 0;
}
core_initcall(s5p64x0_syscore_init);

74
arch/arm/mach-s5p64x0/mach-smdk6440.c
View File

@ -23,6 +23,9 @@
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/pwm_backlight.h>
#include <linux/fb.h>
#include <video/platform_lcd.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -47,6 +50,8 @@
#include <plat/ts.h>
#include <plat/s5p-time.h>
#include <plat/backlight.h>
#include <plat/fb.h>
#include <plat/regs-fb.h>
#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
@ -92,6 +97,59 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
},
};
/* Frame Buffer */
static struct s3c_fb_pd_win smdk6440_fb_win0 = {
.win_mode = {
.left_margin = 8,
.right_margin = 13,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.max_bpp = 32,
.default_bpp = 24,
};
static struct s3c_fb_platdata smdk6440_lcd_pdata __initdata = {
.win[0] = &smdk6440_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
.setup_gpio = s5p64x0_fb_gpio_setup_24bpp,
};
/* LCD power controller */
static void smdk6440_lte480_reset_power(struct plat_lcd_data *pd,
unsigned int power)
{
int err;
if (power) {
err = gpio_request(S5P6440_GPN(5), "GPN");
if (err) {
printk(KERN_ERR "failed to request GPN for lcd reset\n");
return;
}
gpio_direction_output(S5P6440_GPN(5), 1);
gpio_set_value(S5P6440_GPN(5), 0);
gpio_set_value(S5P6440_GPN(5), 1);
gpio_free(S5P6440_GPN(5));
}
}
static struct plat_lcd_data smdk6440_lcd_power_data = {
.set_power = smdk6440_lte480_reset_power,
};
static struct platform_device smdk6440_lcd_lte480wv = {
.name = "platform-lcd",
.dev.parent = &s3c_device_fb.dev,
.dev.platform_data = &smdk6440_lcd_power_data,
};
static struct platform_device *smdk6440_devices[] __initdata = {
&s3c_device_adc,
&s3c_device_rtc,
@ -101,6 +159,8 @@ static struct platform_device *smdk6440_devices[] __initdata = {
&s3c_device_wdt,
&samsung_asoc_dma,
&s5p6440_device_iis,
&s3c_device_fb,
&smdk6440_lcd_lte480wv,
};
static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
@ -147,6 +207,17 @@ static void __init smdk6440_map_io(void)
s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
}
static void s5p6440_set_lcd_interface(void)
{
unsigned int cfg;
/* select TFT LCD type (RGB I/F) */
cfg = __raw_readl(S5P64X0_SPCON0);
cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK;
cfg |= S5P64X0_SPCON0_LCD_SEL_RGB;
__raw_writel(cfg, S5P64X0_SPCON0);
}
static void __init smdk6440_machine_init(void)
{
s3c24xx_ts_set_platdata(NULL);
@ -160,6 +231,9 @@ static void __init smdk6440_machine_init(void)
samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data);
s5p6440_set_lcd_interface();
s3c_fb_set_platdata(&smdk6440_lcd_pdata);
platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
}

75
arch/arm/mach-s5p64x0/mach-smdk6450.c
View File

@ -23,6 +23,9 @@
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/pwm_backlight.h>
#include <linux/fb.h>
#include <video/platform_lcd.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -47,6 +50,8 @@
#include <plat/ts.h>
#include <plat/s5p-time.h>
#include <plat/backlight.h>
#include <plat/fb.h>
#include <plat/regs-fb.h>
#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
@ -110,6 +115,59 @@ static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
#endif
};
/* Frame Buffer */
static struct s3c_fb_pd_win smdk6450_fb_win0 = {
.win_mode = {
.left_margin = 8,
.right_margin = 13,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.max_bpp = 32,
.default_bpp = 24,
};
static struct s3c_fb_platdata smdk6450_lcd_pdata __initdata = {
.win[0] = &smdk6450_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
.setup_gpio = s5p64x0_fb_gpio_setup_24bpp,
};
/* LCD power controller */
static void smdk6450_lte480_reset_power(struct plat_lcd_data *pd,
unsigned int power)
{
int err;
if (power) {
err = gpio_request(S5P6450_GPN(5), "GPN");
if (err) {
printk(KERN_ERR "failed to request GPN for lcd reset\n");
return;
}
gpio_direction_output(S5P6450_GPN(5), 1);
gpio_set_value(S5P6450_GPN(5), 0);
gpio_set_value(S5P6450_GPN(5), 1);
gpio_free(S5P6450_GPN(5));
}
}
static struct plat_lcd_data smdk6450_lcd_power_data = {
.set_power = smdk6450_lte480_reset_power,
};
static struct platform_device smdk6450_lcd_lte480wv = {
.name = "platform-lcd",
.dev.parent = &s3c_device_fb.dev,
.dev.platform_data = &smdk6450_lcd_power_data,
};
static struct platform_device *smdk6450_devices[] __initdata = {
&s3c_device_adc,
&s3c_device_rtc,
@ -119,6 +177,9 @@ static struct platform_device *smdk6450_devices[] __initdata = {
&s3c_device_wdt,
&samsung_asoc_dma,
&s5p6450_device_iis0,
&s3c_device_fb,
&smdk6450_lcd_lte480wv,
/* s5p6450_device_spi0 will be added */
};
@ -166,6 +227,17 @@ static void __init smdk6450_map_io(void)
s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
}
static void s5p6450_set_lcd_interface(void)
{
unsigned int cfg;
/* select TFT LCD type (RGB I/F) */
cfg = __raw_readl(S5P64X0_SPCON0);
cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK;
cfg |= S5P64X0_SPCON0_LCD_SEL_RGB;
__raw_writel(cfg, S5P64X0_SPCON0);
}
static void __init smdk6450_machine_init(void)
{
s3c24xx_ts_set_platdata(NULL);
@ -179,6 +251,9 @@ static void __init smdk6450_machine_init(void)
samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data);
s5p6450_set_lcd_interface();
s3c_fb_set_platdata(&smdk6450_lcd_pdata);
platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
}

204
arch/arm/mach-s5p64x0/pm.c Normal file
View File

@ -0,0 +1,204 @@
/* linux/arch/arm/mach-s5p64x0/pm.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 Power Management Support
*
* Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/suspend.h>
#include <linux/syscore_ops.h>
#include <linux/io.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/regs-timer.h>
#include <plat/wakeup-mask.h>
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
static struct sleep_save s5p64x0_core_save[] = {
SAVE_ITEM(S5P64X0_APLL_CON),
SAVE_ITEM(S5P64X0_MPLL_CON),
SAVE_ITEM(S5P64X0_EPLL_CON),
SAVE_ITEM(S5P64X0_EPLL_CON_K),
SAVE_ITEM(S5P64X0_CLK_SRC0),
SAVE_ITEM(S5P64X0_CLK_SRC1),
SAVE_ITEM(S5P64X0_CLK_DIV0),
SAVE_ITEM(S5P64X0_CLK_DIV1),
SAVE_ITEM(S5P64X0_CLK_DIV2),
SAVE_ITEM(S5P64X0_CLK_DIV3),
SAVE_ITEM(S5P64X0_CLK_GATE_MEM0),
SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1),
SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1),
};
static struct sleep_save s5p64x0_misc_save[] = {
SAVE_ITEM(S5P64X0_AHB_CON0),
SAVE_ITEM(S5P64X0_SPCON0),
SAVE_ITEM(S5P64X0_SPCON1),
SAVE_ITEM(S5P64X0_MEM0CONSLP0),
SAVE_ITEM(S5P64X0_MEM0CONSLP1),
SAVE_ITEM(S5P64X0_MEM0DRVCON),
SAVE_ITEM(S5P64X0_MEM1DRVCON),
SAVE_ITEM(S3C64XX_TINT_CSTAT),
};
/* DPLL is present only in S5P6450 */
static struct sleep_save s5p6450_core_save[] = {
SAVE_ITEM(S5P6450_DPLL_CON),
SAVE_ITEM(S5P6450_DPLL_CON_K),
};
void s3c_pm_configure_extint(void)
{
__raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK);
}
void s3c_pm_restore_core(void)
{
__raw_writel(0, S5P64X0_EINT_WAKEUP_MASK);
s3c_pm_do_restore_core(s5p64x0_core_save,
ARRAY_SIZE(s5p64x0_core_save));
if (soc_is_s5p6450())
s3c_pm_do_restore_core(s5p6450_core_save,
ARRAY_SIZE(s5p6450_core_save));
s3c_pm_do_restore(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
}
void s3c_pm_save_core(void)
{
s3c_pm_do_save(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
if (soc_is_s5p6450())
s3c_pm_do_save(s5p6450_core_save,
ARRAY_SIZE(s5p6450_core_save));
s3c_pm_do_save(s5p64x0_core_save, ARRAY_SIZE(s5p64x0_core_save));
}
static int s5p64x0_cpu_suspend(unsigned long arg)
{
unsigned long tmp = 0;
/*
* Issue the standby signal into the pm unit. Note, we
* issue a write-buffer drain just in case.
*/
asm("b 1f\n\t"
".align 5\n\t"
"1:\n\t"
"mcr p15, 0, %0, c7, c10, 5\n\t"
"mcr p15, 0, %0, c7, c10, 4\n\t"
"mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
/* we should never get past here */
panic("sleep resumed to originator?");
}
/* mapping of interrupts to parts of the wakeup mask */
static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = {
{ .irq = IRQ_RTC_ALARM, .bit = S5P64X0_PWR_CFG_RTC_ALRM_DISABLE, },
{ .irq = IRQ_RTC_TIC, .bit = S5P64X0_PWR_CFG_RTC_TICK_DISABLE, },
{ .irq = IRQ_HSMMC0, .bit = S5P64X0_PWR_CFG_MMC0_DISABLE, },
{ .irq = IRQ_HSMMC1, .bit = S5P64X0_PWR_CFG_MMC1_DISABLE, },
};
static void s5p64x0_pm_prepare(void)
{
u32 tmp;
samsung_sync_wakemask(S5P64X0_PWR_CFG,
s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs));
/* store the resume address in INFORM0 register */
__raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0);
/* setup clock gating for FIMGVG block */
__raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \
(S5P64X0_CLK_GATE_HCLK1_FIMGVG)), S5P64X0_CLK_GATE_HCLK1);
__raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \
(S5P64X0_CLK_GATE_SCLK1_FIMGVG)), S5P64X0_CLK_GATE_SCLK1);
/* Configure the stabilization counter with wait time required */
__raw_writel(S5P64X0_PWR_STABLE_PWR_CNT_VAL4, S5P64X0_PWR_STABLE);
/* set WFI to SLEEP mode configuration */
tmp = __raw_readl(S5P64X0_SLEEP_CFG);
tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN);
__raw_writel(tmp, S5P64X0_SLEEP_CFG);
tmp = __raw_readl(S5P64X0_PWR_CFG);
tmp &= ~(S5P64X0_PWR_CFG_WFI_MASK);
tmp |= S5P64X0_PWR_CFG_WFI_SLEEP;
__raw_writel(tmp, S5P64X0_PWR_CFG);
/*
* set OTHERS register to disable interrupt before going to
* sleep. This bit is present only in S5P6450, it is reserved
* in S5P6440.
*/
if (soc_is_s5p6450()) {
tmp = __raw_readl(S5P64X0_OTHERS);
tmp |= S5P6450_OTHERS_DISABLE_INT;
__raw_writel(tmp, S5P64X0_OTHERS);
}
/* ensure previous wakeup state is cleared before sleeping */
__raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT), S5P64X0_WAKEUP_STAT);
}
static int s5p64x0_pm_add(struct sys_device *sysdev)
{
pm_cpu_prep = s5p64x0_pm_prepare;
pm_cpu_sleep = s5p64x0_cpu_suspend;
pm_uart_udivslot = 1;
return 0;
}
static struct sysdev_driver s5p64x0_pm_driver = {
.add = s5p64x0_pm_add,
};
static __init int s5p64x0_pm_drvinit(void)
{
s3c_pm_init();
return sysdev_driver_register(&s5p64x0_sysclass, &s5p64x0_pm_driver);
}
arch_initcall(s5p64x0_pm_drvinit);
static void s5p64x0_pm_resume(void)
{
u32 tmp;
tmp = __raw_readl(S5P64X0_OTHERS);
tmp |= (S5P64X0_OTHERS_RET_MMC0 | S5P64X0_OTHERS_RET_MMC1 | \
S5P64X0_OTHERS_RET_UART);
__raw_writel(tmp , S5P64X0_OTHERS);
}
static struct syscore_ops s5p64x0_pm_syscore_ops = {
.resume = s5p64x0_pm_resume,
};
static __init int s5p64x0_pm_syscore_init(void)
{
register_syscore_ops(&s5p64x0_pm_syscore_ops);
return 0;
}
arch_initcall(s5p64x0_pm_syscore_init);

29
arch/arm/mach-s5p64x0/setup-fb-24bpp.c Normal file
View File

@ -0,0 +1,29 @@
/* linux/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Base S5P64X0 GPIO setup information for LCD framebuffer
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/fb.h>
#include <linux/gpio.h>
#include <plat/cpu.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
void s5p64x0_fb_gpio_setup_24bpp(void)
{
if (soc_is_s5p6440()) {
s3c_gpio_cfgrange_nopull(S5P6440_GPI(0), 16, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(S5P6440_GPJ(0), 12, S3C_GPIO_SFN(2));
} else if (soc_is_s5p6450()) {
s3c_gpio_cfgrange_nopull(S5P6450_GPI(0), 16, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(S5P6450_GPJ(0), 12, S3C_GPIO_SFN(2));
}
}

4
arch/arm/mach-s5pc100/clock.c
View File

@ -460,13 +460,13 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 2),
}, {
.name = "dma",
.devname = "s3c-pl330.1",
.devname = "dma-pl330.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "dma",
.devname = "s3c-pl330.0",
.devname = "dma-pl330.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 0),

1
arch/arm/mach-s5pc100/dma.c
View File

@ -260,6 +260,7 @@ struct amba_device s5pc100_device_pdma1 = {
static int __init s5pc100_dma_init(void)
{
amba_device_register(&s5pc100_device_pdma0, &iomem_resource);
amba_device_register(&s5pc100_device_pdma1, &iomem_resource);
return 0;
}

7
arch/arm/mach-s5pc100/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

56
arch/arm/mach-s5pc100/include/mach/pwm-clock.h
View File

@ -1,56 +0,0 @@
/* linux/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC100 - pwm clock and timer support
*
* Based on mach-s3c6400/include/mach/pwm-clock.h
*/
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @tcfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
}
/**
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
* @tcfg1: The tcfg1 setting, shifted down.
*
* Get the divisor value for the given tcfg1 setting. We assume the
* caller has already checked to see if this is not a TCLK source.
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << tcfg1;
}
/**
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
*
* Return true if we have a /1 in the tdiv setting.
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 1;
}
/**
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
* @div: The divisor to calculate the bit information for.
*
* Turn a divisor into the necessary bit field for TCFG1.
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div);
}
#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK

42
arch/arm/mach-s5pc100/setup-sdhci.c
View File

@ -11,17 +11,7 @@
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <plat/regs-sdhci.h>
#include <plat/sdhci.h>
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
@ -31,35 +21,3 @@ char *s5pc100_hsmmc_clksrcs[4] = {
[2] = "sclk_mmc", /* mmc_bus */
/* [3] = "48m", - note not successfully used yet */
};
void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card)
{
u32 ctrl2, ctrl3;
/* don't need to alter anything according to card-type */
writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
S3C_SDHCI_CTRL2_ENFBCLKRX |
S3C_SDHCI_CTRL2_DFCNT_NONE |
S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
if (ios->clock < 25 * 1000000)
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
S3C_SDHCI_CTRL3_FCSEL2 |
S3C_SDHCI_CTRL3_FCSEL1 |
S3C_SDHCI_CTRL3_FCSEL0);
else
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
writel(ctrl2, r + S3C_SDHCI_CONTROL2);
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
}

4
arch/arm/mach-s5pv210/Kconfig
View File

@ -14,6 +14,8 @@ config CPU_S5PV210
select SAMSUNG_DMADEV
select S5P_EXT_INT
select S5P_HRT
select S5P_PM if PM
select S5P_SLEEP if PM
help
Enable S5PV210 CPU support
@ -93,11 +95,13 @@ config MACH_GONI
select S3C_DEV_USB_HSOTG
select S5P_DEV_ONENAND
select SAMSUNG_DEV_KEYPAD
select S5P_DEV_TV
select S5PV210_SETUP_FB_24BPP
select S5PV210_SETUP_I2C1
select S5PV210_SETUP_I2C2
select S5PV210_SETUP_KEYPAD
select S5PV210_SETUP_SDHCI
select S5PV210_SETUP_FIMC
help
Machine support for Samsung GONI board
S5PC110(MCP) is one of package option of S5PV210

2
arch/arm/mach-s5pv210/Makefile
View File

@ -14,7 +14,7 @@ obj- :=
obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o
obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_PM) += pm.o
# machine support

141
arch/arm/mach-s5pv210/clock.c
View File

@ -174,6 +174,16 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
}
static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
}
static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
}
static struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
.rate = 27000000,
@ -295,13 +305,13 @@ static struct clk_ops clk_fout_apll_ops = {
static struct clk init_clocks_off[] = {
{
.name = "dma",
.devname = "s3c-pl330.0",
.devname = "dma-pl330.0",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "dma",
.devname = "s3c-pl330.1",
.devname = "dma-pl330.1",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 4),
@ -334,6 +344,40 @@ static struct clk init_clocks_off[] = {
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "dac",
.devname = "s5p-sdo",
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "mixer",
.devname = "s5p-mixer",
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "vp",
.devname = "s5p-mixer",
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "hdmi",
.devname = "s5pv210-hdmi",
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "hdmiphy",
.devname = "s5pv210-hdmi",
.enable = exynos4_clk_hdmiphy_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "dacphy",
.devname = "s5p-sdo",
.enable = exynos4_clk_dac_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "otg",
.parent = &clk_hclk_psys.clk,
@ -411,6 +455,12 @@ static struct clk init_clocks_off[] = {
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<9),
}, {
.name = "i2c",
.devname = "s3c2440-hdmiphy-i2c",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "spi",
.devname = "s3c64xx-spi.0",
@ -599,6 +649,23 @@ static struct clksrc_sources clkset_sclk_mixer = {
.nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
};
static struct clksrc_clk clk_sclk_mixer = {
.clk = {
.name = "sclk_mixer",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 1),
},
.sources = &clkset_sclk_mixer,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
};
static struct clksrc_clk *sclk_tv[] = {
&clk_sclk_dac,
&clk_sclk_pixel,
&clk_sclk_hdmi,
&clk_sclk_mixer,
};
static struct clk *clkset_sclk_audio0_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = &clk_pcmcdclk0,
@ -780,14 +847,6 @@ static struct clksrc_clk clksrcs[] = {
.sources = &clkset_uart,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
}, {
.clk = {
.name = "sclk_mixer",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 1),
},
.sources = &clkset_sclk_mixer,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
}, {
.clk = {
.name = "sclk_fimc",
@ -978,9 +1037,6 @@ static struct clksrc_clk *sysclks[] = {
&clk_pclk_psys,
&clk_vpllsrc,
&clk_sclk_vpll,
&clk_sclk_dac,
&clk_sclk_pixel,
&clk_sclk_hdmi,
&clk_mout_dmc0,
&clk_sclk_dmc0,
&clk_sclk_audio0,
@ -1065,6 +1121,61 @@ static struct clk_ops s5pv210_epll_ops = {
.get_rate = s5p_epll_get_rate,
};
static u32 vpll_div[][5] = {
{ 54000000, 3, 53, 3, 0 },
{ 108000000, 3, 53, 2, 0 },
};
static unsigned long s5pv210_vpll_get_rate(struct clk *clk)
{
return clk->rate;
}
static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate)
{
unsigned int vpll_con;
unsigned int i;
/* Return if nothing changed */
if (clk->rate == rate)
return 0;
vpll_con = __raw_readl(S5P_VPLL_CON);
vpll_con &= ~(0x1 << 27 | \
PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT | \
PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT | \
PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT);
for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
if (vpll_div[i][0] == rate) {
vpll_con |= vpll_div[i][1] << PLL90XX_PDIV_SHIFT;
vpll_con |= vpll_div[i][2] << PLL90XX_MDIV_SHIFT;
vpll_con |= vpll_div[i][3] << PLL90XX_SDIV_SHIFT;
vpll_con |= vpll_div[i][4] << 27;
break;
}
}
if (i == ARRAY_SIZE(vpll_div)) {
printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
__func__);
return -EINVAL;
}
__raw_writel(vpll_con, S5P_VPLL_CON);
/* Wait for VPLL lock */
while (!(__raw_readl(S5P_VPLL_CON) & (1 << PLL90XX_LOCKED_SHIFT)))
continue;
clk->rate = rate;
return 0;
}
static struct clk_ops s5pv210_vpll_ops = {
.get_rate = s5pv210_vpll_get_rate,
.set_rate = s5pv210_vpll_set_rate,
};
void __init_or_cpufreq s5pv210_setup_clocks(void)
{
struct clk *xtal_clk;
@ -1113,6 +1224,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
clk_fout_apll.ops = &clk_fout_apll_ops;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_vpll.ops = &s5pv210_vpll_ops;
clk_fout_vpll.rate = vpll;
printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
@ -1158,6 +1270,9 @@ void __init s5pv210_register_clocks(void)
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
s3c_register_clksrc(sclk_tv[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));

4
arch/arm/mach-s5pv210/cpu.c
View File

@ -42,6 +42,7 @@
#include <plat/keypad-core.h>
#include <plat/sdhci.h>
#include <plat/reset.h>
#include <plat/tv-core.h>
/* Initial IO mappings */
@ -145,6 +146,9 @@ void __init s5pv210_map_io(void)
/* Use s5pv210-keypad instead of samsung-keypad */
samsung_keypad_setname("s5pv210-keypad");
/* setup TV devices */
s5p_hdmi_setname("s5pv210-hdmi");
}
void __init s5pv210_init_clocks(int xtal)

1
arch/arm/mach-s5pv210/dma.c
View File

@ -254,6 +254,7 @@ struct amba_device s5pv210_device_pdma1 = {
static int __init s5pv210_dma_init(void)
{
amba_device_register(&s5pv210_device_pdma0, &iomem_resource);
amba_device_register(&s5pv210_device_pdma1, &iomem_resource);
return 0;
}

7
arch/arm/mach-s5pv210/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

4
arch/arm/mach-s5pv210/include/mach/irqs.h
View File

@ -56,7 +56,7 @@
#define IRQ_SPI2 S5P_IRQ_VIC1(17)
#define IRQ_IRDA S5P_IRQ_VIC1(18)
#define IRQ_IIC2 S5P_IRQ_VIC1(19)
#define IRQ_IIC3 S5P_IRQ_VIC1(20)
#define IRQ_IIC_HDMIPHY S5P_IRQ_VIC1(20)
#define IRQ_HSIRX S5P_IRQ_VIC1(21)
#define IRQ_HSITX S5P_IRQ_VIC1(22)
#define IRQ_UHOST S5P_IRQ_VIC1(23)
@ -86,7 +86,7 @@
#define IRQ_HDMI S5P_IRQ_VIC2(12)
#define IRQ_IIC1 S5P_IRQ_VIC2(13)
#define IRQ_MFC S5P_IRQ_VIC2(14)
#define IRQ_TVENC S5P_IRQ_VIC2(15)
#define IRQ_SDO S5P_IRQ_VIC2(15)
#define IRQ_I2S0 S5P_IRQ_VIC2(16)
#define IRQ_I2S1 S5P_IRQ_VIC2(17)
#define IRQ_I2S2 S5P_IRQ_VIC2(18)

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