drm/amd/display: Update efficiency bandwidth for dcn351
Fix 4k240 underflow on dcn351 Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -234,6 +234,7 @@ void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, s
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out->round_trip_ping_latency_dcfclk_cycles = 106;
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out->smn_latency_us = 2;
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out->dispclk_dppclk_vco_speed_mhz = 3600;
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out->pct_ideal_dram_bw_after_urgent_pixel_only = 65.0;
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break;
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}
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