net: dsa: rzn1-a5psw: add vlan support
Add support for vlan operation (add, del, filtering) on the RZN1 driver. The a5psw switch supports up to 32 VLAN IDs with filtering, tagged/untagged VLANs and PVID for each ports. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Clément Léger
David S. Miller
parent
0d37f83983
commit
7b3f77c428
@ -639,6 +639,146 @@ out_unlock:
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return ret;
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}
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static int a5psw_port_vlan_filtering(struct dsa_switch *ds, int port,
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bool vlan_filtering,
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struct netlink_ext_ack *extack)
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{
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u32 mask = BIT(port + A5PSW_VLAN_VERI_SHIFT) |
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BIT(port + A5PSW_VLAN_DISC_SHIFT);
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u32 val = vlan_filtering ? mask : 0;
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struct a5psw *a5psw = ds->priv;
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/* Disable/enable vlan tagging */
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a5psw_reg_rmw(a5psw, A5PSW_VLAN_IN_MODE_ENA, BIT(port),
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vlan_filtering ? BIT(port) : 0);
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/* Disable/enable vlan input filtering */
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a5psw_reg_rmw(a5psw, A5PSW_VLAN_VERIFY, mask, val);
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return 0;
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}
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static int a5psw_find_vlan_entry(struct a5psw *a5psw, u16 vid)
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{
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u32 vlan_res;
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int i;
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/* Find vlan for this port */
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for (i = 0; i < A5PSW_VLAN_COUNT; i++) {
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vlan_res = a5psw_reg_readl(a5psw, A5PSW_VLAN_RES(i));
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if (FIELD_GET(A5PSW_VLAN_RES_VLANID, vlan_res) == vid)
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return i;
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}
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return -1;
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}
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static int a5psw_new_vlan_res_entry(struct a5psw *a5psw, u16 newvid)
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{
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u32 vlan_res;
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int i;
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/* Find a free VLAN entry */
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for (i = 0; i < A5PSW_VLAN_COUNT; i++) {
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vlan_res = a5psw_reg_readl(a5psw, A5PSW_VLAN_RES(i));
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if (!(FIELD_GET(A5PSW_VLAN_RES_PORTMASK, vlan_res))) {
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vlan_res = FIELD_PREP(A5PSW_VLAN_RES_VLANID, newvid);
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a5psw_reg_writel(a5psw, A5PSW_VLAN_RES(i), vlan_res);
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return i;
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}
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}
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return -1;
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}
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static void a5psw_port_vlan_tagged_cfg(struct a5psw *a5psw,
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unsigned int vlan_res_id, int port,
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bool set)
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{
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u32 mask = A5PSW_VLAN_RES_WR_PORTMASK | A5PSW_VLAN_RES_RD_TAGMASK |
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BIT(port);
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u32 vlan_res_off = A5PSW_VLAN_RES(vlan_res_id);
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u32 val = A5PSW_VLAN_RES_WR_TAGMASK, reg;
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if (set)
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val |= BIT(port);
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/* Toggle tag mask read */
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a5psw_reg_writel(a5psw, vlan_res_off, A5PSW_VLAN_RES_RD_TAGMASK);
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reg = a5psw_reg_readl(a5psw, vlan_res_off);
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a5psw_reg_writel(a5psw, vlan_res_off, A5PSW_VLAN_RES_RD_TAGMASK);
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reg &= ~mask;
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reg |= val;
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a5psw_reg_writel(a5psw, vlan_res_off, reg);
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}
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static void a5psw_port_vlan_cfg(struct a5psw *a5psw, unsigned int vlan_res_id,
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int port, bool set)
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{
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u32 mask = A5PSW_VLAN_RES_WR_TAGMASK | BIT(port);
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u32 reg = A5PSW_VLAN_RES_WR_PORTMASK;
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if (set)
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reg |= BIT(port);
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a5psw_reg_rmw(a5psw, A5PSW_VLAN_RES(vlan_res_id), mask, reg);
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}
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static int a5psw_port_vlan_add(struct dsa_switch *ds, int port,
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const struct switchdev_obj_port_vlan *vlan,
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struct netlink_ext_ack *extack)
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{
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bool tagged = !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED);
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bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
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struct a5psw *a5psw = ds->priv;
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u16 vid = vlan->vid;
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int vlan_res_id;
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dev_dbg(a5psw->dev, "Add VLAN %d on port %d, %s, %s\n",
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vid, port, tagged ? "tagged" : "untagged",
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pvid ? "PVID" : "no PVID");
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vlan_res_id = a5psw_find_vlan_entry(a5psw, vid);
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if (vlan_res_id < 0) {
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vlan_res_id = a5psw_new_vlan_res_entry(a5psw, vid);
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if (vlan_res_id < 0)
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return -ENOSPC;
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}
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a5psw_port_vlan_cfg(a5psw, vlan_res_id, port, true);
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if (tagged)
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a5psw_port_vlan_tagged_cfg(a5psw, vlan_res_id, port, true);
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/* Configure port to tag with corresponding VID, but do not enable it
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* yet: wait for vlan filtering to be enabled to enable vlan port
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* tagging
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*/
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if (pvid)
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a5psw_reg_writel(a5psw, A5PSW_SYSTEM_TAGINFO(port), vid);
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return 0;
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}
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static int a5psw_port_vlan_del(struct dsa_switch *ds, int port,
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const struct switchdev_obj_port_vlan *vlan)
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{
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struct a5psw *a5psw = ds->priv;
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u16 vid = vlan->vid;
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int vlan_res_id;
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dev_dbg(a5psw->dev, "Removing VLAN %d on port %d\n", vid, port);
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vlan_res_id = a5psw_find_vlan_entry(a5psw, vid);
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if (vlan_res_id < 0)
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return -EINVAL;
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a5psw_port_vlan_cfg(a5psw, vlan_res_id, port, false);
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a5psw_port_vlan_tagged_cfg(a5psw, vlan_res_id, port, false);
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return 0;
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}
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static u64 a5psw_read_stat(struct a5psw *a5psw, u32 offset, int port)
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{
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u32 reg_lo, reg_hi;
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@ -756,6 +896,27 @@ static void a5psw_get_eth_ctrl_stats(struct dsa_switch *ds, int port,
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ctrl_stats->MACControlFramesReceived = stat;
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}
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static void a5psw_vlan_setup(struct a5psw *a5psw, int port)
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{
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u32 reg;
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/* Enable TAG always mode for the port, this is actually controlled
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* by VLAN_IN_MODE_ENA field which will be used for PVID insertion
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*/
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reg = A5PSW_VLAN_IN_MODE_TAG_ALWAYS;
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reg <<= A5PSW_VLAN_IN_MODE_PORT_SHIFT(port);
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a5psw_reg_rmw(a5psw, A5PSW_VLAN_IN_MODE, A5PSW_VLAN_IN_MODE_PORT(port),
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reg);
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/* Set transparent mode for output frame manipulation, this will depend
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* on the VLAN_RES configuration mode
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*/
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reg = A5PSW_VLAN_OUT_MODE_TRANSPARENT;
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reg <<= A5PSW_VLAN_OUT_MODE_PORT_SHIFT(port);
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a5psw_reg_rmw(a5psw, A5PSW_VLAN_OUT_MODE,
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A5PSW_VLAN_OUT_MODE_PORT(port), reg);
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}
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static int a5psw_setup(struct dsa_switch *ds)
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{
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struct a5psw *a5psw = ds->priv;
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@ -830,6 +991,8 @@ static int a5psw_setup(struct dsa_switch *ds)
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/* Enable standalone mode for user ports */
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if (dsa_port_is_user(dp))
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a5psw_port_set_standalone(a5psw, port, true);
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a5psw_vlan_setup(a5psw, port);
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}
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return 0;
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@ -859,6 +1022,9 @@ static const struct dsa_switch_ops a5psw_switch_ops = {
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.port_bridge_flags = a5psw_port_bridge_flags,
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.port_stp_state_set = a5psw_port_stp_state_set,
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.port_fast_age = a5psw_port_fast_age,
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.port_vlan_filtering = a5psw_port_vlan_filtering,
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.port_vlan_add = a5psw_port_vlan_add,
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.port_vlan_del = a5psw_port_vlan_del,
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.port_fdb_add = a5psw_port_fdb_add,
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.port_fdb_del = a5psw_port_fdb_del,
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.port_fdb_dump = a5psw_port_fdb_dump,
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@ -51,7 +51,9 @@
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#define A5PSW_VLAN_IN_MODE_TAG_ALWAYS 0x2
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#define A5PSW_VLAN_OUT_MODE 0x2C
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#define A5PSW_VLAN_OUT_MODE_PORT(port) (GENMASK(1, 0) << ((port) * 2))
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#define A5PSW_VLAN_OUT_MODE_PORT_SHIFT(port) ((port) * 2)
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#define A5PSW_VLAN_OUT_MODE_PORT(port) (GENMASK(1, 0) << \
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A5PSW_VLAN_OUT_MODE_PORT_SHIFT(port))
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#define A5PSW_VLAN_OUT_MODE_DIS 0x0
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#define A5PSW_VLAN_OUT_MODE_STRIP 0x1
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#define A5PSW_VLAN_OUT_MODE_TAG_THROUGH 0x2
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@ -60,7 +62,7 @@
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#define A5PSW_VLAN_IN_MODE_ENA 0x30
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#define A5PSW_VLAN_TAG_ID 0x34
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#define A5PSW_SYSTEM_TAGINFO(port) (0x200 + A5PSW_PORT_OFFSET(port))
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#define A5PSW_SYSTEM_TAGINFO(port) (0x200 + 4 * (port))
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#define A5PSW_AUTH_PORT(port) (0x240 + 4 * (port))
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#define A5PSW_AUTH_PORT_AUTHORIZED BIT(0)
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@ -69,7 +71,7 @@
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#define A5PSW_VLAN_RES_WR_PORTMASK BIT(30)
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#define A5PSW_VLAN_RES_WR_TAGMASK BIT(29)
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#define A5PSW_VLAN_RES_RD_TAGMASK BIT(28)
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#define A5PSW_VLAN_RES_ID GENMASK(16, 5)
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#define A5PSW_VLAN_RES_VLANID GENMASK(16, 5)
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#define A5PSW_VLAN_RES_PORTMASK GENMASK(4, 0)
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#define A5PSW_RXMATCH_CONFIG(port) (0x3e80 + 4 * (port))
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