ARM: dts: aspeed: Add Nuvia DC-SCM BMC
Add initial version of device tree for Nuvia DC-SCM BMC which is equipped with Aspeed AST2600 BMC SoC. Signed-off-by: Graeme Gregory <quic_ggregory@quicinc.com> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Link: https://lore.kernel.org/r/20220325190247.468079-1-quic_jaehyoo@quicinc.com Signed-off-by: Joel Stanley <joel@jms.id.au>
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@ -1546,6 +1546,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
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aspeed-bmc-lenovo-hr630.dtb \
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aspeed-bmc-lenovo-hr855xg2.dtb \
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aspeed-bmc-microsoft-olympus.dtb \
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aspeed-bmc-nuvia-dc-scm.dtb \
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aspeed-bmc-opp-lanyang.dtb \
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aspeed-bmc-opp-mihawk.dtb \
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aspeed-bmc-opp-mowgli.dtb \
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arch/arm/boot/dts/aspeed-bmc-nuvia-dc-scm.dts
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190
arch/arm/boot/dts/aspeed-bmc-nuvia-dc-scm.dts
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@ -0,0 +1,190 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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// Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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/dts-v1/;
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#include "aspeed-g6.dtsi"
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/ {
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model = "Nuvia DC-SCM BMC";
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compatible = "nuvia,dc-scm-bmc", "aspeed,ast2600";
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aliases {
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serial4 = &uart5;
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};
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chosen {
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stdout-path = &uart5;
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bootargs = "console=ttyS4,115200n8";
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x40000000>;
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};
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};
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&mdio3 {
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status = "okay";
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ethphy3: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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&mac2 {
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status = "okay";
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/* Bootloader sets up the MAC to insert delay */
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phy-mode = "rgmii";
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phy-handle = <ðphy3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rgmii3_default>;
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};
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&mac3 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rmii4_default>;
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use-ncsi;
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};
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&rtc {
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status = "okay";
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};
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&fmc {
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status = "okay";
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flash@0 {
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status = "okay";
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m25p,fast-read;
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label = "bmc";
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spi-max-frequency = <133000000>;
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#include "openbmc-flash-layout-64.dtsi"
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};
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flash@1 {
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status = "okay";
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m25p,fast-read;
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label = "alt-bmc";
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spi-max-frequency = <133000000>;
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#include "openbmc-flash-layout-64-alt.dtsi"
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};
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};
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&spi1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1_default>;
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flash@0 {
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status = "okay";
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m25p,fast-read;
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label = "bios";
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spi-max-frequency = <133000000>;
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};
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};
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&gpio0 {
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gpio-line-names =
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/*A0-A7*/ "","","","","","","","",
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/*B0-B7*/ "BMC_FLASH_MUX_SEL","","","","","","","",
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/*C0-C7*/ "","","","","","","","",
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/*D0-D7*/ "","","","","","","","",
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/*E0-E7*/ "","","","","","","","",
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/*F0-F7*/ "","","","","","","","",
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/*G0-G7*/ "","","","","","","","",
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/*H0-H7*/ "","","","","","","","",
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/*I0-I7*/ "","","","","","","","",
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/*J0-J7*/ "","","","","","","","",
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/*K0-K7*/ "","","","","","","","",
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/*L0-L7*/ "","","","","","","","",
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/*M0-M7*/ "","","","","","","","",
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/*N0-N7*/ "BMC_FWSPI_RST_N","","GPIO_1_BMC_3V3","","","","","",
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/*O0-O7*/ "JTAG_MUX_A","JTAG_MUX_B","","","","","","",
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/*P0-P7*/ "","","","","","","","",
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/*Q0-Q7*/ "","","","","","","","",
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/*R0-R7*/ "","","","","","","","",
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/*S0-S7*/ "","","","","","","","",
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/*T0-T7*/ "","","","","","","","",
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/*U0-U7*/ "","","","","","","","",
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/*V0-V7*/ "","","","SCMFPGA_SPARE_GPIO1_3V3",
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"SCMFPGA_SPARE_GPIO2_3V3","SCMFPGA_SPARE_GPIO3_3V3",
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"SCMFPGA_SPARE_GPIO4_3V3","SCMFPGA_SPARE_GPIO5_3V3",
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/*W0-W7*/ "","","","","","","","",
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/*X0-X7*/ "","","","","","","","",
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/*Y0-Y7*/ "","","","","","","","",
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/*Z0-Z7*/ "","","","","","","","",
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/*AA0-AA7*/ "","","","","","","","",
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/*AB0-AB7*/ "","","","","","","","",
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/*AC0-AC7*/ "","","","","","","","";
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};
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&gpio1 {
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gpio-line-names =
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/*A0-A7*/ "GPI_1_BMC_1V8","","","","","",
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"SCMFPGA_SPARE_GPIO1_1V8","SCMFPGA_SPARE_GPIO2_1V8",
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/*B0-B7*/ "SCMFPGA_SPARE_GPIO3_1V8","SCMFPGA_SPARE_GPIO4_1V8",
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"SCMFPGA_SPARE_GPIO5_1V8","","","","","",
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/*C0-C7*/ "","","","","","","","",
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/*D0-D7*/ "","BMC_SPI1_RST_N","BIOS_FLASH_MUX_SEL","",
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"","TPM2_PIRQ_N","TPM2_RST_N","",
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/*E0-E7*/ "","","","","","","","";
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};
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&i2c2 {
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status = "okay";
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};
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&i2c4 {
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status = "okay";
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};
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&i2c5 {
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status = "okay";
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};
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&i2c6 {
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status = "okay";
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};
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&i2c7 {
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status = "okay";
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};
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&i2c8 {
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status = "okay";
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};
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&i2c9 {
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status = "okay";
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};
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&i2c10 {
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status = "okay";
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};
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&i2c12 {
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status = "okay";
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};
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&i2c13 {
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status = "okay";
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};
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&i2c14 {
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status = "okay";
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};
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&i2c15 {
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status = "okay";
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};
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&vhub {
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status = "okay";
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};
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