IRQCHIP: bcm7120-l2: Add support for BCM3380-style controllers
These controllers support multiple enable/status pairs (64+ IRQs), can put the enable/status words at different offsets, and do not support multiple parent IRQs. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8843/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -0,0 +1,41 @@
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Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
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This interrupt controller shows up in various forms on many BCM338x/BCM63xx
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chipsets. It has the following properties:
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- outputs a single interrupt signal to its interrupt controller parent
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- contains one or more enable/status word pairs, which often appear at
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different offsets in different blocks
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- no atomic set/clear operations
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Required properties:
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- compatible: should be "brcm,bcm3380-l2-intc"
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- reg: specifies one or more enable/status pairs, in the following format:
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<enable_reg 0x4 status_reg 0x4>...
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: specifies the number of cells needed to encode an interrupt
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source, should be 1.
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- interrupt-parent: specifies the phandle to the parent interrupt controller
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this one is cascaded from
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- interrupts: specifies the interrupt line in the interrupt-parent controller
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node, valid values depend on the type of parent interrupt controller
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Optional properties:
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- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
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wakeup source for system suspend/resume.
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Example:
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irq0_intc: interrupt-controller@10000020 {
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compatible = "brcm,bcm3380-l2-intc";
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reg = <0x10000024 0x4 0x1000002c 0x4>,
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<0x10000020 0x4 0x10000028 0x4>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <2>;
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};
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@ -14,6 +14,7 @@
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/kconfig.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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@ -120,10 +121,15 @@ static int bcm7120_l2_intc_init_one(struct device_node *dn,
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/* For multiple parent IRQs with multiple words, this looks like:
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* <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
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*/
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for (idx = 0; idx < data->n_words; idx++)
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data->irq_map_mask[idx] |=
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be32_to_cpup(data->map_mask_prop +
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irq * data->n_words + idx);
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for (idx = 0; idx < data->n_words; idx++) {
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if (data->map_mask_prop) {
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data->irq_map_mask[idx] |=
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be32_to_cpup(data->map_mask_prop +
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irq * data->n_words + idx);
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} else {
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data->irq_map_mask[idx] = 0xffffffff;
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}
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}
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irq_set_handler_data(parent_irq, data);
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irq_set_chained_handler(parent_irq, bcm7120_l2_intc_irq_handle);
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@ -165,6 +171,37 @@ static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
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return 0;
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}
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static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
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struct bcm7120_l2_intc_data *data)
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{
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unsigned int gc_idx;
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for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
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unsigned int map_idx = gc_idx * 2;
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void __iomem *en = of_iomap(dn, map_idx + 0);
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void __iomem *stat = of_iomap(dn, map_idx + 1);
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void __iomem *base = min(en, stat);
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data->map_base[map_idx + 0] = en;
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data->map_base[map_idx + 1] = stat;
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if (!base)
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break;
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data->pair_base[gc_idx] = base;
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data->en_offset[gc_idx] = en - base;
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data->stat_offset[gc_idx] = stat - base;
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}
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if (!gc_idx) {
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pr_err("unable to map registers\n");
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return -EINVAL;
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}
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data->n_words = gc_idx;
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return 0;
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}
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int __init bcm7120_l2_intc_probe(struct device_node *dn,
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struct device_node *parent,
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int (*iomap_regs_fn)(struct device_node *,
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@ -279,5 +316,15 @@ int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
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"BCM7120 L2");
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}
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int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
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struct device_node *parent)
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{
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return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
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"BCM3380 L2");
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}
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IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc",
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bcm7120_l2_intc_probe_7120);
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IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc",
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bcm7120_l2_intc_probe_3380);
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