drm/amdgpu/powerplay: add renoir funcs to support dc
there are two paths for renoir dc access smu. one dc access smu directly using bios smc interface: set disply, dprefclk, etc. another goes through pplib for get dpm clock table and set watermmark. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hersen Wu
Alex Deucher
parent
5bcc92407c
commit
7bbdbe4059
@ -589,10 +589,9 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
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if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
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pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
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&wm_with_clock_ranges);
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else if (adev->smu.funcs &&
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adev->smu.funcs->set_watermarks_for_clock_ranges)
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else
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smu_set_watermarks_for_clock_ranges(&adev->smu,
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&wm_with_clock_ranges);
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&wm_with_clock_ranges);
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}
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void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
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@ -665,7 +664,6 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
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{
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const struct dc_context *ctx = pp->dm;
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struct amdgpu_device *adev = ctx->driver_context;
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struct smu_context *smu = &adev->smu;
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struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
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struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
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wm_with_clock_ranges.wm_dmif_clocks_ranges;
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@ -708,15 +706,7 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
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ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
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}
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if (!smu->funcs)
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return PP_SMU_RESULT_UNSUPPORTED;
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/* 0: successful or smu.funcs->set_watermarks_for_clock_ranges = NULL;
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* 1: fail
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*/
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if (smu_set_watermarks_for_clock_ranges(&adev->smu,
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&wm_with_clock_ranges))
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return PP_SMU_RESULT_UNSUPPORTED;
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smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges);
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return PP_SMU_RESULT_OK;
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}
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@ -1813,6 +1813,41 @@ int smu_set_df_cstate(struct smu_context *smu,
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return ret;
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}
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int smu_write_watermarks_table(struct smu_context *smu)
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{
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int ret = 0;
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struct smu_table_context *smu_table = &smu->smu_table;
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struct smu_table *table = NULL;
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table = &smu_table->tables[SMU_TABLE_WATERMARKS];
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if (!table->cpu_addr)
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return -EINVAL;
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ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
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true);
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return ret;
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}
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int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
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{
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int ret = 0;
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struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
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void *table = watermarks->cpu_addr;
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if (!smu->disable_watermark &&
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smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
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smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
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smu_set_watermarks_table(smu, table, clock_ranges);
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smu->watermarks_bitmap |= WATERMARKS_EXIST;
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smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
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}
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return ret;
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}
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const struct amd_ip_funcs smu_ip_funcs = {
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.name = "smu",
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.early_init = smu_early_init,
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@ -470,6 +470,7 @@ struct pptable_funcs {
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uint32_t dpm_level, uint32_t *freq);
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int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
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int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
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int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
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};
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struct smu_funcs
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@ -495,7 +496,6 @@ struct smu_funcs
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int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
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int (*set_tool_table_location)(struct smu_context *smu);
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int (*notify_memory_pool_location)(struct smu_context *smu);
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int (*write_watermarks_table)(struct smu_context *smu);
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int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
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int (*system_features_control)(struct smu_context *smu, bool en);
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int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
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@ -533,8 +533,6 @@ struct smu_funcs
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int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
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struct smu_clock_info *clocks);
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int (*notify_smu_enable_pwe)(struct smu_context *smu);
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int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
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int (*conv_power_profile_to_pplib_workload)(int power_profile);
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uint32_t (*get_fan_control_mode)(struct smu_context *smu);
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int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
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@ -599,9 +597,6 @@ struct smu_funcs
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((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
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#define smu_gfx_off_control(smu, enable) \
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((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
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#define smu_write_watermarks_table(smu) \
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((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
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#define smu_set_last_dcef_min_deep_sleep_clk(smu) \
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((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
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#define smu_system_features_control(smu, en) \
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@ -741,8 +736,6 @@ struct smu_funcs
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((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
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#define smu_notify_smu_enable_pwe(smu) \
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((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
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#define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
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((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
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#define smu_dpm_set_uvd_enable(smu, enable) \
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((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
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#define smu_dpm_set_vce_enable(smu, enable) \
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@ -781,9 +774,10 @@ struct smu_funcs
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((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
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#define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \
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((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
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#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
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((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
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#define smu_get_dpm_clock_table(smu, clock_table) \
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((smu)->ppt_funcs->get_dpm_clock_table ? (smu)->ppt_funcs->get_dpm_clock_table((smu), (clock_table)) : -EINVAL)
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#define smu_override_pcie_parameters(smu) \
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((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
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@ -823,6 +817,10 @@ int smu_sys_get_pp_table(struct smu_context *smu, void **table);
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int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
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int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
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enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
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int smu_write_watermarks_table(struct smu_context *smu);
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int smu_set_watermarks_for_clock_ranges(
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struct smu_context *smu,
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
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/* smu to display interface */
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extern int smu_display_configuration_change(struct smu_context *smu, const
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@ -416,6 +416,40 @@ static int renoir_get_profiling_clk_mask(struct smu_context *smu,
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return 0;
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}
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/**
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* This interface get dpm clock table for dc
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*/
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static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
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{
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DpmClocks_t *table = smu->smu_table.clocks_table;
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int i;
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if (!clock_table || !table)
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return -EINVAL;
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for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) {
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clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
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clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
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}
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for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) {
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clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
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clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
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}
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for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) {
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clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
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clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
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}
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for (i = 0; i< PP_SMU_NUM_MEMCLK_DPM_LEVELS; i++) {
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clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
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clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
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}
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return 0;
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}
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static int renoir_force_clk_levels(struct smu_context *smu,
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enum smu_clk_type clk_type, uint32_t mask)
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{
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@ -546,6 +580,66 @@ static int renoir_set_performance_level(struct smu_context *smu, enum amd_dpm_fo
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return ret;
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}
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/* save watermark settings into pplib smu structure,
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* also pass data to smu controller
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*/
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static int renoir_set_watermarks_table(
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struct smu_context *smu,
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void *watermarks,
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
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{
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int i;
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int ret = 0;
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Watermarks_t *table = watermarks;
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if (!table || !clock_ranges)
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return -EINVAL;
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if (clock_ranges->num_wm_dmif_sets > 4 ||
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clock_ranges->num_wm_mcif_sets > 4)
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return -EINVAL;
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/* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
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for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
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table->WatermarkRow[WM_DCFCLK][i].MinClock =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz));
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table->WatermarkRow[WM_DCFCLK][i].MaxClock =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz));
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table->WatermarkRow[WM_DCFCLK][i].MinMclk =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz));
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table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz));
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table->WatermarkRow[WM_DCFCLK][i].WmSetting = (uint8_t)
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clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
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}
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for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
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table->WatermarkRow[WM_SOCCLK][i].MinClock =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz));
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table->WatermarkRow[WM_SOCCLK][i].MaxClock =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz));
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table->WatermarkRow[WM_SOCCLK][i].MinMclk =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz));
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table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
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cpu_to_le16((uint16_t)
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(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz));
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table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
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clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
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}
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/* pass data to smu controller */
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ret = smu_write_watermarks_table(smu);
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return ret;
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}
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static const struct pptable_funcs renoir_ppt_funcs = {
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.get_smu_msg_index = renoir_get_smu_msg_index,
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.get_smu_table_index = renoir_get_smu_table_index,
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@ -562,6 +656,8 @@ static const struct pptable_funcs renoir_ppt_funcs = {
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.force_clk_levels = renoir_force_clk_levels,
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.set_power_profile_mode = renoir_set_power_profile_mode,
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.set_performance_level = renoir_set_performance_level,
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.get_dpm_clock_table = renoir_get_dpm_clock_table,
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.set_watermarks_table = renoir_set_watermarks_table,
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};
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void renoir_set_ppt_funcs(struct smu_context *smu)
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@ -771,23 +771,6 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
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return ret;
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}
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static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
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{
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int ret = 0;
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struct smu_table_context *smu_table = &smu->smu_table;
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struct smu_table *table = NULL;
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table = &smu_table->tables[SMU_TABLE_WATERMARKS];
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if (!table->cpu_addr)
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return -EINVAL;
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ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
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true);
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return ret;
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}
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static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
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{
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int ret;
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@ -1337,26 +1320,6 @@ failed:
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return ret;
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}
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static int
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smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
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dm_pp_wm_sets_with_clock_ranges_soc15
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*clock_ranges)
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{
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int ret = 0;
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struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
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void *table = watermarks->cpu_addr;
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if (!smu->disable_watermark &&
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smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
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smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
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smu_set_watermarks_table(smu, table, clock_ranges);
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smu->watermarks_bitmap |= WATERMARKS_EXIST;
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smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
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}
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return ret;
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}
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static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
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{
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int ret = 0;
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@ -1855,7 +1818,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
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.parse_pptable = smu_v11_0_parse_pptable,
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.populate_smc_tables = smu_v11_0_populate_smc_pptable,
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.write_pptable = smu_v11_0_write_pptable,
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.write_watermarks_table = smu_v11_0_write_watermarks_table,
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.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
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.set_tool_table_location = smu_v11_0_set_tool_table_location,
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.init_display_count = smu_v11_0_init_display_count,
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@ -1871,7 +1833,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
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.read_sensor = smu_v11_0_read_sensor,
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.set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
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.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
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.set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
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.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
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.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
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.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
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||||
|
||||
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