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clk: sunxi: Add support for the H3 usb phy clocks

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The H3 has a usb-phy clk register which is similar to that of earlier
SoCs, but with support for a larger number of phys. So we can simply add
a new set of clk-data and a new compatible and be done with it.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Reinder de Haan 2015-11-15 20:46:13 +01:00 committed by Maxime Ripard
parent 8005c49d9a
commit 7bec0200ac
2 changed files with 13 additions and 0 deletions
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1
Documentation/devicetree/bindings/clock/sunxi.txt
View File

@ -68,6 +68,7 @@ Required properties:
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
"allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23
"allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80

12
drivers/clk/sunxi/clk-usb.c
View File

@ -243,3 +243,15 @@ static void __init sun9i_a80_usb_phy_setup(struct device_node *node)
sunxi_usb_clk_setup(node, &sun9i_a80_usb_phy_data, &a80_usb_phy_lock);
}
CLK_OF_DECLARE(sun9i_a80_usb_phy, "allwinner,sun9i-a80-usb-phy-clk", sun9i_a80_usb_phy_setup);
static const struct usb_clk_data sun8i_h3_usb_clk_data __initconst = {
.clk_mask = BIT(19) | BIT(18) | BIT(17) | BIT(16) |
BIT(11) | BIT(10) | BIT(9) | BIT(8),
.reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
};
static void __init sun8i_h3_usb_setup(struct device_node *node)
{
sunxi_usb_clk_setup(node, &sun8i_h3_usb_clk_data, &sun4i_a10_usb_lock);
}
CLK_OF_DECLARE(sun8i_h3_usb, "allwinner,sun8i-h3-usb-clk", sun8i_h3_usb_setup);