staging: mt7621-gpio: avoid custom irq_domain for gpio
Instead of create a custom irq_domain for this chip, use 'gpiochip_set_chained_irqchip' from GPIOLIB_IRQCHIP. It is ok to call this function several times. We have to manually mark the line with 'IRQF_SHARED' and then loop over the three banks until you find a hit. There were some problems with removing an irqchip like that but this driver is a bool so it might work just fine. After this changes the functions 'mediatek_gpio_to_irq' is not needed anymore and also the 'gpio_irq_domain' field from the state container. Instead of use the custom irq domain in the irq handler use the associated domain from the gpio_chip in 'irq_find_mapping' function. Function 'mediatek_gpio_bank_probe' has been moved a it to the botton to have all the irq related functions together and avoid some forward declarations to resolve some symbols along the code. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sergio Paracuellos
Greg Kroah-Hartman
parent
368d97d69d
commit
7bf3d70e6e
@ -2,6 +2,7 @@ config GPIO_MT7621
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bool "Mediatek GPIO Support"
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depends on SOC_MT7620 || SOC_MT7621 || COMPILE_TEST
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select GPIO_GENERIC
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select GPIOLIB_IRQCHIP
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select ARCH_REQUIRE_GPIOLIB
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help
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Say yes here to support the Mediatek SoC GPIO device
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@ -8,7 +8,6 @@
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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@ -58,14 +57,12 @@ struct mtk_gc {
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* @dev: device instance
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* @gpio_membase: memory base address
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* @gpio_irq: irq number from the device tree
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* @gpio_irq_domain: irq domain for this chip
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* @gc_map: array of the gpio chips
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*/
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struct mtk_data {
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struct device *dev;
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void __iomem *gpio_membase;
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int gpio_irq;
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struct irq_domain *gpio_irq_domain;
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struct mtk_gc gc_map[MTK_BANK_CNT];
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};
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@ -95,98 +92,36 @@ mtk_gpio_r32(struct mtk_gc *rg, u32 offset)
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return gc->read_reg(gpio_data->gpio_membase + offset);
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}
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static int
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mediatek_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
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static irqreturn_t
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mediatek_gpio_irq_handler(int irq, void *data)
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{
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struct mtk_data *gpio_data = gpiochip_get_data(chip);
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struct mtk_gc *rg = to_mediatek_gpio(chip);
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struct gpio_chip *gc = data;
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struct mtk_gc *rg = to_mediatek_gpio(gc);
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irqreturn_t ret = IRQ_NONE;
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unsigned long pending;
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int bit;
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return irq_create_mapping(gpio_data->gpio_irq_domain,
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pin + (rg->bank * MTK_BANK_WIDTH));
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}
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static int
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mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
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{
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struct mtk_data *gpio = dev_get_drvdata(&pdev->dev);
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const __be32 *id = of_get_property(bank, "reg", NULL);
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struct mtk_gc *rg;
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void __iomem *dat, *set, *ctrl, *diro;
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int ret;
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if (!id || be32_to_cpu(*id) >= MTK_BANK_CNT)
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return -EINVAL;
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rg = &gpio->gc_map[be32_to_cpu(*id)];
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memset(rg, 0, sizeof(*rg));
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spin_lock_init(&rg->lock);
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rg->chip.of_node = bank;
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rg->bank = be32_to_cpu(*id);
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dat = gpio->gpio_membase + GPIO_REG_DATA + (rg->bank * GPIO_BANK_WIDE);
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set = gpio->gpio_membase + GPIO_REG_DSET + (rg->bank * GPIO_BANK_WIDE);
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ctrl = gpio->gpio_membase + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_WIDE);
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diro = gpio->gpio_membase + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_WIDE);
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ret = bgpio_init(&rg->chip, &pdev->dev, 4,
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dat, set, ctrl, diro, NULL, 0);
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if (ret) {
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dev_err(&pdev->dev, "bgpio_init() failed\n");
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return ret;
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}
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if (gpio->gpio_irq_domain)
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rg->chip.to_irq = mediatek_gpio_to_irq;
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ret = devm_gpiochip_add_data(&pdev->dev, &rg->chip, gpio);
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if (ret < 0) {
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dev_err(&pdev->dev, "Could not register gpio %d, ret=%d\n",
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rg->chip.ngpio, ret);
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return ret;
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}
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/* set polarity to low for all gpios */
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mtk_gpio_w32(rg, GPIO_REG_POL, 0);
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dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
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return 0;
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}
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static void
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mediatek_gpio_irq_handler(struct irq_desc *desc)
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{
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struct mtk_data *gpio_data = irq_desc_get_handler_data(desc);
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int i;
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for (i = 0; i < MTK_BANK_CNT; i++) {
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struct mtk_gc *rg = &gpio_data->gc_map[i];
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unsigned long pending;
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int bit;
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if (!rg)
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continue;
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pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
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pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
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if (pending) {
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for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
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u32 map = irq_find_mapping(gpio_data->gpio_irq_domain,
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(MTK_BANK_WIDTH * i) + bit);
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u32 map = irq_find_mapping(gc->irq.domain, bit);
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generic_handle_irq(map);
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mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
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ret |= IRQ_HANDLED;
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}
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}
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return ret;
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}
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static void
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mediatek_gpio_irq_unmask(struct irq_data *d)
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{
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struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct mtk_gc *rg = to_mediatek_gpio(gc);
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int pin = d->hwirq;
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int bank = pin / MTK_BANK_WIDTH;
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struct mtk_gc *rg = &gpio_data->gc_map[bank];
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unsigned long flags;
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u32 rise, fall, high, low;
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@ -208,10 +143,9 @@ mediatek_gpio_irq_unmask(struct irq_data *d)
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static void
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mediatek_gpio_irq_mask(struct irq_data *d)
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{
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struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct mtk_gc *rg = to_mediatek_gpio(gc);
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int pin = d->hwirq;
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int bank = pin / MTK_BANK_WIDTH;
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struct mtk_gc *rg = &gpio_data->gc_map[bank];
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unsigned long flags;
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u32 rise, fall, high, low;
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@ -233,10 +167,9 @@ mediatek_gpio_irq_mask(struct irq_data *d)
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static int
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mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
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{
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struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct mtk_gc *rg = to_mediatek_gpio(gc);
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int pin = d->hwirq;
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int bank = pin / MTK_BANK_WIDTH;
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struct mtk_gc *rg = &gpio_data->gc_map[bank];
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u32 mask = PIN_MASK(pin);
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if (!rg)
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@ -277,65 +210,84 @@ mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
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return 0;
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}
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static int mediatek_irq_reqres(struct irq_data *d)
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{
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struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d);
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int bank = irqd_to_hwirq(d) / MTK_BANK_WIDTH;
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struct mtk_gc *rg = &gpio_data->gc_map[bank];
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struct gpio_chip *gc = &rg->chip;
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int ret;
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ret = gpiochip_lock_as_irq(gc, irqd_to_hwirq(d));
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if (ret) {
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dev_err(gpio_data->dev, "unable to lock HW IRQ %lu for IRQ\n",
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irqd_to_hwirq(d));
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return -EINVAL;
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}
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return 0;
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}
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static void mediatek_irq_relres(struct irq_data *d)
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{
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struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d);
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int bank = irqd_to_hwirq(d) / MTK_BANK_WIDTH;
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struct mtk_gc *rg = &gpio_data->gc_map[bank];
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struct gpio_chip *gc = &rg->chip;
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gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
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}
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static struct irq_chip mediatek_gpio_irq_chip = {
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.name = "GPIO",
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.irq_unmask = mediatek_gpio_irq_unmask,
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.irq_mask = mediatek_gpio_irq_mask,
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.irq_mask_ack = mediatek_gpio_irq_mask,
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.irq_set_type = mediatek_gpio_irq_type,
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.irq_request_resources = mediatek_irq_reqres,
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.irq_release_resources = mediatek_irq_relres,
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};
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static int
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mediatek_gpio_gpio_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
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{
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struct mtk_data *gpio = dev_get_drvdata(&pdev->dev);
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const __be32 *id = of_get_property(bank, "reg", NULL);
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struct mtk_gc *rg;
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void __iomem *dat, *set, *ctrl, *diro;
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int ret;
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ret = irq_set_chip_data(irq, d->host_data);
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if (ret < 0)
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if (!id || be32_to_cpu(*id) >= MTK_BANK_CNT)
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return -EINVAL;
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rg = &gpio->gc_map[be32_to_cpu(*id)];
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memset(rg, 0, sizeof(*rg));
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spin_lock_init(&rg->lock);
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rg->chip.of_node = bank;
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rg->bank = be32_to_cpu(*id);
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dat = gpio->gpio_membase + GPIO_REG_DATA + (rg->bank * GPIO_BANK_WIDE);
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set = gpio->gpio_membase + GPIO_REG_DSET + (rg->bank * GPIO_BANK_WIDE);
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ctrl = gpio->gpio_membase + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_WIDE);
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diro = gpio->gpio_membase + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_WIDE);
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ret = bgpio_init(&rg->chip, &pdev->dev, 4,
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dat, set, ctrl, diro, NULL, 0);
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if (ret) {
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dev_err(&pdev->dev, "bgpio_init() failed\n");
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return ret;
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irq_set_chip_and_handler(irq, &mediatek_gpio_irq_chip,
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handle_level_irq);
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irq_set_handler_data(irq, d);
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}
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ret = devm_gpiochip_add_data(&pdev->dev, &rg->chip, gpio);
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if (ret < 0) {
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dev_err(&pdev->dev, "Could not register gpio %d, ret=%d\n",
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rg->chip.ngpio, ret);
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return ret;
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}
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/*
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* Manually request the irq here instead of passing a flow-handler
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* to gpiochip_set_chained_irqchip, because the irq is shared.
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*/
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ret = devm_request_irq(&pdev->dev, gpio->gpio_irq,
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mediatek_gpio_irq_handler, IRQF_SHARED,
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"mt7621", &rg->chip);
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if (ret) {
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dev_err(&pdev->dev, "Error requesting IRQ %d: %d\n",
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gpio->gpio_irq, ret);
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return ret;
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}
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ret = gpiochip_irqchip_add(&rg->chip, &mediatek_gpio_irq_chip,
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0, handle_simple_irq, IRQ_TYPE_NONE);
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if (ret) {
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dev_err(&pdev->dev, "failed to add gpiochip_irqchip\n");
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return ret;
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}
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gpiochip_set_chained_irqchip(&rg->chip, &mediatek_gpio_irq_chip,
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gpio->gpio_irq, NULL);
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/* set polarity to low for all gpios */
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mtk_gpio_w32(rg, GPIO_REG_POL, 0);
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dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
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return 0;
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}
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static const struct irq_domain_ops irq_domain_ops = {
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.xlate = irq_domain_xlate_twocell,
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.map = mediatek_gpio_gpio_map,
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};
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static int
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mediatek_gpio_probe(struct platform_device *pdev)
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{
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@ -352,14 +304,6 @@ mediatek_gpio_probe(struct platform_device *pdev)
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return PTR_ERR(gpio_data->gpio_membase);
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gpio_data->gpio_irq = irq_of_parse_and_map(np, 0);
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if (gpio_data->gpio_irq) {
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gpio_data->gpio_irq_domain = irq_domain_add_linear(np,
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MTK_BANK_CNT * MTK_BANK_WIDTH,
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&irq_domain_ops, gpio_data);
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if (!gpio_data->gpio_irq_domain)
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dev_err(&pdev->dev, "irq_domain_add_linear failed\n");
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}
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gpio_data->dev = &pdev->dev;
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platform_set_drvdata(pdev, gpio_data);
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@ -367,11 +311,6 @@ mediatek_gpio_probe(struct platform_device *pdev)
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if (of_device_is_compatible(bank, "mediatek,mt7621-gpio-bank"))
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mediatek_gpio_bank_probe(pdev, bank);
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if (gpio_data->gpio_irq_domain)
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irq_set_chained_handler_and_data(gpio_data->gpio_irq,
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mediatek_gpio_irq_handler,
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gpio_data);
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return 0;
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}
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