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Merge branches 'next/ar7', 'next/ath79', 'next/bcm63xx', 'next/bmips', 'next/cavium', 'next/generic', 'next/kprobes', 'next/lantiq', 'next/perf' and 'next/raza' into mips-for-linux-next

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This commit is contained in:
Ralf Baechle 2012-01-11 15:42:31 +01:00
commit 7bf6612e8a
194 changed files with 15445 additions and 2375 deletions
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84
arch/mips/Kconfig
View File

@ -716,7 +716,6 @@ config CAVIUM_OCTEON_SIMULATOR
select DMA_COHERENT
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_HOTPLUG_CPU
select SYS_HAS_CPU_CAVIUM_OCTEON
select HOLES_IN_ZONE
@ -732,7 +731,6 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
select DMA_COHERENT
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_HOTPLUG_CPU
select SYS_HAS_EARLY_PRINTK
select SYS_HAS_CPU_CAVIUM_OCTEON
@ -761,7 +759,6 @@ config NLM_XLR_BOARD
depends on EXPERIMENTAL
select BOOT_ELF32
select NLM_COMMON
select NLM_XLR
select SYS_HAS_CPU_XLR
select SYS_SUPPORTS_SMP
select HW_HAS_PCI
@ -776,6 +773,7 @@ config NLM_XLR_BOARD
select CEVT_R4K
select CSRC_R4K
select IRQ_CPU
select ARCH_SUPPORTS_MSI
select ZONE_DMA if 64BIT
select SYNC_R4K
select SYS_HAS_EARLY_PRINTK
@ -783,6 +781,33 @@ config NLM_XLR_BOARD
Support for systems based on Netlogic XLR and XLS processors.
Say Y here if you have a XLR or XLS based board.
config NLM_XLP_BOARD
bool "Netlogic XLP based systems"
depends on EXPERIMENTAL
select BOOT_ELF32
select NLM_COMMON
select SYS_HAS_CPU_XLP
select SYS_SUPPORTS_SMP
select HW_HAS_PCI
select SWAP_IO_SPACE
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select 64BIT_PHYS_ADDR
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select DMA_COHERENT
select NR_CPUS_DEFAULT_32
select CEVT_R4K
select CSRC_R4K
select IRQ_CPU
select ZONE_DMA if 64BIT
select SYNC_R4K
select SYS_HAS_EARLY_PRINTK
help
This board is based on Netlogic XLP Processor.
Say Y here if you have a XLP based board.
endchoice
source "arch/mips/alchemy/Kconfig"
@ -1413,51 +1438,36 @@ config CPU_CAVIUM_OCTEON
config CPU_BMIPS3300
bool "BMIPS3300"
depends on SYS_HAS_CPU_BMIPS3300
select DMA_NONCOHERENT
select IRQ_CPU
select SWAP_IO_SPACE
select SYS_SUPPORTS_32BIT_KERNEL
select WEAK_ORDERING
select CPU_BMIPS
help
Broadcom BMIPS3300 processors.
config CPU_BMIPS4350
bool "BMIPS4350"
depends on SYS_HAS_CPU_BMIPS4350
select CPU_SUPPORTS_32BIT_KERNEL
select DMA_NONCOHERENT
select IRQ_CPU
select SWAP_IO_SPACE
select CPU_BMIPS
select SYS_SUPPORTS_SMP
select SYS_SUPPORTS_HOTPLUG_CPU
select WEAK_ORDERING
help
Broadcom BMIPS4350 ("VIPER") processors.
config CPU_BMIPS4380
bool "BMIPS4380"
depends on SYS_HAS_CPU_BMIPS4380
select CPU_SUPPORTS_32BIT_KERNEL
select DMA_NONCOHERENT
select IRQ_CPU
select SWAP_IO_SPACE
select CPU_BMIPS
select SYS_SUPPORTS_SMP
select SYS_SUPPORTS_HOTPLUG_CPU
select WEAK_ORDERING
help
Broadcom BMIPS4380 processors.
config CPU_BMIPS5000
bool "BMIPS5000"
depends on SYS_HAS_CPU_BMIPS5000
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_BMIPS
select CPU_SUPPORTS_HIGHMEM
select DMA_NONCOHERENT
select IRQ_CPU
select SWAP_IO_SPACE
select MIPS_CPU_SCACHE
select SYS_SUPPORTS_SMP
select SYS_SUPPORTS_HOTPLUG_CPU
select WEAK_ORDERING
help
Broadcom BMIPS5000 processors.
@ -1472,6 +1482,19 @@ config CPU_XLR
select CPU_SUPPORTS_HUGEPAGES
help
Netlogic Microsystems XLR/XLS processors.
config CPU_XLP
bool "Netlogic XLP SoC"
depends on SYS_HAS_CPU_XLP
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
select CPU_HAS_LLSC
select WEAK_ORDERING
select WEAK_REORDERING_BEYOND_LLSC
select CPU_HAS_PREFETCH
help
Netlogic Microsystems XLP processors.
endchoice
if CPU_LOONGSON2F
@ -1518,6 +1541,15 @@ config CPU_LOONGSON2
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
config CPU_BMIPS
bool
select CPU_MIPS32
select CPU_SUPPORTS_32BIT_KERNEL
select DMA_NONCOHERENT
select IRQ_CPU
select SWAP_IO_SPACE
select WEAK_ORDERING
config SYS_HAS_CPU_LOONGSON2E
bool
@ -1605,6 +1637,9 @@ config SYS_HAS_CPU_BMIPS5000
config SYS_HAS_CPU_XLR
bool
config SYS_HAS_CPU_XLP
bool
#
# CPU may reorder R->R, R->W, W->R, W->W
# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
@ -1992,6 +2027,9 @@ config CPU_HAS_SMARTMIPS
config CPU_HAS_WB
bool
config XKS01
bool
#
# Vectored interrupt mode is an R2 feature
#

1
arch/mips/Makefile
View File

@ -157,6 +157,7 @@ ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
endif
cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap
cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)

2
arch/mips/ar7/gpio.c
View File

@ -217,7 +217,7 @@ struct titan_gpio_cfg {
u32 func;
};
static struct titan_gpio_cfg titan_gpio_table[] = {
static const struct titan_gpio_cfg titan_gpio_table[] = {
/* reg, start bit, mux value */
{4, 24, 1},
{4, 26, 1},

37
arch/mips/ar7/platform.c
View File

@ -462,6 +462,40 @@ static struct gpio_led fb_fon_leds[] = {
},
};
static struct gpio_led gt701_leds[] = {
{
.name = "inet:green",
.gpio = 13,
.active_low = 1,
},
{
.name = "usb",
.gpio = 12,
.active_low = 1,
},
{
.name = "inet:red",
.gpio = 9,
.active_low = 1,
},
{
.name = "power:red",
.gpio = 7,
.active_low = 1,
},
{
.name = "power:green",
.gpio = 8,
.active_low = 1,
.default_trigger = "default-on",
},
{
.name = "ethernet",
.gpio = 10,
.active_low = 1,
},
};
static struct gpio_led_platform_data ar7_led_data;
static struct platform_device ar7_gpio_leds = {
@ -503,6 +537,9 @@ static void __init detect_leds(void)
} else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) {
ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
ar7_led_data.leds = titan_leds;
} else if (strstr(prid, "GT701")) {
ar7_led_data.num_leds = ARRAY_SIZE(gt701_leds);
ar7_led_data.leds = gt701_leds;
}
}

4
arch/mips/ar7/prom.c
View File

@ -69,7 +69,7 @@ struct psbl_rec {
u32 ffs_size;
};
static __initdata char psp_env_version[] = "TIENV0.8";
static const char psp_env_version[] __initconst = "TIENV0.8";
struct psp_env_chunk {
u8 num;
@ -84,7 +84,7 @@ struct psp_var_map_entry {
char *value;
};
static struct psp_var_map_entry psp_var_map[] = {
static const struct psp_var_map_entry psp_var_map[] = {
{ 1, "cpufrequency" },
{ 2, "memsize" },
{ 3, "flashsize" },

44
arch/mips/ath79/Kconfig
View File

@ -2,13 +2,26 @@ if ATH79
menu "Atheros AR71XX/AR724X/AR913X machine selection"
config ATH79_MACH_AP81
bool "Atheros AP81 reference board"
select SOC_AR913X
select ATH79_DEV_AR913X_WMAC
config ATH79_MACH_AP121
bool "Atheros AP121 reference board"
select SOC_AR933X
select ATH79_DEV_GPIO_BUTTONS
select ATH79_DEV_LEDS_GPIO
select ATH79_DEV_SPI
select ATH79_DEV_USB
select ATH79_DEV_WMAC
help
Say 'Y' here if you want your kernel to support the
Atheros AP121 reference board.
config ATH79_MACH_AP81
bool "Atheros AP81 reference board"
select SOC_AR913X
select ATH79_DEV_GPIO_BUTTONS
select ATH79_DEV_LEDS_GPIO
select ATH79_DEV_SPI
select ATH79_DEV_USB
select ATH79_DEV_WMAC
help
Say 'Y' here if you want your kernel to support the
Atheros AP81 reference board.
@ -19,10 +32,21 @@ config ATH79_MACH_PB44
select ATH79_DEV_GPIO_BUTTONS
select ATH79_DEV_LEDS_GPIO
select ATH79_DEV_SPI
select ATH79_DEV_USB
help
Say 'Y' here if you want your kernel to support the
Atheros PB44 reference board.
config ATH79_MACH_UBNT_XM
bool "Ubiquiti Networks XM (rev 1.0) board"
select SOC_AR724X
select ATH79_DEV_GPIO_BUTTONS
select ATH79_DEV_LEDS_GPIO
select ATH79_DEV_SPI
help
Say 'Y' here if you want your kernel to support the
Ubiquiti Networks XM (rev 1.0) board.
endmenu
config SOC_AR71XX
@ -33,14 +57,15 @@ config SOC_AR71XX
config SOC_AR724X
select USB_ARCH_HAS_EHCI
select USB_ARCH_HAS_OHCI
select HW_HAS_PCI
def_bool n
config SOC_AR913X
select USB_ARCH_HAS_EHCI
def_bool n
config ATH79_DEV_AR913X_WMAC
depends on SOC_AR913X
config SOC_AR933X
select USB_ARCH_HAS_EHCI
def_bool n
config ATH79_DEV_GPIO_BUTTONS
@ -52,4 +77,11 @@ config ATH79_DEV_LEDS_GPIO
config ATH79_DEV_SPI
def_bool n
config ATH79_DEV_USB
def_bool n
config ATH79_DEV_WMAC
depends on (SOC_AR913X || SOC_AR933X)
def_bool n
endif

5
arch/mips/ath79/Makefile
View File

@ -16,13 +16,16 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
# Devices
#
obj-y += dev-common.o
obj-$(CONFIG_ATH79_DEV_AR913X_WMAC) += dev-ar913x-wmac.o
obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
#
# Machines
#
obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o

55
arch/mips/ath79/clock.c
View File

@ -110,6 +110,59 @@ static void __init ar913x_clocks_init(void)
ath79_uart_clk.rate = ath79_ahb_clk.rate;
}
static void __init ar933x_clocks_init(void)
{
u32 clock_ctrl;
u32 cpu_config;
u32 freq;
u32 t;
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
if (t & AR933X_BOOTSTRAP_REF_CLK_40)
ath79_ref_clk.rate = (40 * 1000 * 1000);
else
ath79_ref_clk.rate = (25 * 1000 * 1000);
clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
ath79_cpu_clk.rate = ath79_ref_clk.rate;
ath79_ahb_clk.rate = ath79_ref_clk.rate;
ath79_ddr_clk.rate = ath79_ref_clk.rate;
} else {
cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
freq = ath79_ref_clk.rate / t;
t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
AR933X_PLL_CPU_CONFIG_NINT_MASK;
freq *= t;
t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
if (t == 0)
t = 1;
freq >>= t;
t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
ath79_cpu_clk.rate = freq / t;
t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
ath79_ddr_clk.rate = freq / t;
t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
ath79_ahb_clk.rate = freq / t;
}
ath79_wdt_clk.rate = ath79_ref_clk.rate;
ath79_uart_clk.rate = ath79_ref_clk.rate;
}
void __init ath79_clocks_init(void)
{
if (soc_is_ar71xx())
@ -118,6 +171,8 @@ void __init ath79_clocks_init(void)
ar724x_clocks_init();
else if (soc_is_ar913x())
ar913x_clocks_init();
else if (soc_is_ar933x())
ar933x_clocks_init();
else
BUG();

5
arch/mips/ath79/common.c
View File

@ -30,6 +30,7 @@ u32 ath79_ddr_freq;
EXPORT_SYMBOL_GPL(ath79_ddr_freq);
enum ath79_soc_type ath79_soc;
unsigned int ath79_soc_rev;
void __iomem *ath79_pll_base;
void __iomem *ath79_reset_base;
@ -64,6 +65,8 @@ void ath79_device_reset_set(u32 mask)
reg = AR724X_RESET_REG_RESET_MODULE;
else if (soc_is_ar913x())
reg = AR913X_RESET_REG_RESET_MODULE;
else if (soc_is_ar933x())
reg = AR933X_RESET_REG_RESET_MODULE;
else
BUG();
@ -86,6 +89,8 @@ void ath79_device_reset_clear(u32 mask)
reg = AR724X_RESET_REG_RESET_MODULE;
else if (soc_is_ar913x())
reg = AR913X_RESET_REG_RESET_MODULE;
else if (soc_is_ar933x())
reg = AR933X_RESET_REG_RESET_MODULE;
else
BUG();

60
arch/mips/ath79/dev-ar913x-wmac.c
View File

@ -1,60 +0,0 @@
/*
* Atheros AR913X SoC built-in WMAC device support
*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/ath9k_platform.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "dev-ar913x-wmac.h"
static struct ath9k_platform_data ar913x_wmac_data;
static struct resource ar913x_wmac_resources[] = {
{
.start = AR913X_WMAC_BASE,
.end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1,
.flags = IORESOURCE_MEM,
}, {
.start = ATH79_CPU_IRQ_IP2,
.end = ATH79_CPU_IRQ_IP2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device ar913x_wmac_device = {
.name = "ath9k",
.id = -1,
.resource = ar913x_wmac_resources,
.num_resources = ARRAY_SIZE(ar913x_wmac_resources),
.dev = {
.platform_data = &ar913x_wmac_data,
},
};
void __init ath79_register_ar913x_wmac(u8 *cal_data)
{
if (cal_data)
memcpy(ar913x_wmac_data.eeprom_data, cal_data,
sizeof(ar913x_wmac_data.eeprom_data));
/* reset the WMAC */
ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
mdelay(10);
ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
mdelay(10);
platform_device_register(&ar913x_wmac_device);
}

38
arch/mips/ath79/dev-common.c
View File

@ -20,6 +20,7 @@
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ar933x_uart_platform.h>
#include "common.h"
#include "dev-common.h"
@ -54,6 +55,30 @@ static struct platform_device ath79_uart_device = {
},
};
static struct resource ar933x_uart_resources[] = {
{
.start = AR933X_UART_BASE,
.end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = ATH79_MISC_IRQ_UART,
.end = ATH79_MISC_IRQ_UART,
.flags = IORESOURCE_IRQ,
},
};
static struct ar933x_uart_platform_data ar933x_uart_data;
static struct platform_device ar933x_uart_device = {
.name = "ar933x-uart",
.id = -1,
.resource = ar933x_uart_resources,
.num_resources = ARRAY_SIZE(ar933x_uart_resources),
.dev = {
.platform_data = &ar933x_uart_data,
},
};
void __init ath79_register_uart(void)
{
struct clk *clk;
@ -62,8 +87,17 @@ void __init ath79_register_uart(void)
if (IS_ERR(clk))
panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
ath79_uart_data[0].uartclk = clk_get_rate(clk);
platform_device_register(&ath79_uart_device);
if (soc_is_ar71xx() ||
soc_is_ar724x() ||
soc_is_ar913x()) {
ath79_uart_data[0].uartclk = clk_get_rate(clk);
platform_device_register(&ath79_uart_device);
} else if (soc_is_ar933x()) {
ar933x_uart_data.uartclk = clk_get_rate(clk);
platform_device_register(&ar933x_uart_device);
} else {
BUG();
}
}
static struct platform_device ath79_wdt_device = {

197
arch/mips/ath79/dev-usb.c Normal file
View File

@ -0,0 +1,197 @@
/*
* Atheros AR7XXX/AR9XXX USB Host Controller device
*
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Atheros' 2.6.15 BSP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-usb.h"
static struct resource ath79_ohci_resources[] = {
[0] = {
/* .start and .end fields are filled dynamically */
.flags = IORESOURCE_MEM,
},
[1] = {
.start = ATH79_MISC_IRQ_OHCI,
.end = ATH79_MISC_IRQ_OHCI,
.flags = IORESOURCE_IRQ,
},
};
static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
static struct platform_device ath79_ohci_device = {
.name = "ath79-ohci",
.id = -1,
.resource = ath79_ohci_resources,
.num_resources = ARRAY_SIZE(ath79_ohci_resources),
.dev = {
.dma_mask = &ath79_ohci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource ath79_ehci_resources[] = {
[0] = {
/* .start and .end fields are filled dynamically */
.flags = IORESOURCE_MEM,
},
[1] = {
.start = ATH79_CPU_IRQ_USB,
.end = ATH79_CPU_IRQ_USB,
.flags = IORESOURCE_IRQ,
},
};
static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
static struct platform_device ath79_ehci_device = {
.name = "ath79-ehci",
.id = -1,
.resource = ath79_ehci_resources,
.num_resources = ARRAY_SIZE(ath79_ehci_resources),
.dev = {
.dma_mask = &ath79_ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \
AR71XX_RESET_USB_PHY | \
AR71XX_RESET_USB_OHCI_DLL)
static void __init ath79_usb_setup(void)
{
void __iomem *usb_ctrl_base;
ath79_device_reset_set(AR71XX_USB_RESET_MASK);
mdelay(1000);
ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
/* Turning on the Buff and Desc swap bits */
__raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
/* WAR for HW bug. Here it adjusts the duration between two SOFS */
__raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
iounmap(usb_ctrl_base);
mdelay(900);
ath79_ohci_resources[0].start = AR71XX_OHCI_BASE;
ath79_ohci_resources[0].end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1;
platform_device_register(&ath79_ohci_device);
ath79_ehci_resources[0].start = AR71XX_EHCI_BASE;
ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1;
ath79_ehci_device.name = "ar71xx-ehci";
platform_device_register(&ath79_ehci_device);
}
static void __init ar7240_usb_setup(void)
{
void __iomem *usb_ctrl_base;
ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
ath79_device_reset_set(AR7240_RESET_USB_HOST);
mdelay(1000);
ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
ath79_device_reset_clear(AR7240_RESET_USB_HOST);
usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
/* WAR for HW bug. Here it adjusts the duration between two SOFS */
__raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
iounmap(usb_ctrl_base);
ath79_ohci_resources[0].start = AR7240_OHCI_BASE;
ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1;
platform_device_register(&ath79_ohci_device);
}
static void __init ar724x_usb_setup(void)
{
ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
mdelay(10);
ath79_device_reset_clear(AR724X_RESET_USB_HOST);
mdelay(10);
ath79_device_reset_clear(AR724X_RESET_USB_PHY);
mdelay(10);
ath79_ehci_resources[0].start = AR724X_EHCI_BASE;
ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1;
ath79_ehci_device.name = "ar724x-ehci";
platform_device_register(&ath79_ehci_device);
}
static void __init ar913x_usb_setup(void)
{
ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
mdelay(10);
ath79_device_reset_clear(AR913X_RESET_USB_HOST);
mdelay(10);
ath79_device_reset_clear(AR913X_RESET_USB_PHY);
mdelay(10);
ath79_ehci_resources[0].start = AR913X_EHCI_BASE;
ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1;
ath79_ehci_device.name = "ar913x-ehci";
platform_device_register(&ath79_ehci_device);
}
static void __init ar933x_usb_setup(void)
{
ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
mdelay(10);
ath79_device_reset_clear(AR933X_RESET_USB_HOST);
mdelay(10);
ath79_device_reset_clear(AR933X_RESET_USB_PHY);
mdelay(10);
ath79_ehci_resources[0].start = AR933X_EHCI_BASE;
ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1;
ath79_ehci_device.name = "ar933x-ehci";
platform_device_register(&ath79_ehci_device);
}
void __init ath79_register_usb(void)
{
if (soc_is_ar71xx())
ath79_usb_setup();
else if (soc_is_ar7240())
ar7240_usb_setup();
else if (soc_is_ar7241() || soc_is_ar7242())
ar724x_usb_setup();
else if (soc_is_ar913x())
ar913x_usb_setup();
else if (soc_is_ar933x())
ar933x_usb_setup();
else
BUG();
}

10
arch/mips/ath79/dev-ar913x-wmac.h → arch/mips/ath79/dev-usb.h
View File

@ -1,5 +1,5 @@
/*
* Atheros AR913X SoC built-in WMAC device support
* Atheros AR71XX/AR724X/AR913X USB Host Controller support
*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
@ -9,9 +9,9 @@
* by the Free Software Foundation.
*/
#ifndef _ATH79_DEV_AR913X_WMAC_H
#define _ATH79_DEV_AR913X_WMAC_H
#ifndef _ATH79_DEV_USB_H
#define _ATH79_DEV_USB_H
void ath79_register_ar913x_wmac(u8 *cal_data);
void ath79_register_usb(void);
#endif /* _ATH79_DEV_AR913X_WMAC_H */
#endif /* _ATH79_DEV_USB_H */

109
arch/mips/ath79/dev-wmac.c Normal file
View File

@ -0,0 +1,109 @@
/*
* Atheros AR913X/AR933X SoC built-in WMAC device support
*
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/ath9k_platform.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "dev-wmac.h"
static struct ath9k_platform_data ath79_wmac_data;
static struct resource ath79_wmac_resources[] = {
{
/* .start and .end fields are filled dynamically */
.flags = IORESOURCE_MEM,
}, {
.start = ATH79_CPU_IRQ_IP2,
.end = ATH79_CPU_IRQ_IP2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device ath79_wmac_device = {
.name = "ath9k",
.id = -1,
.resource = ath79_wmac_resources,
.num_resources = ARRAY_SIZE(ath79_wmac_resources),
.dev = {
.platform_data = &ath79_wmac_data,
},
};
static void __init ar913x_wmac_setup(void)
{
/* reset the WMAC */
ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
mdelay(10);
ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
mdelay(10);
ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
}
static int ar933x_wmac_reset(void)
{
ath79_device_reset_clear(AR933X_RESET_WMAC);
ath79_device_reset_set(AR933X_RESET_WMAC);
return 0;
}
static int ar933x_r1_get_wmac_revision(void)
{
return ath79_soc_rev;
}
static void __init ar933x_wmac_setup(void)
{
u32 t;
ar933x_wmac_reset();
ath79_wmac_device.name = "ar933x_wmac";
ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
if (t & AR933X_BOOTSTRAP_REF_CLK_40)
ath79_wmac_data.is_clk_25mhz = false;
else
ath79_wmac_data.is_clk_25mhz = true;
if (ath79_soc_rev == 1)
ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
ath79_wmac_data.external_reset = ar933x_wmac_reset;
}
void __init ath79_register_wmac(u8 *cal_data)
{
if (soc_is_ar913x())
ar913x_wmac_setup();
if (soc_is_ar933x())
ar933x_wmac_setup();
else
BUG();
if (cal_data)
memcpy(ath79_wmac_data.eeprom_data, cal_data,
sizeof(ath79_wmac_data.eeprom_data));
platform_device_register(&ath79_wmac_device);
}

17
arch/mips/ath79/dev-wmac.h Normal file
View File

@ -0,0 +1,17 @@
/*
* Atheros AR913X/AR933X SoC built-in WMAC device support
*
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _ATH79_DEV_WMAC_H
#define _ATH79_DEV_WMAC_H
void ath79_register_wmac(u8 *cal_data);
#endif /* _ATH79_DEV_WMAC_H */

76
arch/mips/ath79/early_printk.c
View File

@ -1,7 +1,7 @@
/*
* Atheros AR71XX/AR724X/AR913X SoC early printk support
* Atheros AR7XXX/AR9XXX SoC early printk support
*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
@ -10,27 +10,85 @@
*/
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/serial_reg.h>
#include <asm/addrspace.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ar933x_uart.h>
static inline void prom_wait_thre(void __iomem *base)
static void (*_prom_putchar) (unsigned char);
static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
{
u32 lsr;
u32 t;
do {
lsr = __raw_readl(base + UART_LSR * 4);
if (lsr & UART_LSR_THRE)
t = __raw_readl(reg);
if ((t & mask) == val)
break;
} while (1);
}
void prom_putchar(unsigned char ch)
static void prom_putchar_ar71xx(unsigned char ch)
{
void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
prom_wait_thre(base);
prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
__raw_writel(ch, base + UART_TX * 4);
prom_wait_thre(base);
prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
}
static void prom_putchar_ar933x(unsigned char ch)
{
void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));
prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
AR933X_UART_DATA_TX_CSR);
__raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG);
prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
AR933X_UART_DATA_TX_CSR);
}
static void prom_putchar_dummy(unsigned char ch)
{
/* nothing to do */
}
static void prom_putchar_init(void)
{
void __iomem *base;
u32 id;
base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE));
id = __raw_readl(base + AR71XX_RESET_REG_REV_ID);
id &= REV_ID_MAJOR_MASK;
switch (id) {
case REV_ID_MAJOR_AR71XX:
case REV_ID_MAJOR_AR7240:
case REV_ID_MAJOR_AR7241:
case REV_ID_MAJOR_AR7242:
case REV_ID_MAJOR_AR913X:
_prom_putchar = prom_putchar_ar71xx;
break;
case REV_ID_MAJOR_AR9330:
case REV_ID_MAJOR_AR9331:
_prom_putchar = prom_putchar_ar933x;
break;
default:
_prom_putchar = prom_putchar_dummy;
break;
}
}
void prom_putchar(unsigned char ch)
{
if (!_prom_putchar)
prom_putchar_init();
_prom_putchar(ch);
}

2
arch/mips/ath79/gpio.c
View File

@ -153,6 +153,8 @@ void __init ath79_gpio_init(void)
ath79_gpio_count = AR724X_GPIO_COUNT;
else if (soc_is_ar913x())
ath79_gpio_count = AR913X_GPIO_COUNT;
else if (soc_is_ar933x())
ath79_gpio_count = AR933X_GPIO_COUNT;
else
BUG();

17
arch/mips/ath79/irq.c
View File

@ -46,6 +46,15 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
else if (pending & MISC_INT_TIMER)
generic_handle_irq(ATH79_MISC_IRQ_TIMER);
else if (pending & MISC_INT_TIMER2)
generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
else if (pending & MISC_INT_TIMER3)
generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
else if (pending & MISC_INT_TIMER4)
generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
else if (pending & MISC_INT_OHCI)
generic_handle_irq(ATH79_MISC_IRQ_OHCI);
@ -58,6 +67,9 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
else if (pending & MISC_INT_WDOG)
generic_handle_irq(ATH79_MISC_IRQ_WDOG);
else if (pending & MISC_INT_ETHSW)
generic_handle_irq(ATH79_MISC_IRQ_ETHSW);
else
spurious_interrupt();
}
@ -117,7 +129,7 @@ static void __init ath79_misc_irq_init(void)
if (soc_is_ar71xx() || soc_is_ar913x())
ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
else if (soc_is_ar724x())
else if (soc_is_ar724x() || soc_is_ar933x())
ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
else
BUG();
@ -174,6 +186,9 @@ void __init arch_init_irq(void)
} else if (soc_is_ar913x()) {
ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
} else if (soc_is_ar933x()) {
ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB;
} else
BUG();

92
arch/mips/ath79/mach-ap121.c Normal file
View File

@ -0,0 +1,92 @@
/*
* Atheros AP121 board support
*
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "machtypes.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-spi.h"
#include "dev-usb.h"
#include "dev-wmac.h"
#define AP121_GPIO_LED_WLAN 0
#define AP121_GPIO_LED_USB 1
#define AP121_GPIO_BTN_JUMPSTART 11
#define AP121_GPIO_BTN_RESET 12
#define AP121_KEYS_POLL_INTERVAL 20 /* msecs */
#define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL)
#define AP121_CAL_DATA_ADDR 0x1fff1000
static struct gpio_led ap121_leds_gpio[] __initdata = {
{
.name = "ap121:green:usb",
.gpio = AP121_GPIO_LED_USB,
.active_low = 0,
},
{
.name = "ap121:green:wlan",
.gpio = AP121_GPIO_LED_WLAN,
.active_low = 0,
},
};
static struct gpio_keys_button ap121_gpio_keys[] __initdata = {
{
.desc = "jumpstart button",
.type = EV_KEY,
.code = KEY_WPS_BUTTON,
.debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
.gpio = AP121_GPIO_BTN_JUMPSTART,
.active_low = 1,
},
{
.desc = "reset button",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
.gpio = AP121_GPIO_BTN_RESET,
.active_low = 1,
}
};
static struct spi_board_info ap121_spi_info[] = {
{
.bus_num = 0,
.chip_select = 0,
.max_speed_hz = 25000000,
.modalias = "mx25l1606e",
}
};
static struct ath79_spi_platform_data ap121_spi_data = {
.bus_num = 0,
.num_chipselect = 1,
};
static void __init ap121_setup(void)
{
u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
ap121_leds_gpio);
ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ap121_gpio_keys),
ap121_gpio_keys);
ath79_register_spi(&ap121_spi_data, ap121_spi_info,
ARRAY_SIZE(ap121_spi_info));
ath79_register_usb();
ath79_register_wmac(cal_data);
}
MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
ap121_setup);

6
arch/mips/ath79/mach-ap81.c
View File

@ -10,10 +10,11 @@
*/
#include "machtypes.h"
#include "dev-ar913x-wmac.h"
#include "dev-wmac.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-spi.h"
#include "dev-usb.h"
#define AP81_GPIO_LED_STATUS 1
#define AP81_GPIO_LED_AOSS 3
@ -91,7 +92,8 @@ static void __init ap81_setup(void)
ap81_gpio_keys);
ath79_register_spi(&ap81_spi_data, ap81_spi_info,
ARRAY_SIZE(ap81_spi_info));
ath79_register_ar913x_wmac(cal_data);
ath79_register_wmac(cal_data);
ath79_register_usb();
}
MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",

2
arch/mips/ath79/mach-pb44.c
View File

@ -18,6 +18,7 @@
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-spi.h"
#include "dev-usb.h"
#define PB44_GPIO_I2C_SCL 0
#define PB44_GPIO_I2C_SDA 1
@ -112,6 +113,7 @@ static void __init pb44_init(void)
pb44_gpio_keys);
ath79_register_spi(&pb44_spi_data, pb44_spi_info,
ARRAY_SIZE(pb44_spi_info));
ath79_register_usb();
}
MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",

119
arch/mips/ath79/mach-ubnt-xm.c Normal file
View File

@ -0,0 +1,119 @@
/*
* Ubiquiti Networks XM (rev 1.0) board support
*
* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
*
* Derived from: mach-pb44.c
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/pci.h>
#ifdef CONFIG_PCI
#include <linux/ath9k_platform.h>
#include <asm/mach-ath79/pci-ath724x.h>
#endif /* CONFIG_PCI */
#include "machtypes.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-spi.h"
#define UBNT_XM_GPIO_LED_L1 0
#define UBNT_XM_GPIO_LED_L2 1
#define UBNT_XM_GPIO_LED_L3 11
#define UBNT_XM_GPIO_LED_L4 7
#define UBNT_XM_GPIO_BTN_RESET 12
#define UBNT_XM_KEYS_POLL_INTERVAL 20
#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
#define UBNT_XM_PCI_IRQ 48
#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
{
.name = "ubnt-xm:red:link1",
.gpio = UBNT_XM_GPIO_LED_L1,
.active_low = 0,
}, {
.name = "ubnt-xm:orange:link2",
.gpio = UBNT_XM_GPIO_LED_L2,
.active_low = 0,
}, {
.name = "ubnt-xm:green:link3",
.gpio = UBNT_XM_GPIO_LED_L3,
.active_low = 0,
}, {
.name = "ubnt-xm:green:link4",
.gpio = UBNT_XM_GPIO_LED_L4,
.active_low = 0,
},
};
static struct gpio_keys_button ubnt_xm_gpio_keys[] __initdata = {
{
.desc = "reset",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL,
.gpio = UBNT_XM_GPIO_BTN_RESET,
.active_low = 1,
}
};
static struct spi_board_info ubnt_xm_spi_info[] = {
{
.bus_num = 0,
.chip_select = 0,
.max_speed_hz = 25000000,
.modalias = "mx25l6405d",
}
};
static struct ath79_spi_platform_data ubnt_xm_spi_data = {
.bus_num = 0,
.num_chipselect = 1,
};
#ifdef CONFIG_PCI
static struct ath9k_platform_data ubnt_xm_eeprom_data;
static struct ath724x_pci_data ubnt_xm_pci_data[] = {
{
.irq = UBNT_XM_PCI_IRQ,
.pdata = &ubnt_xm_eeprom_data,
},
};
#endif /* CONFIG_PCI */
static void __init ubnt_xm_init(void)
{
ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
ubnt_xm_leds_gpio);
ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ubnt_xm_gpio_keys),
ubnt_xm_gpio_keys);
ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
ARRAY_SIZE(ubnt_xm_spi_info));
#ifdef CONFIG_PCI
memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
sizeof(ubnt_xm_eeprom_data.eeprom_data));
ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
#endif /* CONFIG_PCI */
}
MIPS_MACHINE(ATH79_MACH_UBNT_XM,
"UBNT-XM",
"Ubiquiti Networks XM (rev 1.0) board",
ubnt_xm_init);

2
arch/mips/ath79/machtypes.h
View File

@ -16,8 +16,10 @@
enum ath79_mach_type {
ATH79_MACH_GENERIC = 0,
ATH79_MACH_AP121, /* Atheros AP121 reference board */
ATH79_MACH_AP81, /* Atheros AP81 reference board */
ATH79_MACH_PB44, /* Atheros PB44 reference board */
ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
};
#endif /* _ATH79_MACHTYPE_H */

20
arch/mips/ath79/setup.c
View File

@ -101,19 +101,31 @@ static void __init ath79_detect_sys_type(void)
case REV_ID_MAJOR_AR7240:
ath79_soc = ATH79_SOC_AR7240;
chip = "7240";
rev = (id & AR724X_REV_ID_REVISION_MASK);
rev = id & AR724X_REV_ID_REVISION_MASK;
break;
case REV_ID_MAJOR_AR7241:
ath79_soc = ATH79_SOC_AR7241;
chip = "7241";
rev = (id & AR724X_REV_ID_REVISION_MASK);
rev = id & AR724X_REV_ID_REVISION_MASK;
break;
case REV_ID_MAJOR_AR7242:
ath79_soc = ATH79_SOC_AR7242;
chip = "7242";
rev = (id & AR724X_REV_ID_REVISION_MASK);
rev = id & AR724X_REV_ID_REVISION_MASK;
break;
case REV_ID_MAJOR_AR9330:
ath79_soc = ATH79_SOC_AR9330;
chip = "9330";
rev = id & AR933X_REV_ID_REVISION_MASK;
break;
case REV_ID_MAJOR_AR9331:
ath79_soc = ATH79_SOC_AR9331;
chip = "9331";
rev = id & AR933X_REV_ID_REVISION_MASK;
break;
case REV_ID_MAJOR_AR913X:
@ -137,6 +149,8 @@ static void __init ath79_detect_sys_type(void)
panic("ath79: unknown SoC, id:0x%08x", id);
}
ath79_soc_rev = rev;
sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
pr_info("SoC: %s\n", ath79_sys_type);
}

4
arch/mips/bcm63xx/Kconfig
View File

@ -20,6 +20,10 @@ config BCM63XX_CPU_6348
config BCM63XX_CPU_6358
bool "support 6358 CPU"
select HW_HAS_PCI
config BCM63XX_CPU_6368
bool "support 6368 CPU"
select HW_HAS_PCI
endmenu
source "arch/mips/bcm63xx/boards/Kconfig"

46
arch/mips/bcm63xx/boards/board_bcm963xx.c
View File

@ -709,15 +709,9 @@ void __init board_prom_init(void)
char cfe_version[32];
u32 val;
/* read base address of boot chip select (0)
* 6345 does not have MPI but boots from standard
* MIPS Flash address */
if (BCMCPU_IS_6345())
val = 0x1fc00000;
else {
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
val &= MPI_CSBASE_BASE_MASK;
}
/* read base address of boot chip select (0) */
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
val &= MPI_CSBASE_BASE_MASK;
boot_addr = (u8 *)KSEG1ADDR(val);
/* dump cfe version */
@ -797,18 +791,6 @@ void __init board_prom_init(void)
}
bcm_gpio_writel(val, GPIO_MODE_REG);
/* Generate MAC address for WLAN and
* register our SPROM */
#ifdef CONFIG_SSB_PCIHOST
if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
if (ssb_arch_register_fallback_sprom(
&bcm63xx_get_fallback_sprom) < 0)
printk(KERN_ERR PFX "failed to register fallback SPROM\n");
}
#endif
}
/*
@ -892,13 +874,23 @@ int __init board_register_devices(void)
if (board.has_dsp)
bcm63xx_dsp_register(&board.dsp);
/* read base address of boot chip select (0) */
if (BCMCPU_IS_6345())
val = 0x1fc00000;
else {
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
val &= MPI_CSBASE_BASE_MASK;
/* Generate MAC address for WLAN and register our SPROM,
* do this after registering enet devices
*/
#ifdef CONFIG_SSB_PCIHOST
if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
if (ssb_arch_register_fallback_sprom(
&bcm63xx_get_fallback_sprom) < 0)
pr_err(PFX "failed to register fallback SPROM\n");
}
#endif
/* read base address of boot chip select (0) */
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
val &= MPI_CSBASE_BASE_MASK;
mtd_resources[0].start = val;
mtd_resources[0].end = 0x1FFFFFFF;

70
arch/mips/bcm63xx/clk.c
View File

@ -10,6 +10,7 @@
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
@ -112,6 +113,34 @@ static struct clk clk_ephy = {
.set = ephy_set,
};
/*
* Ethernet switch clock
*/
static void enetsw_set(struct clk *clk, int enable)
{
if (!BCMCPU_IS_6368())
return;
bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
CKCTL_6368_SWPKT_USB_EN |
CKCTL_6368_SWPKT_SAR_EN, enable);
if (enable) {
u32 val;
/* reset switch core afer clock change */
val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
val &= ~SOFTRESET_6368_ENETSW_MASK;
bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
msleep(10);
val |= SOFTRESET_6368_ENETSW_MASK;
bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
msleep(10);
}
}
static struct clk clk_enetsw = {
.set = enetsw_set,
};
/*
* PCM clock
*/
@ -131,9 +160,10 @@ static struct clk clk_pcm = {
*/
static void usbh_set(struct clk *clk, int enable)
{
if (!BCMCPU_IS_6348())
return;
bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
if (BCMCPU_IS_6348())
bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
else if (BCMCPU_IS_6368())
bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
}
static struct clk clk_usbh = {
@ -161,6 +191,36 @@ static struct clk clk_spi = {
.set = spi_set,
};
/*
* XTM clock
*/
static void xtm_set(struct clk *clk, int enable)
{
if (!BCMCPU_IS_6368())
return;
bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
CKCTL_6368_SWPKT_SAR_EN, enable);
if (enable) {
u32 val;
/* reset sar core afer clock change */
val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
val &= ~SOFTRESET_6368_SAR_MASK;
bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
mdelay(1);
val |= SOFTRESET_6368_SAR_MASK;
bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
mdelay(1);
}
}
static struct clk clk_xtm = {
.set = xtm_set,
};
/*
* Internal peripheral clock
*/
@ -204,12 +264,16 @@ struct clk *clk_get(struct device *dev, const char *id)
return &clk_enet0;
if (!strcmp(id, "enet1"))
return &clk_enet1;
if (!strcmp(id, "enetsw"))
return &clk_enetsw;
if (!strcmp(id, "ephy"))
return &clk_ephy;
if (!strcmp(id, "usbh"))
return &clk_usbh;
if (!strcmp(id, "spi"))
return &clk_spi;
if (!strcmp(id, "xtm"))
return &clk_xtm;
if (!strcmp(id, "periph"))
return &clk_periph;
if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))

261
arch/mips/bcm63xx/cpu.c
View File

@ -29,166 +29,47 @@ static u16 bcm63xx_cpu_rev;
static unsigned int bcm63xx_cpu_freq;
static unsigned int bcm63xx_memory_size;
/*
* 6338 register sets and irqs
*/
static const unsigned long bcm96338_regs_base[] = {
[RSET_DSL_LMEM] = BCM_6338_DSL_LMEM_BASE,
[RSET_PERF] = BCM_6338_PERF_BASE,
[RSET_TIMER] = BCM_6338_TIMER_BASE,
[RSET_WDT] = BCM_6338_WDT_BASE,
[RSET_UART0] = BCM_6338_UART0_BASE,
[RSET_UART1] = BCM_6338_UART1_BASE,
[RSET_GPIO] = BCM_6338_GPIO_BASE,
[RSET_SPI] = BCM_6338_SPI_BASE,
[RSET_OHCI0] = BCM_6338_OHCI0_BASE,
[RSET_OHCI_PRIV] = BCM_6338_OHCI_PRIV_BASE,
[RSET_USBH_PRIV] = BCM_6338_USBH_PRIV_BASE,
[RSET_UDC0] = BCM_6338_UDC0_BASE,
[RSET_MPI] = BCM_6338_MPI_BASE,
[RSET_PCMCIA] = BCM_6338_PCMCIA_BASE,
[RSET_SDRAM] = BCM_6338_SDRAM_BASE,
[RSET_DSL] = BCM_6338_DSL_BASE,
[RSET_ENET0] = BCM_6338_ENET0_BASE,
[RSET_ENET1] = BCM_6338_ENET1_BASE,
[RSET_ENETDMA] = BCM_6338_ENETDMA_BASE,
[RSET_MEMC] = BCM_6338_MEMC_BASE,
[RSET_DDR] = BCM_6338_DDR_BASE,
static const unsigned long bcm6338_regs_base[] = {
__GEN_CPU_REGS_TABLE(6338)
};
static const int bcm96338_irqs[] = {
[IRQ_TIMER] = BCM_6338_TIMER_IRQ,
[IRQ_UART0] = BCM_6338_UART0_IRQ,
[IRQ_DSL] = BCM_6338_DSL_IRQ,
[IRQ_ENET0] = BCM_6338_ENET0_IRQ,
[IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ,
[IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ,
[IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ,
static const int bcm6338_irqs[] = {
__GEN_CPU_IRQ_TABLE(6338)
};
/*
* 6345 register sets and irqs
*/
static const unsigned long bcm96345_regs_base[] = {
[RSET_DSL_LMEM] = BCM_6345_DSL_LMEM_BASE,
[RSET_PERF] = BCM_6345_PERF_BASE,
[RSET_TIMER] = BCM_6345_TIMER_BASE,
[RSET_WDT] = BCM_6345_WDT_BASE,
[RSET_UART0] = BCM_6345_UART0_BASE,
[RSET_UART1] = BCM_6345_UART1_BASE,
[RSET_GPIO] = BCM_6345_GPIO_BASE,
[RSET_SPI] = BCM_6345_SPI_BASE,
[RSET_UDC0] = BCM_6345_UDC0_BASE,
[RSET_OHCI0] = BCM_6345_OHCI0_BASE,
[RSET_OHCI_PRIV] = BCM_6345_OHCI_PRIV_BASE,
[RSET_USBH_PRIV] = BCM_6345_USBH_PRIV_BASE,
[RSET_MPI] = BCM_6345_MPI_BASE,
[RSET_PCMCIA] = BCM_6345_PCMCIA_BASE,
[RSET_DSL] = BCM_6345_DSL_BASE,
[RSET_ENET0] = BCM_6345_ENET0_BASE,
[RSET_ENET1] = BCM_6345_ENET1_BASE,
[RSET_ENETDMA] = BCM_6345_ENETDMA_BASE,
[RSET_EHCI0] = BCM_6345_EHCI0_BASE,
[RSET_SDRAM] = BCM_6345_SDRAM_BASE,
[RSET_MEMC] = BCM_6345_MEMC_BASE,
[RSET_DDR] = BCM_6345_DDR_BASE,
static const unsigned long bcm6345_regs_base[] = {
__GEN_CPU_REGS_TABLE(6345)
};
static const int bcm96345_irqs[] = {
[IRQ_TIMER] = BCM_6345_TIMER_IRQ,
[IRQ_UART0] = BCM_6345_UART0_IRQ,
[IRQ_DSL] = BCM_6345_DSL_IRQ,
[IRQ_ENET0] = BCM_6345_ENET0_IRQ,
[IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ,
[IRQ_ENET0_RXDMA] = BCM_6345_ENET0_RXDMA_IRQ,
[IRQ_ENET0_TXDMA] = BCM_6345_ENET0_TXDMA_IRQ,
static const int bcm6345_irqs[] = {
__GEN_CPU_IRQ_TABLE(6345)
};
/*
* 6348 register sets and irqs
*/
static const unsigned long bcm96348_regs_base[] = {
[RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE,
[RSET_PERF] = BCM_6348_PERF_BASE,
[RSET_TIMER] = BCM_6348_TIMER_BASE,
[RSET_WDT] = BCM_6348_WDT_BASE,
[RSET_UART0] = BCM_6348_UART0_BASE,
[RSET_UART1] = BCM_6348_UART1_BASE,
[RSET_GPIO] = BCM_6348_GPIO_BASE,
[RSET_SPI] = BCM_6348_SPI_BASE,
[RSET_OHCI0] = BCM_6348_OHCI0_BASE,
[RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE,
[RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE,
[RSET_MPI] = BCM_6348_MPI_BASE,
[RSET_PCMCIA] = BCM_6348_PCMCIA_BASE,
[RSET_SDRAM] = BCM_6348_SDRAM_BASE,
[RSET_DSL] = BCM_6348_DSL_BASE,
[RSET_ENET0] = BCM_6348_ENET0_BASE,
[RSET_ENET1] = BCM_6348_ENET1_BASE,
[RSET_ENETDMA] = BCM_6348_ENETDMA_BASE,
[RSET_MEMC] = BCM_6348_MEMC_BASE,
[RSET_DDR] = BCM_6348_DDR_BASE,
static const unsigned long bcm6348_regs_base[] = {
__GEN_CPU_REGS_TABLE(6348)
};
static const int bcm96348_irqs[] = {
[IRQ_TIMER] = BCM_6348_TIMER_IRQ,
[IRQ_UART0] = BCM_6348_UART0_IRQ,
[IRQ_DSL] = BCM_6348_DSL_IRQ,
[IRQ_ENET0] = BCM_6348_ENET0_IRQ,
[IRQ_ENET1] = BCM_6348_ENET1_IRQ,
[IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ,
[IRQ_OHCI0] = BCM_6348_OHCI0_IRQ,
[IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ,
[IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ,
[IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ,
[IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ,
[IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ,
[IRQ_PCI] = BCM_6348_PCI_IRQ,
static const int bcm6348_irqs[] = {
__GEN_CPU_IRQ_TABLE(6348)
};
/*
* 6358 register sets and irqs
*/
static const unsigned long bcm96358_regs_base[] = {
[RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE,
[RSET_PERF] = BCM_6358_PERF_BASE,
[RSET_TIMER] = BCM_6358_TIMER_BASE,
[RSET_WDT] = BCM_6358_WDT_BASE,
[RSET_UART0] = BCM_6358_UART0_BASE,
[RSET_UART1] = BCM_6358_UART1_BASE,
[RSET_GPIO] = BCM_6358_GPIO_BASE,
[RSET_SPI] = BCM_6358_SPI_BASE,
[RSET_OHCI0] = BCM_6358_OHCI0_BASE,
[RSET_EHCI0] = BCM_6358_EHCI0_BASE,
[RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE,
[RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE,
[RSET_MPI] = BCM_6358_MPI_BASE,
[RSET_PCMCIA] = BCM_6358_PCMCIA_BASE,
[RSET_SDRAM] = BCM_6358_SDRAM_BASE,
[RSET_DSL] = BCM_6358_DSL_BASE,
[RSET_ENET0] = BCM_6358_ENET0_BASE,
[RSET_ENET1] = BCM_6358_ENET1_BASE,
[RSET_ENETDMA] = BCM_6358_ENETDMA_BASE,
[RSET_MEMC] = BCM_6358_MEMC_BASE,
[RSET_DDR] = BCM_6358_DDR_BASE,
static const unsigned long bcm6358_regs_base[] = {
__GEN_CPU_REGS_TABLE(6358)
};
static const int bcm96358_irqs[] = {
[IRQ_TIMER] = BCM_6358_TIMER_IRQ,
[IRQ_UART0] = BCM_6358_UART0_IRQ,
[IRQ_UART1] = BCM_6358_UART1_IRQ,
[IRQ_DSL] = BCM_6358_DSL_IRQ,
[IRQ_ENET0] = BCM_6358_ENET0_IRQ,
[IRQ_ENET1] = BCM_6358_ENET1_IRQ,
[IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ,
[IRQ_OHCI0] = BCM_6358_OHCI0_IRQ,
[IRQ_EHCI0] = BCM_6358_EHCI0_IRQ,
[IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ,
[IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ,
[IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ,
[IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ,
[IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ,
[IRQ_PCI] = BCM_6358_PCI_IRQ,
static const int bcm6358_irqs[] = {
__GEN_CPU_IRQ_TABLE(6358)
};
static const unsigned long bcm6368_regs_base[] = {
__GEN_CPU_REGS_TABLE(6368)
};
static const int bcm6368_irqs[] = {
__GEN_CPU_IRQ_TABLE(6368)
};
u16 __bcm63xx_get_cpu_id(void)
@ -217,20 +98,19 @@ unsigned int bcm63xx_get_memory_size(void)
static unsigned int detect_cpu_clock(void)
{
unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
/* BCM6338 has a fixed 240 Mhz frequency */
if (BCMCPU_IS_6338())
switch (bcm63xx_get_cpu_id()) {
case BCM6338_CPU_ID:
/* BCM6338 has a fixed 240 Mhz frequency */
return 240000000;
/* BCM6345 has a fixed 140Mhz frequency */
if (BCMCPU_IS_6345())
case BCM6345_CPU_ID:
/* BCM6345 has a fixed 140Mhz frequency */
return 140000000;
/*
* frequency depends on PLL configuration:
*/
if (BCMCPU_IS_6348()) {
case BCM6348_CPU_ID:
{
unsigned int tmp, n1, n2, m1;
/* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
@ -239,17 +119,47 @@ static unsigned int detect_cpu_clock(void)
n1 += 1;
n2 += 2;
m1 += 1;
return (16 * 1000000 * n1 * n2) / m1;
}
if (BCMCPU_IS_6358()) {
case BCM6358_CPU_ID:
{
unsigned int tmp, n1, n2, m1;
/* 16MHz * N1 * N2 / M1_CPU */
tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
return (16 * 1000000 * n1 * n2) / m1;
}
return (16 * 1000000 * n1 * n2) / m1;
case BCM6368_CPU_ID:
{
unsigned int tmp, p1, p2, ndiv, m1;
/* (64MHz / P1) * P2 * NDIV / M1_CPU */
tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
DMIPSPLLCFG_6368_P1_SHIFT;
p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
DMIPSPLLCFG_6368_P2_SHIFT;
ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
DMIPSPLLCFG_6368_NDIV_SHIFT;
tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
DMIPSPLLDIV_6368_MDIV_SHIFT;
return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
}
default:
BUG();
}
}
/*
@ -260,8 +170,10 @@ static unsigned int detect_memory_size(void)
unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
u32 val;
if (BCMCPU_IS_6345())
return (8 * 1024 * 1024);
if (BCMCPU_IS_6345()) {
val = bcm_sdram_readl(SDRAM_MBASE_REG);
return (val * 8 * 1024 * 1024);
}
if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
val = bcm_sdram_readl(SDRAM_CFG_REG);
@ -271,7 +183,7 @@ static unsigned int detect_memory_size(void)
banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
}
if (BCMCPU_IS_6358()) {
if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
val = bcm_memc_readl(MEMC_CFG_REG);
rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
@ -301,24 +213,33 @@ void __init bcm63xx_cpu_init(void)
case CPU_BMIPS3300:
if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
expected_cpu_id = BCM6348_CPU_ID;
bcm63xx_regs_base = bcm96348_regs_base;
bcm63xx_irqs = bcm96348_irqs;
bcm63xx_regs_base = bcm6348_regs_base;
bcm63xx_irqs = bcm6348_irqs;
} else {
__cpu_name[cpu] = "Broadcom BCM6338";
expected_cpu_id = BCM6338_CPU_ID;
bcm63xx_regs_base = bcm96338_regs_base;
bcm63xx_irqs = bcm96338_irqs;
bcm63xx_regs_base = bcm6338_regs_base;
bcm63xx_irqs = bcm6338_irqs;
}
break;
case CPU_BMIPS32:
expected_cpu_id = BCM6345_CPU_ID;
bcm63xx_regs_base = bcm96345_regs_base;
bcm63xx_irqs = bcm96345_irqs;
bcm63xx_regs_base = bcm6345_regs_base;
bcm63xx_irqs = bcm6345_irqs;
break;
case CPU_BMIPS4350:
expected_cpu_id = BCM6358_CPU_ID;
bcm63xx_regs_base = bcm96358_regs_base;
bcm63xx_irqs = bcm96358_irqs;
switch (read_c0_prid() & 0xf0) {
case 0x10:
expected_cpu_id = BCM6358_CPU_ID;
bcm63xx_regs_base = bcm6358_regs_base;
bcm63xx_irqs = bcm6358_irqs;
break;
case 0x30:
expected_cpu_id = BCM6368_CPU_ID;
bcm63xx_regs_base = bcm6368_regs_base;
bcm63xx_irqs = bcm6368_irqs;
break;
}
break;
}

2
arch/mips/bcm63xx/dev-uart.c
View File

@ -54,7 +54,7 @@ int __init bcm63xx_uart_register(unsigned int id)
if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
return -ENODEV;
if (id == 1 && !BCMCPU_IS_6358())
if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
return -ENODEV;
if (id == 0) {

41
arch/mips/bcm63xx/gpio.c
View File

@ -4,7 +4,7 @@
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
* Copyright (C) 2008-2011 Florian Fainelli <florian@openwrt.org>
*/
#include <linux/kernel.h>
@ -18,6 +18,34 @@
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
#ifndef BCMCPU_RUNTIME_DETECT
#define gpio_out_low_reg GPIO_DATA_LO_REG
#ifdef CONFIG_BCM63XX_CPU_6345
#ifdef gpio_out_low_reg
#undef gpio_out_low_reg
#define gpio_out_low_reg GPIO_DATA_LO_REG_6345
#endif /* gpio_out_low_reg */
#endif /* CONFIG_BCM63XX_CPU_6345 */
static inline void bcm63xx_gpio_out_low_reg_init(void)
{
}
#else /* ! BCMCPU_RUNTIME_DETECT */
static u32 gpio_out_low_reg;
static void bcm63xx_gpio_out_low_reg_init(void)
{
switch (bcm63xx_get_cpu_id()) {
case BCM6345_CPU_ID:
gpio_out_low_reg = GPIO_DATA_LO_REG_6345;
break;
default:
gpio_out_low_reg = GPIO_DATA_LO_REG;
break;
}
}
#endif /* ! BCMCPU_RUNTIME_DETECT */
static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
static u32 gpio_out_low, gpio_out_high;
@ -33,7 +61,7 @@ static void bcm63xx_gpio_set(struct gpio_chip *chip,
BUG();
if (gpio < 32) {
reg = GPIO_DATA_LO_REG;
reg = gpio_out_low_reg;
mask = 1 << gpio;
v = &gpio_out_low;
} else {
@ -60,7 +88,7 @@ static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio)
BUG();
if (gpio < 32) {
reg = GPIO_DATA_LO_REG;
reg = gpio_out_low_reg;
mask = 1 << gpio;
} else {
reg = GPIO_DATA_HI_REG;
@ -125,8 +153,11 @@ static struct gpio_chip bcm63xx_gpio_chip = {
int __init bcm63xx_gpio_init(void)
{
gpio_out_low = bcm_gpio_readl(GPIO_DATA_LO_REG);
gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG);
bcm63xx_gpio_out_low_reg_init();
gpio_out_low = bcm_gpio_readl(gpio_out_low_reg);
if (!BCMCPU_IS_6345())
gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG);
bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count();
pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio);

407
arch/mips/bcm63xx/irq.c
View File

@ -19,19 +19,187 @@
#include <bcm63xx_io.h>
#include <bcm63xx_irq.h>
static void __dispatch_internal(void) __maybe_unused;
static void __dispatch_internal_64(void) __maybe_unused;
static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
#ifndef BCMCPU_RUNTIME_DETECT
#ifdef CONFIG_BCM63XX_CPU_6338
#define irq_stat_reg PERF_IRQSTAT_6338_REG
#define irq_mask_reg PERF_IRQMASK_6338_REG
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
#define ext_irq_end 0
#define ext_irq_count 4
#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6338
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6345
#define irq_stat_reg PERF_IRQSTAT_6345_REG
#define irq_mask_reg PERF_IRQMASK_6345_REG
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
#define ext_irq_end 0
#define ext_irq_count 0
#define ext_irq_cfg_reg1 0
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6348
#define irq_stat_reg PERF_IRQSTAT_6348_REG
#define irq_mask_reg PERF_IRQMASK_6348_REG
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
#define ext_irq_end 0
#define ext_irq_count 4
#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6348
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6358
#define irq_stat_reg PERF_IRQSTAT_6358_REG
#define irq_mask_reg PERF_IRQMASK_6358_REG
#define irq_bits 32
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
#define ext_irq_end (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
#define ext_irq_count 4
#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6368
#define irq_stat_reg PERF_IRQSTAT_6368_REG
#define irq_mask_reg PERF_IRQMASK_6368_REG
#define irq_bits 64
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
#define ext_irq_end (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
#define ext_irq_count 6
#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6368
#define ext_irq_cfg_reg2 PERF_EXTIRQ_CFG_REG2_6368
#endif
#if irq_bits == 32
#define dispatch_internal __dispatch_internal
#define internal_irq_mask __internal_irq_mask_32
#define internal_irq_unmask __internal_irq_unmask_32
#else
#define dispatch_internal __dispatch_internal_64
#define internal_irq_mask __internal_irq_mask_64
#define internal_irq_unmask __internal_irq_unmask_64
#endif
#define irq_stat_addr (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
#define irq_mask_addr (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
static inline void bcm63xx_init_irq(void)
{
}
#else /* ! BCMCPU_RUNTIME_DETECT */
static u32 irq_stat_addr, irq_mask_addr;
static void (*dispatch_internal)(void);
static int is_ext_irq_cascaded;
static unsigned int ext_irq_count;
static unsigned int ext_irq_start, ext_irq_end;
static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
static void (*internal_irq_mask)(unsigned int irq);
static void (*internal_irq_unmask)(unsigned int irq);
static void bcm63xx_init_irq(void)
{
int irq_bits;
irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
switch (bcm63xx_get_cpu_id()) {
case BCM6338_CPU_ID:
irq_stat_addr += PERF_IRQSTAT_6338_REG;
irq_mask_addr += PERF_IRQMASK_6338_REG;
irq_bits = 32;
break;
case BCM6345_CPU_ID:
irq_stat_addr += PERF_IRQSTAT_6345_REG;
irq_mask_addr += PERF_IRQMASK_6345_REG;
irq_bits = 32;
break;
case BCM6348_CPU_ID:
irq_stat_addr += PERF_IRQSTAT_6348_REG;
irq_mask_addr += PERF_IRQMASK_6348_REG;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
break;
case BCM6358_CPU_ID:
irq_stat_addr += PERF_IRQSTAT_6358_REG;
irq_mask_addr += PERF_IRQMASK_6358_REG;
irq_bits = 32;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
break;
case BCM6368_CPU_ID:
irq_stat_addr += PERF_IRQSTAT_6368_REG;
irq_mask_addr += PERF_IRQMASK_6368_REG;
irq_bits = 64;
ext_irq_count = 6;
is_ext_irq_cascaded = 1;
ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
break;
default:
BUG();
}
if (irq_bits == 32) {
dispatch_internal = __dispatch_internal;
internal_irq_mask = __internal_irq_mask_32;
internal_irq_unmask = __internal_irq_unmask_32;
} else {
dispatch_internal = __dispatch_internal_64;
internal_irq_mask = __internal_irq_mask_64;
internal_irq_unmask = __internal_irq_unmask_64;
}
}
#endif /* ! BCMCPU_RUNTIME_DETECT */
static inline u32 get_ext_irq_perf_reg(int irq)
{
if (irq < 4)
return ext_irq_cfg_reg1;
return ext_irq_cfg_reg2;
}
static inline void handle_internal(int intbit)
{
if (is_ext_irq_cascaded &&
intbit >= ext_irq_start && intbit <= ext_irq_end)
do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
else
do_IRQ(intbit + IRQ_INTERNAL_BASE);
}
/*
* dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
* prioritize any interrupt relatively to another. the static counter
* will resume the loop where it ended the last time we left this
* function.
*/
static void bcm63xx_irq_dispatch_internal(void)
static void __dispatch_internal(void)
{
u32 pending;
static int i;
pending = bcm_perf_readl(PERF_IRQMASK_REG) &
bcm_perf_readl(PERF_IRQSTAT_REG);
pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr);
if (!pending)
return ;
@ -41,7 +209,28 @@ static void bcm63xx_irq_dispatch_internal(void)
i = (i + 1) & 0x1f;
if (pending & (1 << to_call)) {
do_IRQ(to_call + IRQ_INTERNAL_BASE);
handle_internal(to_call);
break;
}
}
}
static void __dispatch_internal_64(void)
{
u64 pending;
static int i;
pending = bcm_readq(irq_stat_addr) & bcm_readq(irq_mask_addr);
if (!pending)
return ;
while (1) {
int to_call = i;
i = (i + 1) & 0x3f;
if (pending & (1ull << to_call)) {
handle_internal(to_call);
break;
}
}
@ -60,15 +249,17 @@ asmlinkage void plat_irq_dispatch(void)
if (cause & CAUSEF_IP7)
do_IRQ(7);
if (cause & CAUSEF_IP2)
bcm63xx_irq_dispatch_internal();
if (cause & CAUSEF_IP3)
do_IRQ(IRQ_EXT_0);
if (cause & CAUSEF_IP4)
do_IRQ(IRQ_EXT_1);
if (cause & CAUSEF_IP5)
do_IRQ(IRQ_EXT_2);
if (cause & CAUSEF_IP6)
do_IRQ(IRQ_EXT_3);
dispatch_internal();
if (!is_ext_irq_cascaded) {
if (cause & CAUSEF_IP3)
do_IRQ(IRQ_EXT_0);
if (cause & CAUSEF_IP4)
do_IRQ(IRQ_EXT_1);
if (cause & CAUSEF_IP5)
do_IRQ(IRQ_EXT_2);
if (cause & CAUSEF_IP6)
do_IRQ(IRQ_EXT_3);
}
} while (1);
}
@ -76,24 +267,50 @@ asmlinkage void plat_irq_dispatch(void)
* internal IRQs operations: only mask/unmask on PERF irq mask
* register.
*/
static inline void bcm63xx_internal_irq_mask(struct irq_data *d)
static void __internal_irq_mask_32(unsigned int irq)
{
unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
u32 mask;
mask = bcm_perf_readl(PERF_IRQMASK_REG);
mask = bcm_readl(irq_mask_addr);
mask &= ~(1 << irq);
bcm_perf_writel(mask, PERF_IRQMASK_REG);
bcm_writel(mask, irq_mask_addr);
}
static void __internal_irq_mask_64(unsigned int irq)
{
u64 mask;
mask = bcm_readq(irq_mask_addr);
mask &= ~(1ull << irq);
bcm_writeq(mask, irq_mask_addr);
}
static void __internal_irq_unmask_32(unsigned int irq)
{
u32 mask;
mask = bcm_readl(irq_mask_addr);
mask |= (1 << irq);
bcm_writel(mask, irq_mask_addr);
}
static void __internal_irq_unmask_64(unsigned int irq)
{
u64 mask;
mask = bcm_readq(irq_mask_addr);
mask |= (1ull << irq);
bcm_writeq(mask, irq_mask_addr);
}
static void bcm63xx_internal_irq_mask(struct irq_data *d)
{
internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
}
static void bcm63xx_internal_irq_unmask(struct irq_data *d)
{
unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
u32 mask;
mask = bcm_perf_readl(PERF_IRQMASK_REG);
mask |= (1 << irq);
bcm_perf_writel(mask, PERF_IRQMASK_REG);
internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
}
/*
@ -102,94 +319,131 @@ static void bcm63xx_internal_irq_unmask(struct irq_data *d)
*/
static void bcm63xx_external_irq_mask(struct irq_data *d)
{
unsigned int irq = d->irq - IRQ_EXT_BASE;
u32 reg;
unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
u32 reg, regaddr;
reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
reg &= ~EXTIRQ_CFG_MASK(irq);
bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
regaddr = get_ext_irq_perf_reg(irq);
reg = bcm_perf_readl(regaddr);
if (BCMCPU_IS_6348())
reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
else
reg &= ~EXTIRQ_CFG_MASK(irq % 4);
bcm_perf_writel(reg, regaddr);
if (is_ext_irq_cascaded)
internal_irq_mask(irq + ext_irq_start);
}
static void bcm63xx_external_irq_unmask(struct irq_data *d)
{
unsigned int irq = d->irq - IRQ_EXT_BASE;
u32 reg;
unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
u32 reg, regaddr;
reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
reg |= EXTIRQ_CFG_MASK(irq);
bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
regaddr = get_ext_irq_perf_reg(irq);
reg = bcm_perf_readl(regaddr);
if (BCMCPU_IS_6348())
reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
else
reg |= EXTIRQ_CFG_MASK(irq % 4);
bcm_perf_writel(reg, regaddr);
if (is_ext_irq_cascaded)
internal_irq_unmask(irq + ext_irq_start);
}
static void bcm63xx_external_irq_clear(struct irq_data *d)
{
unsigned int irq = d->irq - IRQ_EXT_BASE;
u32 reg;
unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
u32 reg, regaddr;
reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
reg |= EXTIRQ_CFG_CLEAR(irq);
bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
}
regaddr = get_ext_irq_perf_reg(irq);
reg = bcm_perf_readl(regaddr);
static unsigned int bcm63xx_external_irq_startup(struct irq_data *d)
{
set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
irq_enable_hazard();
bcm63xx_external_irq_unmask(d);
return 0;
}
if (BCMCPU_IS_6348())
reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
else
reg |= EXTIRQ_CFG_CLEAR(irq % 4);
static void bcm63xx_external_irq_shutdown(struct irq_data *d)
{
bcm63xx_external_irq_mask(d);
clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
irq_disable_hazard();
bcm_perf_writel(reg, regaddr);
}
static int bcm63xx_external_irq_set_type(struct irq_data *d,
unsigned int flow_type)
{
unsigned int irq = d->irq - IRQ_EXT_BASE;
u32 reg;
unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
u32 reg, regaddr;
int levelsense, sense, bothedge;
flow_type &= IRQ_TYPE_SENSE_MASK;
if (flow_type == IRQ_TYPE_NONE)
flow_type = IRQ_TYPE_LEVEL_LOW;
reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
levelsense = sense = bothedge = 0;
switch (flow_type) {
case IRQ_TYPE_EDGE_BOTH:
reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
reg |= EXTIRQ_CFG_BOTHEDGE(irq);
bothedge = 1;
break;
case IRQ_TYPE_EDGE_RISING:
reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
reg |= EXTIRQ_CFG_SENSE(irq);
reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
sense = 1;
break;
case IRQ_TYPE_EDGE_FALLING:
reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
reg &= ~EXTIRQ_CFG_SENSE(irq);
reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
reg |= EXTIRQ_CFG_LEVELSENSE(irq);
reg |= EXTIRQ_CFG_SENSE(irq);
levelsense = 1;
sense = 1;
break;
case IRQ_TYPE_LEVEL_LOW:
reg |= EXTIRQ_CFG_LEVELSENSE(irq);
reg &= ~EXTIRQ_CFG_SENSE(irq);
levelsense = 1;
break;
default:
printk(KERN_ERR "bogus flow type combination given !\n");
return -EINVAL;
}
bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
regaddr = get_ext_irq_perf_reg(irq);
reg = bcm_perf_readl(regaddr);
irq %= 4;
if (BCMCPU_IS_6348()) {
if (levelsense)
reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
else
reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
if (sense)
reg |= EXTIRQ_CFG_SENSE_6348(irq);
else
reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
if (bothedge)
reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
else
reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
}
if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
if (levelsense)
reg |= EXTIRQ_CFG_LEVELSENSE(irq);
else
reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
if (sense)
reg |= EXTIRQ_CFG_SENSE(irq);
else
reg &= ~EXTIRQ_CFG_SENSE(irq);
if (bothedge)
reg |= EXTIRQ_CFG_BOTHEDGE(irq);
else
reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
}
bcm_perf_writel(reg, regaddr);
irqd_set_trigger_type(d, flow_type);
if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
@ -208,9 +462,6 @@ static struct irq_chip bcm63xx_internal_irq_chip = {
static struct irq_chip bcm63xx_external_irq_chip = {
.name = "bcm63xx_epic",
.irq_startup = bcm63xx_external_irq_startup,
.irq_shutdown = bcm63xx_external_irq_shutdown,
.irq_ack = bcm63xx_external_irq_clear,
.irq_mask = bcm63xx_external_irq_mask,
@ -225,18 +476,30 @@ static struct irqaction cpu_ip2_cascade_action = {
.flags = IRQF_NO_THREAD,
};
static struct irqaction cpu_ext_cascade_action = {
.handler = no_action,
.name = "cascade_extirq",
.flags = IRQF_NO_THREAD,
};
void __init arch_init_irq(void)
{
int i;
bcm63xx_init_irq();
mips_cpu_irq_init();
for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
handle_level_irq);
for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
handle_edge_irq);
setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
if (!is_ext_irq_cascaded) {
for (i = 3; i < 3 + ext_irq_count; ++i)
setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
}
setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
}

7
arch/mips/bcm63xx/prom.c
View File

@ -32,9 +32,12 @@ void __init prom_init(void)
mask = CKCTL_6345_ALL_SAFE_EN;
else if (BCMCPU_IS_6348())
mask = CKCTL_6348_ALL_SAFE_EN;
else
/* BCMCPU_IS_6358() */
else if (BCMCPU_IS_6358())
mask = CKCTL_6358_ALL_SAFE_EN;
else if (BCMCPU_IS_6368())
mask = CKCTL_6368_ALL_SAFE_EN;
else
mask = 0;
reg = bcm_perf_readl(PERF_CKCTL_REG);
reg &= ~mask;

32
arch/mips/bcm63xx/setup.c
View File

@ -63,13 +63,33 @@ static void bcm6348_a1_reboot(void)
void bcm63xx_machine_reboot(void)
{
u32 reg;
u32 reg, perf_regs[2] = { 0, 0 };
unsigned int i;
/* mask and clear all external irq */
reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
reg &= ~EXTIRQ_CFG_MASK_ALL;
reg |= EXTIRQ_CFG_CLEAR_ALL;
bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
switch (bcm63xx_get_cpu_id()) {
case BCM6338_CPU_ID:
perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
break;
case BCM6348_CPU_ID:
perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348;
break;
case BCM6358_CPU_ID:
perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
break;
}
for (i = 0; i < 2; i++) {
reg = bcm_perf_readl(perf_regs[i]);
if (BCMCPU_IS_6348()) {
reg &= ~EXTIRQ_CFG_MASK_ALL_6348;
reg |= EXTIRQ_CFG_CLEAR_ALL_6348;
} else {
reg &= ~EXTIRQ_CFG_MASK_ALL;
reg |= EXTIRQ_CFG_CLEAR_ALL;
}
bcm_perf_writel(reg, perf_regs[i]);
}
if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
bcm6348_a1_reboot();
@ -124,4 +144,4 @@ int __init bcm63xx_register_devices(void)
return board_register_devices();
}
arch_initcall(bcm63xx_register_devices);
device_initcall(bcm63xx_register_devices);

4
arch/mips/cavium-octeon/Kconfig
View File

@ -86,10 +86,6 @@ config ARCH_SPARSEMEM_ENABLE
def_bool y
select SPARSEMEM_STATIC
config CAVIUM_OCTEON_HELPER
def_bool y
depends on OCTEON_ETHERNET || PCI
config IOMMU_HELPER
bool

23
arch/mips/cavium-octeon/dma-octeon.c
View File

@ -61,6 +61,16 @@ static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
return daddr;
}
static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
{
return octeon_hole_phys_to_dma(paddr);
}
static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
{
return octeon_hole_dma_to_phys(daddr);
}
static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
{
if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
@ -262,11 +272,11 @@ void __init plat_swiotlb_setup(void)
for (i = 0 ; i < boot_mem_map.nr_map; i++) {
struct boot_mem_map_entry *e = &boot_mem_map.map[i];
if (e->type != BOOT_MEM_RAM)
if (e->type != BOOT_MEM_RAM && e->type != BOOT_MEM_INIT_RAM)
continue;
/* These addresses map low for PCI. */
if (e->addr > 0x410000000ull)
if (e->addr > 0x410000000ull && !OCTEON_IS_MODEL(OCTEON_CN6XXX))
continue;
addr_size += e->size;
@ -295,6 +305,11 @@ void __init plat_swiotlb_setup(void)
*/
swiotlbsize = 64 * (1<<20);
}
#endif
#ifdef CONFIG_USB_OCTEON_OHCI
/* OCTEON II ohci is only 32-bit. */
if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && max_addr >= 0x100000000ul)
swiotlbsize = 64 * (1<<20);
#endif
swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
@ -330,6 +345,10 @@ struct dma_map_ops *octeon_pci_dma_map_ops;
void __init octeon_pci_dma_init(void)
{
switch (octeon_dma_bar_type) {
case OCTEON_DMA_BAR_TYPE_PCIE2:
_octeon_pci_dma_map_ops.phys_to_dma = octeon_gen2_phys_to_dma;
_octeon_pci_dma_map_ops.dma_to_phys = octeon_gen2_dma_to_phys;
break;
case OCTEON_DMA_BAR_TYPE_PCIE:
_octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma;
_octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys;

7
arch/mips/cavium-octeon/executive/Makefile
View File

@ -10,5 +10,10 @@
#
obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \
cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \
cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \
cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \
cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o
obj-$(CONFIG_CAVIUM_OCTEON_HELPER) += cvmx-helper-errata.o cvmx-helper-jtag.o
obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o

8
drivers/staging/octeon/cvmx-cmd-queue.c → arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
View File

@ -34,13 +34,13 @@
#include <asm/octeon/octeon.h>
#include "cvmx-config.h"
#include "cvmx-fpa.h"
#include "cvmx-cmd-queue.h"
#include <asm/octeon/cvmx-config.h>
#include <asm/octeon/cvmx-fpa.h>
#include <asm/octeon/cvmx-cmd-queue.h>
#include <asm/octeon/cvmx-npei-defs.h>
#include <asm/octeon/cvmx-pexp-defs.h>
#include "cvmx-pko-defs.h"
#include <asm/octeon/cvmx-pko-defs.h>
/**
* This application uses this pointer to access the global queue

0
drivers/staging/octeon/cvmx-fpa.c → arch/mips/cavium-octeon/executive/cvmx-fpa.c
View File

38
drivers/staging/octeon/cvmx-helper-board.c → arch/mips/cavium-octeon/executive/cvmx-helper-board.c
View File

@ -34,16 +34,16 @@
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-bootinfo.h>
#include "cvmx-config.h"
#include <asm/octeon/cvmx-config.h>
#include "cvmx-mdio.h"
#include <asm/octeon/cvmx-mdio.h>
#include "cvmx-helper.h"
#include "cvmx-helper-util.h"
#include "cvmx-helper-board.h"
#include <asm/octeon/cvmx-helper.h>
#include <asm/octeon/cvmx-helper-util.h>
#include <asm/octeon/cvmx-helper-board.h>
#include "cvmx-gmxx-defs.h"
#include "cvmx-asxx-defs.h"
#include <asm/octeon/cvmx-gmxx-defs.h>
#include <asm/octeon/cvmx-asxx-defs.h>
/**
* cvmx_override_board_link_get(int ipd_port) is a function
@ -117,6 +117,10 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
case CVMX_BOARD_TYPE_EBH5200:
case CVMX_BOARD_TYPE_EBH5201:
case CVMX_BOARD_TYPE_EBT5200:
/* Board has 2 management ports */
if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) &&
(ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT;
/*
* Board has 4 SGMII ports. The PHYs start right after the MII
* ports MII0 = 0, MII1 = 1, SGMII = 2-5.
@ -128,6 +132,9 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
case CVMX_BOARD_TYPE_EBH5600:
case CVMX_BOARD_TYPE_EBH5601:
case CVMX_BOARD_TYPE_EBH5610:
/* Board has 1 management port */
if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
return 0;
/*
* Board has 8 SGMII ports. 4 connect out, two connect
* to a switch, and 2 loop to each other
@ -147,6 +154,19 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
return ipd_port - 16 + 1;
else
return -1;
case CVMX_BOARD_TYPE_NIC_XLE_10G:
case CVMX_BOARD_TYPE_NIC10E:
return -1;
case CVMX_BOARD_TYPE_NIC4E:
if (ipd_port >= 0 && ipd_port <= 3)
return (ipd_port + 0x1f) & 0x1f;
else
return -1;
case CVMX_BOARD_TYPE_NIC2E:
if (ipd_port >= 0 && ipd_port <= 1)
return ipd_port + 1;
else
return -1;
case CVMX_BOARD_TYPE_BBGW_REF:
/*
* No PHYs are connected to Octeon, everything is
@ -493,7 +513,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr,
cvmx_mdio_phy_reg_control_t reg_control;
cvmx_mdio_phy_reg_status_t reg_status;
cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
reg_status.u16 =
@ -508,9 +527,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr,
reg_autoneg_adver.s.advert_100base_tx_full = 0;
reg_autoneg_adver.s.advert_100base_tx_half = 0;
if (reg_status.s.capable_extended_status) {
reg_extended_status.u16 =
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
reg_control_1000.u16 =
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
CVMX_MDIO_PHY_REG_CONTROL_1000);

0
drivers/staging/octeon/cvmx-helper-fpa.c → arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c
View File

6
drivers/staging/octeon/cvmx-helper-loop.c → arch/mips/cavium-octeon/executive/cvmx-helper-loop.c
View File

@ -31,10 +31,10 @@
*/
#include <asm/octeon/octeon.h>
#include "cvmx-config.h"
#include <asm/octeon/cvmx-config.h>
#include "cvmx-helper.h"
#include "cvmx-pip-defs.h"
#include <asm/octeon/cvmx-helper.h>
#include <asm/octeon/cvmx-pip-defs.h>
/**
* Probe a LOOP interface and determine the number of ports

6
drivers/staging/octeon/cvmx-helper-npi.c → arch/mips/cavium-octeon/executive/cvmx-helper-npi.c
View File

@ -31,11 +31,11 @@
*/
#include <asm/octeon/octeon.h>
#include "cvmx-config.h"
#include <asm/octeon/cvmx-config.h>
#include "cvmx-helper.h"
#include <asm/octeon/cvmx-helper.h>
#include "cvmx-pip-defs.h"
#include <asm/octeon/cvmx-pip-defs.h>
/**
* Probe a NPI interface and determine the number of ports

17
drivers/staging/octeon/cvmx-helper-rgmii.c → arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
View File

@ -31,18 +31,18 @@
*/
#include <asm/octeon/octeon.h>
#include "cvmx-config.h"
#include <asm/octeon/cvmx-config.h>
#include "cvmx-mdio.h"
#include "cvmx-pko.h"
#include "cvmx-helper.h"
#include "cvmx-helper-board.h"
#include <asm/octeon/cvmx-mdio.h>
#include <asm/octeon/cvmx-pko.h>
#include <asm/octeon/cvmx-helper.h>
#include <asm/octeon/cvmx-helper-board.h>
#include <asm/octeon/cvmx-npi-defs.h>
#include "cvmx-gmxx-defs.h"
#include "cvmx-asxx-defs.h"
#include "cvmx-dbg-defs.h"
#include <asm/octeon/cvmx-gmxx-defs.h>
#include <asm/octeon/cvmx-asxx-defs.h>
#include <asm/octeon/cvmx-dbg-defs.h>
void __cvmx_interrupt_gmxx_enable(int interface);
void __cvmx_interrupt_asxx_enable(int block);
@ -326,6 +326,7 @@ int __cvmx_helper_rgmii_link_set(int ipd_port,
cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) &
~(1 << index));
memset(pko_mem_queue_qos_save, 0, sizeof(pko_mem_queue_qos_save));
/* Disable all queues so that TX should become idle */
for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) {
int queue = cvmx_pko_get_base_queue(ipd_port) + i;

18
drivers/staging/octeon/cvmx-helper-sgmii.c → arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
View File

@ -32,14 +32,14 @@
#include <asm/octeon/octeon.h>
#include "cvmx-config.h"
#include <asm/octeon/cvmx-config.h>
#include "cvmx-mdio.h"
#include "cvmx-helper.h"
#include "cvmx-helper-board.h"
#include <asm/octeon/cvmx-mdio.h>
#include <asm/octeon/cvmx-helper.h>
#include <asm/octeon/cvmx-helper-board.h>
#include "cvmx-gmxx-defs.h"
#include "cvmx-pcsx-defs.h"
#include <asm/octeon/cvmx-gmxx-defs.h>
#include <asm/octeon/cvmx-pcsx-defs.h>
void __cvmx_interrupt_gmxx_enable(int interface);
void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
@ -326,6 +326,10 @@ static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports)
return 0;
}
int __cvmx_helper_sgmii_enumerate(int interface)
{
return 4;
}
/**
* Probe a SGMII interface and determine the number of ports
* connected to it. The SGMII interface should still be down after
@ -347,7 +351,7 @@ int __cvmx_helper_sgmii_probe(int interface)
mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
mode.s.en = 1;
cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
return 4;
return __cvmx_helper_sgmii_enumerate(interface);
}
/**

20
drivers/staging/octeon/cvmx-helper-spi.c → arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
View File

@ -35,12 +35,12 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index);
*/
#include <asm/octeon/octeon.h>
#include "cvmx-config.h"
#include "cvmx-spi.h"
#include "cvmx-helper.h"
#include <asm/octeon/cvmx-config.h>
#include <asm/octeon/cvmx-spi.h>
#include <asm/octeon/cvmx-helper.h>
#include "cvmx-pip-defs.h"
#include "cvmx-pko-defs.h"
#include <asm/octeon/cvmx-pip-defs.h>
#include <asm/octeon/cvmx-pko-defs.h>
/*
* CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI
@ -51,6 +51,16 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index);
#define CVMX_HELPER_SPI_TIMEOUT 10
#endif
int __cvmx_helper_spi_enumerate(int interface)
{
if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
cvmx_spi4000_is_present(interface)) {
return 10;
} else {
return 16;
}
}
/**
* Probe a SPI interface and determine the number of ports
* connected to it. The SPI interface should still be down after

16
drivers/staging/octeon/cvmx-helper-util.c → arch/mips/cavium-octeon/executive/cvmx-helper-util.c
View File

@ -32,16 +32,16 @@
#include <asm/octeon/octeon.h>
#include "cvmx-config.h"
#include <asm/octeon/cvmx-config.h>
#include "cvmx-fpa.h"
#include "cvmx-pip.h"
#include "cvmx-pko.h"
#include "cvmx-ipd.h"
#include "cvmx-spi.h"
#include <asm/octeon/cvmx-fpa.h>
#include <asm/octeon/cvmx-pip.h>
#include <asm/octeon/cvmx-pko.h>
#include <asm/octeon/cvmx-ipd.h>
#include <asm/octeon/cvmx-spi.h>
#include "cvmx-helper.h"
#include "cvmx-helper-util.h"
#include <asm/octeon/cvmx-helper.h>
#include <asm/octeon/cvmx-helper-util.h>
#include <asm/octeon/cvmx-ipd-defs.h>

32
drivers/staging/octeon/cvmx-helper-xaui.c → arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
View File

@ -33,17 +33,30 @@
#include <asm/octeon/octeon.h>
#include "cvmx-config.h"
#include <asm/octeon/cvmx-config.h>
#include "cvmx-helper.h"
#include <asm/octeon/cvmx-helper.h>
#include "cvmx-pko-defs.h"
#include "cvmx-gmxx-defs.h"
#include "cvmx-pcsxx-defs.h"
#include <asm/octeon/cvmx-pko-defs.h>
#include <asm/octeon/cvmx-gmxx-defs.h>
#include <asm/octeon/cvmx-pcsxx-defs.h>
void __cvmx_interrupt_gmxx_enable(int interface);
void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
int __cvmx_helper_xaui_enumerate(int interface)
{
union cvmx_gmxx_hg2_control gmx_hg2_control;
/* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
if (gmx_hg2_control.s.hg2tx_en)
return 16;
else
return 1;
}
/**
* Probe a XAUI interface and determine the number of ports
* connected to it. The XAUI interface should still be down
@ -56,7 +69,6 @@ void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
int __cvmx_helper_xaui_probe(int interface)
{
int i;
union cvmx_gmxx_hg2_control gmx_hg2_control;
union cvmx_gmxx_inf_mode mode;
/*
@ -90,13 +102,7 @@ int __cvmx_helper_xaui_probe(int interface)
pko_mem_port_ptrs.s.pid = interface * 16 + i;
cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
}
/* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
if (gmx_hg2_control.s.hg2tx_en)
return 16;
else
return 1;
return __cvmx_helper_xaui_enumerate(interface);
}
/**

126
drivers/staging/octeon/cvmx-helper.c → arch/mips/cavium-octeon/executive/cvmx-helper.c
View File

@ -32,19 +32,19 @@
*/
#include <asm/octeon/octeon.h>
#include "cvmx-config.h"
#include <asm/octeon/cvmx-config.h>
#include "cvmx-fpa.h"
#include "cvmx-pip.h"
#include "cvmx-pko.h"
#include "cvmx-ipd.h"
#include "cvmx-spi.h"
#include "cvmx-helper.h"
#include "cvmx-helper-board.h"
#include <asm/octeon/cvmx-fpa.h>
#include <asm/octeon/cvmx-pip.h>
#include <asm/octeon/cvmx-pko.h>
#include <asm/octeon/cvmx-ipd.h>
#include <asm/octeon/cvmx-spi.h>
#include <asm/octeon/cvmx-helper.h>
#include <asm/octeon/cvmx-helper-board.h>
#include "cvmx-pip-defs.h"
#include "cvmx-smix-defs.h"
#include "cvmx-asxx-defs.h"
#include <asm/octeon/cvmx-pip-defs.h>
#include <asm/octeon/cvmx-smix-defs.h>
#include <asm/octeon/cvmx-asxx-defs.h>
/**
* cvmx_override_pko_queue_priority(int ipd_port, uint64_t
@ -233,6 +233,80 @@ static int __cvmx_helper_port_setup_ipd(int ipd_port)
return 0;
}
/**
* This function sets the interface_port_count[interface] correctly,
* without modifying any hardware configuration. Hardware setup of
* the ports will be performed later.
*
* @interface: Interface to probe
*
* Returns Zero on success, negative on failure
*/
int cvmx_helper_interface_enumerate(int interface)
{
switch (cvmx_helper_interface_get_mode(interface)) {
/* These types don't support ports to IPD/PKO */
case CVMX_HELPER_INTERFACE_MODE_DISABLED:
case CVMX_HELPER_INTERFACE_MODE_PCIE:
interface_port_count[interface] = 0;
break;
/* XAUI is a single high speed port */
case CVMX_HELPER_INTERFACE_MODE_XAUI:
interface_port_count[interface] =
__cvmx_helper_xaui_enumerate(interface);
break;
/*
* RGMII/GMII/MII are all treated about the same. Most
* functions refer to these ports as RGMII.
*/
case CVMX_HELPER_INTERFACE_MODE_RGMII:
case CVMX_HELPER_INTERFACE_MODE_GMII:
interface_port_count[interface] =
__cvmx_helper_rgmii_enumerate(interface);
break;
/*
* SPI4 can have 1-16 ports depending on the device at
* the other end.
*/
case CVMX_HELPER_INTERFACE_MODE_SPI:
interface_port_count[interface] =
__cvmx_helper_spi_enumerate(interface);
break;
/*
* SGMII can have 1-4 ports depending on how many are
* hooked up.
*/
case CVMX_HELPER_INTERFACE_MODE_SGMII:
case CVMX_HELPER_INTERFACE_MODE_PICMG:
interface_port_count[interface] =
__cvmx_helper_sgmii_enumerate(interface);
break;
/* PCI target Network Packet Interface */
case CVMX_HELPER_INTERFACE_MODE_NPI:
interface_port_count[interface] =
__cvmx_helper_npi_enumerate(interface);
break;
/*
* Special loopback only ports. These are not the same
* as other ports in loopback mode.
*/
case CVMX_HELPER_INTERFACE_MODE_LOOP:
interface_port_count[interface] =
__cvmx_helper_loop_enumerate(interface);
break;
}
interface_port_count[interface] =
__cvmx_helper_board_interface_probe(interface,
interface_port_count
[interface]);
/* Make sure all global variables propagate to other cores */
CVMX_SYNCWS;
return 0;
}
/**
* This function probes an interface to determine the actual
* number of hardware ports connected to it. It doesn't setup the
@ -246,6 +320,7 @@ static int __cvmx_helper_port_setup_ipd(int ipd_port)
*/
int cvmx_helper_interface_probe(int interface)
{
cvmx_helper_interface_enumerate(interface);
/* At this stage in the game we don't want packets to be moving yet.
The following probe calls should perform hardware setup
needed to determine port counts. Receive must still be disabled */
@ -253,12 +328,10 @@ int cvmx_helper_interface_probe(int interface)
/* These types don't support ports to IPD/PKO */
case CVMX_HELPER_INTERFACE_MODE_DISABLED:
case CVMX_HELPER_INTERFACE_MODE_PCIE:
interface_port_count[interface] = 0;
break;
/* XAUI is a single high speed port */
case CVMX_HELPER_INTERFACE_MODE_XAUI:
interface_port_count[interface] =
__cvmx_helper_xaui_probe(interface);
__cvmx_helper_xaui_probe(interface);
break;
/*
* RGMII/GMII/MII are all treated about the same. Most
@ -266,16 +339,14 @@ int cvmx_helper_interface_probe(int interface)
*/
case CVMX_HELPER_INTERFACE_MODE_RGMII:
case CVMX_HELPER_INTERFACE_MODE_GMII:
interface_port_count[interface] =
__cvmx_helper_rgmii_probe(interface);
__cvmx_helper_rgmii_probe(interface);
break;
/*
* SPI4 can have 1-16 ports depending on the device at
* the other end.
*/
case CVMX_HELPER_INTERFACE_MODE_SPI:
interface_port_count[interface] =
__cvmx_helper_spi_probe(interface);
__cvmx_helper_spi_probe(interface);
break;
/*
* SGMII can have 1-4 ports depending on how many are
@ -283,29 +354,21 @@ int cvmx_helper_interface_probe(int interface)
*/
case CVMX_HELPER_INTERFACE_MODE_SGMII:
case CVMX_HELPER_INTERFACE_MODE_PICMG:
interface_port_count[interface] =
__cvmx_helper_sgmii_probe(interface);
__cvmx_helper_sgmii_probe(interface);
break;
/* PCI target Network Packet Interface */
case CVMX_HELPER_INTERFACE_MODE_NPI:
interface_port_count[interface] =
__cvmx_helper_npi_probe(interface);
__cvmx_helper_npi_probe(interface);
break;
/*
* Special loopback only ports. These are not the same
* as other ports in loopback mode.
*/
case CVMX_HELPER_INTERFACE_MODE_LOOP:
interface_port_count[interface] =
__cvmx_helper_loop_probe(interface);
__cvmx_helper_loop_probe(interface);
break;
}
interface_port_count[interface] =
__cvmx_helper_board_interface_probe(interface,
interface_port_count
[interface]);
/* Make sure all global variables propagate to other cores */
CVMX_SYNCWS;
@ -548,7 +611,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
union cvmx_gmxx_prtx_cfg gmx_cfg;
int retry_cnt;
int retry_loop_cnt;
int mtu;
int i;
cvmx_helper_link_info_t link_info;
@ -662,10 +724,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
1 << INDEX(FIX_IPD_OUTPORT));
mtu =
cvmx_read_csr(CVMX_GMXX_RXX_JABBER
(INDEX(FIX_IPD_OUTPORT),
INTERFACE(FIX_IPD_OUTPORT)));
cvmx_write_csr(CVMX_GMXX_RXX_JABBER
(INDEX(FIX_IPD_OUTPORT),
INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4);

10
drivers/staging/octeon/cvmx-interrupt-decodes.c → arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c
View File

@ -34,11 +34,11 @@
#include <asm/octeon/octeon.h>
#include "cvmx-gmxx-defs.h"
#include "cvmx-pcsx-defs.h"
#include "cvmx-pcsxx-defs.h"
#include "cvmx-spxx-defs.h"
#include "cvmx-stxx-defs.h"
#include <asm/octeon/cvmx-gmxx-defs.h>
#include <asm/octeon/cvmx-pcsx-defs.h>
#include <asm/octeon/cvmx-pcsxx-defs.h>
#include <asm/octeon/cvmx-spxx-defs.h>
#include <asm/octeon/cvmx-stxx-defs.h>
#ifndef PRINT_ERROR
#define PRINT_ERROR(format, ...)

4
drivers/staging/octeon/cvmx-interrupt-rsl.c → arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
View File

@ -32,8 +32,8 @@
#include <asm/octeon/octeon.h>
#include "cvmx-asxx-defs.h"
#include "cvmx-gmxx-defs.h"
#include <asm/octeon/cvmx-asxx-defs.h>
#include <asm/octeon/cvmx-gmxx-defs.h>
#ifndef PRINT_ERROR
#define PRINT_ERROR(format, ...)

8
drivers/staging/octeon/cvmx-pko.c → arch/mips/cavium-octeon/executive/cvmx-pko.c
View File

@ -31,9 +31,9 @@
#include <asm/octeon/octeon.h>
#include "cvmx-config.h"
#include "cvmx-pko.h"
#include "cvmx-helper.h"
#include <asm/octeon/cvmx-config.h>
#include <asm/octeon/cvmx-pko.h>
#include <asm/octeon/cvmx-helper.h>
/**
* Internal state of packet output
@ -54,7 +54,7 @@ void cvmx_pko_initialize_global(void)
/*
* Set the size of the PKO command buffers to an odd number of
* 64bit words. This allows the normal two word send to stay
* aligned and never span a command word buffer.
* aligned and never span a comamnd word buffer.
*/
config.u64 = 0;
config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;

12
drivers/staging/octeon/cvmx-spi.c → arch/mips/cavium-octeon/executive/cvmx-spi.c
View File

@ -31,14 +31,14 @@
*/
#include <asm/octeon/octeon.h>
#include "cvmx-config.h"
#include <asm/octeon/cvmx-config.h>
#include "cvmx-pko.h"
#include "cvmx-spi.h"
#include <asm/octeon/cvmx-pko.h>
#include <asm/octeon/cvmx-spi.h>
#include "cvmx-spxx-defs.h"
#include "cvmx-stxx-defs.h"
#include "cvmx-srxx-defs.h"
#include <asm/octeon/cvmx-spxx-defs.h>
#include <asm/octeon/cvmx-stxx-defs.h>
#include <asm/octeon/cvmx-srxx-defs.h>
#define INVOKE_CB(function_p, args...) \
do { \

119
arch/mips/cavium-octeon/executive/octeon-model.c
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
* Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -25,10 +25,6 @@
* Contact Cavium Networks for more information
***********************license end**************************************/
/*
* File defining functions for working with different Octeon
* models.
*/
#include <asm/octeon/octeon.h>
/**
@ -69,11 +65,12 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
char fuse_model[10];
uint32_t fuse_data = 0;
fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
fus3.u64 = 0;
if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
num_cores = cvmx_octeon_num_cores();
num_cores = cvmx_pop(cvmx_read_csr(CVMX_CIU_FUSE));
/* Make sure the non existent devices look disabled */
switch ((chip_id >> 8) & 0xff) {
@ -108,7 +105,7 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
* Assume pass number is encoded using <5:3><2:0>. Exceptions
* will be fixed later.
*/
sprintf(pass, "%u.%u", ((chip_id >> 3) & 7) + 1, chip_id & 7);
sprintf(pass, "%d.%d", (int)((chip_id >> 3) & 7) + 1, (int)chip_id & 7);
/*
* Use the number of cores to determine the last 2 digits of
@ -116,6 +113,12 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
* later.
*/
switch (num_cores) {
case 32:
core_model = "80";
break;
case 24:
core_model = "70";
break;
case 16:
core_model = "60";
break;
@ -246,8 +249,8 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
break;
case 3: /* CN58XX */
family = "58";
/* Special case. 4 core, no crypto */
if ((num_cores == 4) && fus_dat2.cn38xx.nocrypto)
/* Special case. 4 core, half cache (CP with half cache) */
if ((num_cores == 4) && fus3.cn58xx.crip_1024k && !strncmp(suffix, "CP", 2))
core_model = "29";
/* Pass 1 uses different encodings for pass numbers */
@ -285,6 +288,9 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
suffix = "NSP";
if (fus_dat3.s.nozip)
suffix = "SCP";
if (fus_dat3.s.bar2_en)
suffix = "NSPB2";
}
if (fus3.cn56xx.crip_1024k)
family = "54";
@ -301,6 +307,60 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
else
family = "52";
break;
case 0x93: /* CN61XX */
family = "61";
if (fus_dat2.cn61xx.nocrypto && fus_dat2.cn61xx.dorm_crypto)
suffix = "AP";
if (fus_dat2.cn61xx.nocrypto)
suffix = "CP";
else if (fus_dat2.cn61xx.dorm_crypto)
suffix = "DAP";
else if (fus_dat3.cn61xx.nozip)
suffix = "SCP";
break;
case 0x90: /* CN63XX */
family = "63";
if (fus_dat3.s.l2c_crip == 2)
family = "62";
if (num_cores == 6) /* Other core counts match generic */
core_model = "35";
if (fus_dat2.cn63xx.nocrypto)
suffix = "CP";
else if (fus_dat2.cn63xx.dorm_crypto)
suffix = "DAP";
else if (fus_dat3.cn63xx.nozip)
suffix = "SCP";
else
suffix = "AAP";
break;
case 0x92: /* CN66XX */
family = "66";
if (num_cores == 6) /* Other core counts match generic */
core_model = "35";
if (fus_dat2.cn66xx.nocrypto && fus_dat2.cn66xx.dorm_crypto)
suffix = "AP";
if (fus_dat2.cn66xx.nocrypto)
suffix = "CP";
else if (fus_dat2.cn66xx.dorm_crypto)
suffix = "DAP";
else if (fus_dat3.cn66xx.nozip)
suffix = "SCP";
else
suffix = "AAP";
break;
case 0x91: /* CN68XX */
family = "68";
if (fus_dat2.cn68xx.nocrypto && fus_dat3.cn68xx.nozip)
suffix = "CP";
else if (fus_dat2.cn68xx.dorm_crypto)
suffix = "DAP";
else if (fus_dat3.cn68xx.nozip)
suffix = "SCP";
else if (fus_dat2.cn68xx.nocrypto)
suffix = "SP";
else
suffix = "AAP";
break;
default:
family = "XX";
core_model = "XX";
@ -310,49 +370,40 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
}
clock_mhz = octeon_get_clock_rate() / 1000000;
if (family[0] != '3') {
int fuse_base = 384 / 8;
if (family[0] == '6')
fuse_base = 832 / 8;
/* Check for model in fuses, overrides normal decode */
/* This is _not_ valid for Octeon CN3XXX models */
fuse_data |= cvmx_fuse_read_byte(51);
fuse_data |= cvmx_fuse_read_byte(fuse_base + 3);
fuse_data = fuse_data << 8;
fuse_data |= cvmx_fuse_read_byte(50);
fuse_data |= cvmx_fuse_read_byte(fuse_base + 2);
fuse_data = fuse_data << 8;
fuse_data |= cvmx_fuse_read_byte(49);
fuse_data |= cvmx_fuse_read_byte(fuse_base + 1);
fuse_data = fuse_data << 8;
fuse_data |= cvmx_fuse_read_byte(48);
fuse_data |= cvmx_fuse_read_byte(fuse_base);
if (fuse_data & 0x7ffff) {
int model = fuse_data & 0x3fff;
int suffix = (fuse_data >> 14) & 0x1f;
if (suffix && model) {
/*
* Have both number and suffix in
* fuses, so both
*/
sprintf(fuse_model, "%d%c",
model, 'A' + suffix - 1);
/* Have both number and suffix in fuses, so both */
sprintf(fuse_model, "%d%c", model, 'A' + suffix - 1);
core_model = "";
family = fuse_model;
} else if (suffix && !model) {
/*
* Only have suffix, so add suffix to
* 'normal' model number.
*/
sprintf(fuse_model, "%s%c", core_model,
'A' + suffix - 1);
/* Only have suffix, so add suffix to 'normal' model number */
sprintf(fuse_model, "%s%c", core_model, 'A' + suffix - 1);
core_model = fuse_model;
} else {
/*
* Don't have suffix, so just use
* model from fuses.
*/
/* Don't have suffix, so just use model from fuses */
sprintf(fuse_model, "%d", model);
core_model = "";
family = fuse_model;
}
}
}
sprintf(buffer, "CN%s%sp%s-%d-%s",
family, core_model, pass, clock_mhz, suffix);
sprintf(buffer, "CN%s%sp%s-%d-%s", family, core_model, pass, clock_mhz, suffix);
return buffer;
}

570
arch/mips/configs/nlm_xlp_defconfig Normal file
View File

@ -0,0 +1,570 @@
CONFIG_NLM_XLP_BOARD=y
CONFIG_64BIT=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
CONFIG_SMP=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
# CONFIG_SECCOMP is not set
CONFIG_USE_OF=y
CONFIG_EXPERIMENTAL=y
CONFIG_CROSS_COMPILE="mips-linux-gnu-"
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_AUDIT=y
CONFIG_CGROUPS=y
CONFIG_NAMESPACES=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs.xlp"
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_INITRAMFS_COMPRESSION_LZMA=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_BLK_DEV_INTEGRITY=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_MISC=y
CONFIG_MIPS32_COMPAT=y
CONFIG_MIPS32_O32=y
CONFIG_MIPS32_N32=y
CONFIG_PM_RUNTIME=y
CONFIG_PM_DEBUG=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=m
CONFIG_NET_KEY=m
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_NET_IPIP=m
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
CONFIG_INET_XFRM_MODE_TRANSPORT=m
CONFIG_INET_XFRM_MODE_TUNNEL=m
CONFIG_INET_XFRM_MODE_BEET=m
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_MD5SIG=y
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_IPCOMP=m
CONFIG_INET6_XFRM_MODE_TRANSPORT=m
CONFIG_INET6_XFRM_MODE_TUNNEL=m
CONFIG_INET6_XFRM_MODE_BEET=m
CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
CONFIG_IPV6_SIT=m
CONFIG_IPV6_TUNNEL=m
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_NETLABEL=y
CONFIG_NETFILTER=y
CONFIG_NF_CONNTRACK=m
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CT_PROTO_UDPLITE=m
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NETFILTER_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
CONFIG_NETFILTER_XT_TARGET_SECMARK=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m
CONFIG_IP_VS_FTP=m
CONFIG_NF_CONNTRACK_IPV4=m
CONFIG_IP_NF_QUEUE=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_LOG=m
CONFIG_IP_NF_TARGET_ULOG=m
CONFIG_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_SECURITY=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_NF_CONNTRACK_IPV6=m
CONFIG_IP6_NF_QUEUE=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_TARGET_LOG=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP6_NF_SECURITY=m
CONFIG_DECNET_NF_GRABULATOR=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_ULOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
CONFIG_IP_DCCP=m
CONFIG_RDS=m
CONFIG_RDS_TCP=m
CONFIG_TIPC=m
CONFIG_ATM=m
CONFIG_ATM_CLIP=m
CONFIG_ATM_LANE=m
CONFIG_ATM_MPOA=m
CONFIG_ATM_BR2684=m
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_DECNET=m
CONFIG_LLC2=m
CONFIG_IPX=m
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
CONFIG_IPDDP_DECAP=y
CONFIG_X25=m
CONFIG_LAPB=m
CONFIG_ECONET=m
CONFIG_ECONET_AUNUDP=y
CONFIG_ECONET_NATIVE=y
CONFIG_WAN_ROUTER=m
CONFIG_PHONET=m
CONFIG_IEEE802154=m
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_ATM=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_RSVP=m
CONFIG_NET_CLS_RSVP6=m
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_DCB=y
CONFIG_NET_PKTGEN=m
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
CONFIG_CONNECTOR=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=m
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_OSD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_CDROM_PKTCDVD=y
CONFIG_RAID_ATTRS=m
CONFIG_SCSI=y
CONFIG_SCSI_TGT=m
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=m
CONFIG_CHR_DEV_OSST=m
CONFIG_BLK_DEV_SR=y
CONFIG_CHR_DEV_SG=y
CONFIG_CHR_DEV_SCH=m
CONFIG_SCSI_MULTI_LUN=y
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_SCSI_SPI_ATTRS=m
CONFIG_SCSI_FC_TGT_ATTRS=y
CONFIG_SCSI_SAS_LIBSAS=m
CONFIG_SCSI_SRP_ATTRS=m
CONFIG_SCSI_SRP_TGT_ATTRS=y
CONFIG_ISCSI_TCP=m
CONFIG_LIBFCOE=m
CONFIG_SCSI_DEBUG=m
CONFIG_SCSI_DH=y
CONFIG_SCSI_DH_RDAC=m
CONFIG_SCSI_DH_HP_SW=m
CONFIG_SCSI_DH_EMC=m
CONFIG_SCSI_DH_ALUA=m
CONFIG_SCSI_OSD_INITIATOR=m
CONFIG_SCSI_OSD_ULD=m
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_EVBUG=m
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=m
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIO_RAW=m
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
CONFIG_LEGACY_PTY_COUNT=0
CONFIG_SERIAL_NONSTANDARD=y
CONFIG_N_HDLC=m
# CONFIG_DEVKMEM is not set
CONFIG_STALDRV=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=48
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_RSA=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=m
CONFIG_RAW_DRIVER=m
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_UIO=y
CONFIG_UIO_PDRV=m
CONFIG_UIO_PDRV_GENIRQ=m
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_GFS2_FS=m
CONFIG_GFS2_FS_LOCKING_DLM=y
CONFIG_OCFS2_FS=m
CONFIG_BTRFS_FS=m
CONFIG_BTRFS_FS_POSIX_ACL=y
CONFIG_NILFS2_FS=m
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_PRINT_QUOTA_WARNING is not set
CONFIG_QFMT_V1=m
CONFIG_QFMT_V2=m
CONFIG_AUTOFS4_FS=m
CONFIG_FUSE_FS=y
CONFIG_CUSE=m
CONFIG_FSCACHE=m
CONFIG_FSCACHE_STATS=y
CONFIG_FSCACHE_HISTOGRAM=y
CONFIG_CACHEFILES=m
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_NTFS_FS=m
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_ADFS_FS=m
CONFIG_AFFS_FS=m
CONFIG_ECRYPT_FS=y
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
CONFIG_BEFS_FS=m
CONFIG_BFS_FS=m
CONFIG_EFS_FS=m
CONFIG_CRAMFS=m
CONFIG_SQUASHFS=m
CONFIG_VXFS_FS=m
CONFIG_MINIX_FS=m
CONFIG_OMFS_FS=m
CONFIG_HPFS_FS=m
CONFIG_QNX4FS_FS=m
CONFIG_ROMFS_FS=m
CONFIG_SYSV_FS=m
CONFIG_UFS_FS=m
CONFIG_EXOFS_FS=m
CONFIG_NFS_FS=m
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_FSCACHE=y
CONFIG_NFSD=m
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
CONFIG_CIFS=m
CONFIG_CIFS_WEAK_PW_HASH=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CIFS_DFS_UPCALL=y
CONFIG_NCP_FS=m
CONFIG_NCPFS_PACKET_SIGNING=y
CONFIG_NCPFS_IOCTL_LOCKING=y
CONFIG_NCPFS_STRONG=y
CONFIG_NCPFS_NFS_NS=y
CONFIG_NCPFS_OS2_NS=y
CONFIG_NCPFS_NLS=y
CONFIG_NCPFS_EXTRAS=y
CONFIG_CODA_FS=m
CONFIG_AFS_FS=m
CONFIG_PARTITION_ADVANCED=y
CONFIG_ACORN_PARTITION=y
CONFIG_ACORN_PARTITION_ICS=y
CONFIG_ACORN_PARTITION_RISCIX=y
CONFIG_OSF_PARTITION=y
CONFIG_AMIGA_PARTITION=y
CONFIG_ATARI_PARTITION=y
CONFIG_MAC_PARTITION=y
CONFIG_BSD_DISKLABEL=y
CONFIG_MINIX_SUBPARTITION=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_UNIXWARE_DISKLABEL=y
CONFIG_LDM_PARTITION=y
CONFIG_SGI_PARTITION=y
CONFIG_ULTRIX_PARTITION=y
CONFIG_SUN_PARTITION=y
CONFIG_KARMA_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_SYSV68_PARTITION=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="cp437"
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_PRINTK_TIME=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FRAME_WARN=1024
CONFIG_UNUSED_SYMBOLS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_SCHED_TRACER=y
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_KGDB=y
CONFIG_SECURITY=y
CONFIG_SECURITY_NETWORK=y
CONFIG_LSM_MMAP_MIN_ADDR=0
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0
CONFIG_SECURITY_SELINUX_DISABLE=y
CONFIG_SECURITY_SMACK=y
CONFIG_SECURITY_TOMOYO=y
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_CRYPTD=m
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_CCM=m
CONFIG_CRYPTO_GCM=m
CONFIG_CRYPTO_CTS=m
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_VMAC=m
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_RMD128=m
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_RMD256=m
CONFIG_CRYPTO_RMD320=m
CONFIG_CRYPTO_SHA256=m
CONFIG_CRYPTO_SHA512=m
CONFIG_CRYPTO_TGR192=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SALSA20=m
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_ZLIB=m
CONFIG_CRYPTO_LZO=m
CONFIG_CRC_CCITT=m
CONFIG_CRC7=m

16
arch/mips/configs/nlm_xlr_defconfig
View File

@ -8,7 +8,7 @@ CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_KEXEC=y
CONFIG_EXPERIMENTAL=y
CONFIG_CROSS_COMPILE="mips64-unknown-linux-gnu-"
CONFIG_CROSS_COMPILE="mips-linux-gnu-"
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
@ -22,15 +22,13 @@ CONFIG_AUDIT=y
CONFIG_NAMESPACES=y
CONFIG_SCHED_AUTOGROUP=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs"
CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs.xlr"
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_INITRAMFS_COMPRESSION_GZIP=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
CONFIG_KALLSYMS_ALL=y
# CONFIG_ELF_CORE is not set
# CONFIG_PCSPKR_PLATFORM is not set
# CONFIG_PERF_EVENTS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
@ -39,6 +37,9 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
CONFIG_PCI_DEBUG=y
CONFIG_BINFMT_MISC=m
CONFIG_PM_RUNTIME=y
CONFIG_PM_DEBUG=y
@ -297,12 +298,10 @@ CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_DCB=y
CONFIG_NET_PKTGEN=m
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
CONFIG_CONNECTOR=y
CONFIG_MTD=m
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=m
CONFIG_BLK_DEV_NBD=m
@ -339,6 +338,9 @@ CONFIG_SCSI_DH_EMC=m
CONFIG_SCSI_DH_ALUA=m
CONFIG_SCSI_OSD_INITIATOR=m
CONFIG_SCSI_OSD_ULD=m
CONFIG_NETDEVICES=y
CONFIG_E1000E=y
CONFIG_SKY2=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_EVBUG=m
@ -443,7 +445,6 @@ CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CIFS_DFS_UPCALL=y
CONFIG_CIFS_EXPERIMENTAL=y
CONFIG_NCP_FS=m
CONFIG_NCPFS_PACKET_SIGNING=y
CONFIG_NCPFS_IOCTL_LOCKING=y
@ -516,7 +517,6 @@ CONFIG_PRINTK_TIME=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_UNUSED_SYMBOLS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y

110
arch/mips/include/asm/bmips.h Normal file
View File

@ -0,0 +1,110 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
*
* Definitions for BMIPS processors
*/
#ifndef _ASM_BMIPS_H
#define _ASM_BMIPS_H
#include <linux/compiler.h>
#include <linux/linkage.h>
#include <asm/addrspace.h>
#include <asm/mipsregs.h>
#include <asm/hazards.h>
/* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
#define BMIPS_GET_CBR() ((void __iomem *)(CKSEG1 | \
(unsigned long) \
((read_c0_brcm_cbr() >> 18) << 18)))
#define BMIPS_RAC_CONFIG 0x00000000
#define BMIPS_RAC_ADDRESS_RANGE 0x00000004
#define BMIPS_RAC_CONFIG_1 0x00000008
#define BMIPS_L2_CONFIG 0x0000000c
#define BMIPS_LMB_CONTROL 0x0000001c
#define BMIPS_SYSTEM_BASE 0x00000020
#define BMIPS_PERF_GLOBAL_CONTROL 0x00020000
#define BMIPS_PERF_CONTROL_0 0x00020004
#define BMIPS_PERF_CONTROL_1 0x00020008
#define BMIPS_PERF_COUNTER_0 0x00020010
#define BMIPS_PERF_COUNTER_1 0x00020014
#define BMIPS_PERF_COUNTER_2 0x00020018
#define BMIPS_PERF_COUNTER_3 0x0002001c
#define BMIPS_RELO_VECTOR_CONTROL_0 0x00030000
#define BMIPS_RELO_VECTOR_CONTROL_1 0x00038000
#define BMIPS_NMI_RESET_VEC 0x80000000
#define BMIPS_WARM_RESTART_VEC 0x80000380
#define ZSCM_REG_BASE 0x97000000
#if !defined(__ASSEMBLY__)
#include <linux/cpumask.h>
#include <asm/r4kcache.h>
extern struct plat_smp_ops bmips_smp_ops;
extern char bmips_reset_nmi_vec;
extern char bmips_reset_nmi_vec_end;
extern char bmips_smp_movevec;
extern char bmips_smp_int_vec;
extern char bmips_smp_int_vec_end;
extern int bmips_smp_enabled;
extern int bmips_cpu_offset;
extern cpumask_t bmips_booted_mask;
extern void bmips_ebase_setup(void);
extern asmlinkage void plat_wired_tlb_setup(void);
static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
{
unsigned long ret;
__asm__ __volatile__(
".set push\n"
".set noreorder\n"
"cache %1, 0(%2)\n"
"sync\n"
"_ssnop\n"
"_ssnop\n"
"_ssnop\n"
"_ssnop\n"
"_ssnop\n"
"_ssnop\n"
"_ssnop\n"
"mfc0 %0, $28, 3\n"
"_ssnop\n"
".set pop\n"
: "=&r" (ret)
: "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset)
: "memory");
return ret;
}
static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
{
__asm__ __volatile__(
".set push\n"
".set noreorder\n"
"mtc0 %0, $28, 3\n"
"_ssnop\n"
"_ssnop\n"
"_ssnop\n"
"cache %1, 0(%2)\n"
"_ssnop\n"
"_ssnop\n"
"_ssnop\n"
: /* no outputs */
: "r" (data),
"i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset)
: "memory");
}
#endif /* !defined(__ASSEMBLY__) */
#endif /* _ASM_BMIPS_H */

5
arch/mips/include/asm/branch.h
View File

@ -9,6 +9,7 @@
#define _ASM_BRANCH_H
#include <asm/ptrace.h>
#include <asm/inst.h>
static inline int delay_slot(struct pt_regs *regs)
{
@ -23,7 +24,11 @@ static inline unsigned long exception_epc(struct pt_regs *regs)
return regs->cp0_epc + 4;
}
#define BRANCH_LIKELY_TAKEN 0x0001
extern int __compute_return_epc(struct pt_regs *regs);
extern int __compute_return_epc_for_insn(struct pt_regs *regs,
union mips_instruction insn);
static inline int compute_return_epc(struct pt_regs *regs)
{

5
arch/mips/include/asm/cpu.h
View File

@ -171,6 +171,9 @@
#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
#define PRID_IMP_NETLOGIC_AU13XX 0x8000
#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
/*
* Definitions for 7:0 on legacy processors
*/
@ -264,7 +267,7 @@ enum cpu_type_enum {
*/
CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
CPU_XLR,
CPU_XLR, CPU_XLP,
CPU_LAST
};

7
arch/mips/include/asm/hazards.h
View File

@ -87,7 +87,8 @@ do { \
: "=r" (tmp)); \
} while (0)
#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)
#elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
defined(CONFIG_CPU_BMIPS)
/*
* These are slightly complicated by the fact that we guarantee R1 kernels to
@ -139,8 +140,8 @@ do { \
} while (0)
#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
defined(CONFIG_CPU_R5500)
defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
defined(CONFIG_CPU_R5500)
/*
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.

5
arch/mips/include/asm/kprobes.h
View File

@ -74,6 +74,8 @@ struct prev_kprobe {
: MAX_JPROBES_STACK_SIZE)
#define SKIP_DELAYSLOT 0x0001
/* per-cpu kprobe control block */
struct kprobe_ctlblk {
unsigned long kprobe_status;
@ -82,6 +84,9 @@ struct kprobe_ctlblk {
unsigned long kprobe_saved_epc;
unsigned long jprobe_saved_sp;
struct pt_regs jprobe_saved_regs;
/* Per-thread fields, used while emulating branches */
unsigned long flags;
unsigned long target_epc;
u8 jprobes_stack[MAX_JPROBES_STACK_SIZE];
struct prev_kprobe prev_kprobe;
};

81
arch/mips/include/asm/mach-ath79/ar71xx_regs.h
View File

@ -20,6 +20,10 @@
#include <linux/bitops.h>
#define AR71XX_APB_BASE 0x18000000
#define AR71XX_EHCI_BASE 0x1b000000
#define AR71XX_EHCI_SIZE 0x1000
#define AR71XX_OHCI_BASE 0x1c000000
#define AR71XX_OHCI_SIZE 0x1000
#define AR71XX_SPI_BASE 0x1f000000
#define AR71XX_SPI_SIZE 0x01000000
@ -27,6 +31,8 @@
#define AR71XX_DDR_CTRL_SIZE 0x100
#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
#define AR71XX_UART_SIZE 0x100
#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
#define AR71XX_USB_CTRL_SIZE 0x100
#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
#define AR71XX_GPIO_SIZE 0x100
#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
@ -34,9 +40,26 @@
#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
#define AR71XX_RESET_SIZE 0x100
#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
#define AR7240_USB_CTRL_SIZE 0x100
#define AR7240_OHCI_BASE 0x1b000000
#define AR7240_OHCI_SIZE 0x1000
#define AR724X_EHCI_BASE 0x1b000000
#define AR724X_EHCI_SIZE 0x1000
#define AR913X_EHCI_BASE 0x1b000000
#define AR913X_EHCI_SIZE 0x1000
#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
#define AR913X_WMAC_SIZE 0x30000
#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
#define AR933X_UART_SIZE 0x14
#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
#define AR933X_WMAC_SIZE 0x20000
#define AR933X_EHCI_BASE 0x1b000000
#define AR933X_EHCI_SIZE 0x1000
/*
* DDR_CTRL block
*/
@ -63,6 +86,11 @@
#define AR913X_DDR_REG_FLUSH_USB 0x84
#define AR913X_DDR_REG_FLUSH_WMAC 0x88
#define AR933X_DDR_REG_FLUSH_GE0 0x7c
#define AR933X_DDR_REG_FLUSH_GE1 0x80
#define AR933X_DDR_REG_FLUSH_USB 0x84
#define AR933X_DDR_REG_FLUSH_WMAC 0x88
/*
* PLL block
*/
@ -104,6 +132,30 @@
#define AR913X_AHB_DIV_SHIFT 19
#define AR913X_AHB_DIV_MASK 0x1
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
/*
* USB_CONFIG block
*/
#define AR71XX_USB_CTRL_REG_FLADJ 0x00
#define AR71XX_USB_CTRL_REG_CONFIG 0x04
/*
* RESET block
*/
@ -130,6 +182,13 @@
#define AR724X_RESET_REG_RESET_MODULE 0x1c
#define AR933X_RESET_REG_RESET_MODULE 0x1c
#define AR933X_RESET_REG_BOOTSTRAP 0xac
#define MISC_INT_ETHSW BIT(12)
#define MISC_INT_TIMER4 BIT(10)
#define MISC_INT_TIMER3 BIT(9)
#define MISC_INT_TIMER2 BIT(8)
#define MISC_INT_DMA BIT(7)
#define MISC_INT_OHCI BIT(6)
#define MISC_INT_PERFC BIT(5)
@ -158,14 +217,29 @@
#define AR71XX_RESET_PCI_BUS BIT(1)
#define AR71XX_RESET_PCI_CORE BIT(0)
#define AR7240_RESET_USB_HOST BIT(5)
#define AR7240_RESET_OHCI_DLL BIT(3)
#define AR724X_RESET_GE1_MDIO BIT(23)
#define AR724X_RESET_GE0_MDIO BIT(22)
#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
#define AR724X_RESET_PCIE_PHY BIT(7)
#define AR724X_RESET_PCIE BIT(6)
#define AR724X_RESET_OHCI_DLL BIT(3)
#define AR724X_RESET_USB_HOST BIT(5)
#define AR724X_RESET_USB_PHY BIT(4)
#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
#define AR913X_RESET_AMBA2WMAC BIT(22)
#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
#define AR913X_RESET_USB_HOST BIT(5)
#define AR913X_RESET_USB_PHY BIT(4)
#define AR933X_RESET_WMAC BIT(11)
#define AR933X_RESET_USB_HOST BIT(5)
#define AR933X_RESET_USB_PHY BIT(4)
#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define REV_ID_MAJOR_MASK 0xfff0
#define REV_ID_MAJOR_AR71XX 0x00a0
@ -173,6 +247,8 @@
#define REV_ID_MAJOR_AR7240 0x00c0
#define REV_ID_MAJOR_AR7241 0x0100
#define REV_ID_MAJOR_AR7242 0x1100
#define REV_ID_MAJOR_AR9330 0x0110
#define REV_ID_MAJOR_AR9331 0x1110
#define AR71XX_REV_ID_MINOR_MASK 0x3
#define AR71XX_REV_ID_MINOR_AR7130 0x0
@ -187,6 +263,8 @@
#define AR913X_REV_ID_REVISION_MASK 0x3
#define AR913X_REV_ID_REVISION_SHIFT 2
#define AR933X_REV_ID_REVISION_MASK 0x3
#define AR724X_REV_ID_REVISION_MASK 0x3
/*
@ -229,5 +307,6 @@
#define AR71XX_GPIO_COUNT 16
#define AR724X_GPIO_COUNT 18
#define AR913X_GPIO_COUNT 22
#define AR933X_GPIO_COUNT 30
#endif /* __ASM_MACH_AR71XX_REGS_H */

67
arch/mips/include/asm/mach-ath79/ar933x_uart.h Normal file
View File

@ -0,0 +1,67 @@
/*
* Atheros AR933X UART defines
*
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __AR933X_UART_H
#define __AR933X_UART_H
#define AR933X_UART_REGS_SIZE 20
#define AR933X_UART_FIFO_SIZE 16
#define AR933X_UART_DATA_REG 0x00
#define AR933X_UART_CS_REG 0x04
#define AR933X_UART_CLOCK_REG 0x08
#define AR933X_UART_INT_REG 0x0c
#define AR933X_UART_INT_EN_REG 0x10
#define AR933X_UART_DATA_TX_RX_MASK 0xff
#define AR933X_UART_DATA_RX_CSR BIT(8)
#define AR933X_UART_DATA_TX_CSR BIT(9)
#define AR933X_UART_CS_PARITY_S 0
#define AR933X_UART_CS_PARITY_M 0x3
#define AR933X_UART_CS_PARITY_NONE 0
#define AR933X_UART_CS_PARITY_ODD 1
#define AR933X_UART_CS_PARITY_EVEN 2
#define AR933X_UART_CS_IF_MODE_S 2
#define AR933X_UART_CS_IF_MODE_M 0x3
#define AR933X_UART_CS_IF_MODE_NONE 0
#define AR933X_UART_CS_IF_MODE_DTE 1
#define AR933X_UART_CS_IF_MODE_DCE 2
#define AR933X_UART_CS_FLOW_CTRL_S 4
#define AR933X_UART_CS_FLOW_CTRL_M 0x3
#define AR933X_UART_CS_DMA_EN BIT(6)
#define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
#define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
#define AR933X_UART_CS_TX_READY BIT(9)
#define AR933X_UART_CS_RX_BREAK BIT(10)
#define AR933X_UART_CS_TX_BREAK BIT(11)
#define AR933X_UART_CS_HOST_INT BIT(12)
#define AR933X_UART_CS_HOST_INT_EN BIT(13)
#define AR933X_UART_CS_TX_BUSY BIT(14)
#define AR933X_UART_CS_RX_BUSY BIT(15)
#define AR933X_UART_CLOCK_STEP_M 0xffff
#define AR933X_UART_CLOCK_SCALE_M 0xfff
#define AR933X_UART_CLOCK_SCALE_S 16
#define AR933X_UART_CLOCK_STEP_M 0xffff
#define AR933X_UART_INT_RX_VALID BIT(0)
#define AR933X_UART_INT_TX_READY BIT(1)
#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2)
#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3)
#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4)
#define AR933X_UART_INT_RX_PARITY_ERR BIT(5)
#define AR933X_UART_INT_RX_BREAK_ON BIT(6)
#define AR933X_UART_INT_RX_BREAK_OFF BIT(7)
#define AR933X_UART_INT_RX_FULL BIT(8)
#define AR933X_UART_INT_TX_EMPTY BIT(9)
#define AR933X_UART_INT_ALLINTS 0x3ff
#endif /* __AR933X_UART_H */

18
arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h Normal file
View File

@ -0,0 +1,18 @@
/*
* Platform data definition for Atheros AR933X UART
*
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _AR933X_UART_PLATFORM_H
#define _AR933X_UART_PLATFORM_H
struct ar933x_uart_platform_data {
unsigned uartclk;
};
#endif /* _AR933X_UART_PLATFORM_H */

11
arch/mips/include/asm/mach-ath79/ath79.h
View File

@ -26,10 +26,13 @@ enum ath79_soc_type {
ATH79_SOC_AR7241,
ATH79_SOC_AR7242,
ATH79_SOC_AR9130,
ATH79_SOC_AR9132
ATH79_SOC_AR9132,
ATH79_SOC_AR9330,
ATH79_SOC_AR9331,
};
extern enum ath79_soc_type ath79_soc;
extern unsigned int ath79_soc_rev;
static inline int soc_is_ar71xx(void)
{
@ -66,6 +69,12 @@ static inline int soc_is_ar913x(void)
ath79_soc == ATH79_SOC_AR9132);
}
static inline int soc_is_ar933x(void)
{
return (ath79_soc == ATH79_SOC_AR9330 ||
ath79_soc == ATH79_SOC_AR9331);
}
extern void __iomem *ath79_ddr_base;
extern void __iomem *ath79_pll_base;
extern void __iomem *ath79_reset_base;

8
arch/mips/include/asm/mach-ath79/irq.h
View File

@ -10,10 +10,10 @@
#define __ASM_MACH_ATH79_IRQ_H
#define MIPS_CPU_IRQ_BASE 0
#define NR_IRQS 16
#define NR_IRQS 40
#define ATH79_MISC_IRQ_BASE 8
#define ATH79_MISC_IRQ_COUNT 8
#define ATH79_MISC_IRQ_COUNT 32
#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
@ -30,6 +30,10 @@
#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8)
#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9)
#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10)
#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12)
#include_next <irq.h>

21
arch/mips/include/asm/mach-ath79/pci-ath724x.h Normal file
View File

@ -0,0 +1,21 @@
/*
* Atheros 724x PCI support
*
* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
#define __ASM_MACH_ATH79_PCI_ATH724X_H
struct ath724x_pci_data {
int irq;
void *pdata;
};
void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */

597
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
View File

@ -13,6 +13,7 @@
#define BCM6345_CPU_ID 0x6345
#define BCM6348_CPU_ID 0x6348
#define BCM6358_CPU_ID 0x6358
#define BCM6368_CPU_ID 0x6368
void __init bcm63xx_cpu_init(void);
u16 __bcm63xx_get_cpu_id(void);
@ -71,6 +72,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
# define BCMCPU_IS_6358() (0)
#endif
#ifdef CONFIG_BCM63XX_CPU_6368
# ifdef bcm63xx_get_cpu_id
# undef bcm63xx_get_cpu_id
# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
# define BCMCPU_RUNTIME_DETECT
# else
# define bcm63xx_get_cpu_id() BCM6368_CPU_ID
# endif
# define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
#else
# define BCMCPU_IS_6368() (0)
#endif
#ifndef bcm63xx_get_cpu_id
#error "No CPU support configured"
#endif
@ -88,6 +102,7 @@ enum bcm63xx_regs_set {
RSET_UART1,
RSET_GPIO,
RSET_SPI,
RSET_SPI2,
RSET_UDC0,
RSET_OHCI0,
RSET_OHCI_PRIV,
@ -98,10 +113,23 @@ enum bcm63xx_regs_set {
RSET_ENET0,
RSET_ENET1,
RSET_ENETDMA,
RSET_ENETDMAC,
RSET_ENETDMAS,
RSET_ENETSW,
RSET_EHCI0,
RSET_SDRAM,
RSET_MEMC,
RSET_DDR,
RSET_M2M,
RSET_ATM,
RSET_XTM,
RSET_XTMDMA,
RSET_XTMDMAC,
RSET_XTMDMAS,
RSET_PCM,
RSET_PCMDMA,
RSET_PCMDMAC,
RSET_PCMDMAS,
};
#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
@ -109,11 +137,18 @@ enum bcm63xx_regs_set {
#define RSET_WDT_SIZE 12
#define RSET_ENET_SIZE 2048
#define RSET_ENETDMA_SIZE 2048
#define RSET_ENETSW_SIZE 65536
#define RSET_UART_SIZE 24
#define RSET_UDC_SIZE 256
#define RSET_OHCI_SIZE 256
#define RSET_EHCI_SIZE 256
#define RSET_PCMCIA_SIZE 12
#define RSET_M2M_SIZE 256
#define RSET_ATM_SIZE 4096
#define RSET_XTM_SIZE 10240
#define RSET_XTMDMA_SIZE 256
#define RSET_XTMDMAC_SIZE(chans) (16 * (chans))
#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
/*
* 6338 register sets base address
@ -127,6 +162,7 @@ enum bcm63xx_regs_set {
#define BCM_6338_UART1_BASE (0xdeadbeef)
#define BCM_6338_GPIO_BASE (0xfffe0400)
#define BCM_6338_SPI_BASE (0xfffe0c00)
#define BCM_6338_SPI2_BASE (0xdeadbeef)
#define BCM_6338_UDC0_BASE (0xdeadbeef)
#define BCM_6338_USBDMA_BASE (0xfffe2400)
#define BCM_6338_OHCI0_BASE (0xdeadbeef)
@ -136,15 +172,27 @@ enum bcm63xx_regs_set {
#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
#define BCM_6338_DSL_BASE (0xfffe1000)
#define BCM_6338_SAR_BASE (0xfffe2000)
#define BCM_6338_UBUS_BASE (0xdeadbeef)
#define BCM_6338_ENET0_BASE (0xfffe2800)
#define BCM_6338_ENET1_BASE (0xdeadbeef)
#define BCM_6338_ENETDMA_BASE (0xfffe2400)
#define BCM_6338_ENETDMAC_BASE (0xfffe2500)
#define BCM_6338_ENETDMAS_BASE (0xfffe2600)
#define BCM_6338_ENETSW_BASE (0xdeadbeef)
#define BCM_6338_EHCI0_BASE (0xdeadbeef)
#define BCM_6338_SDRAM_BASE (0xfffe3100)
#define BCM_6338_MEMC_BASE (0xdeadbeef)
#define BCM_6338_DDR_BASE (0xdeadbeef)
#define BCM_6338_M2M_BASE (0xdeadbeef)
#define BCM_6338_ATM_BASE (0xfffe2000)
#define BCM_6338_XTM_BASE (0xdeadbeef)
#define BCM_6338_XTMDMA_BASE (0xdeadbeef)
#define BCM_6338_XTMDMAC_BASE (0xdeadbeef)
#define BCM_6338_XTMDMAS_BASE (0xdeadbeef)
#define BCM_6338_PCM_BASE (0xdeadbeef)
#define BCM_6338_PCMDMA_BASE (0xdeadbeef)
#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
/*
* 6345 register sets base address
@ -158,24 +206,37 @@ enum bcm63xx_regs_set {
#define BCM_6345_UART1_BASE (0xdeadbeef)
#define BCM_6345_GPIO_BASE (0xfffe0400)
#define BCM_6345_SPI_BASE (0xdeadbeef)
#define BCM_6345_SPI2_BASE (0xdeadbeef)
#define BCM_6345_UDC0_BASE (0xdeadbeef)
#define BCM_6345_USBDMA_BASE (0xfffe2800)
#define BCM_6345_ENET0_BASE (0xfffe1800)
#define BCM_6345_ENETDMA_BASE (0xfffe2800)
#define BCM_6345_ENETDMAC_BASE (0xfffe2900)
#define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
#define BCM_6345_ENETSW_BASE (0xdeadbeef)
#define BCM_6345_PCMCIA_BASE (0xfffe2028)
#define BCM_6345_MPI_BASE (0xdeadbeef)
#define BCM_6345_MPI_BASE (0xfffe2000)
#define BCM_6345_OHCI0_BASE (0xfffe2100)
#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
#define BCM_6345_DSL_BASE (0xdeadbeef)
#define BCM_6345_SAR_BASE (0xdeadbeef)
#define BCM_6345_UBUS_BASE (0xdeadbeef)
#define BCM_6345_ENET1_BASE (0xdeadbeef)
#define BCM_6345_EHCI0_BASE (0xdeadbeef)
#define BCM_6345_SDRAM_BASE (0xfffe2300)
#define BCM_6345_MEMC_BASE (0xdeadbeef)
#define BCM_6345_DDR_BASE (0xdeadbeef)
#define BCM_6345_M2M_BASE (0xdeadbeef)
#define BCM_6345_ATM_BASE (0xfffe4000)
#define BCM_6345_XTM_BASE (0xdeadbeef)
#define BCM_6345_XTMDMA_BASE (0xdeadbeef)
#define BCM_6345_XTMDMAC_BASE (0xdeadbeef)
#define BCM_6345_XTMDMAS_BASE (0xdeadbeef)
#define BCM_6345_PCM_BASE (0xdeadbeef)
#define BCM_6345_PCMDMA_BASE (0xdeadbeef)
#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
/*
* 6348 register sets base address
@ -188,6 +249,7 @@ enum bcm63xx_regs_set {
#define BCM_6348_UART1_BASE (0xdeadbeef)
#define BCM_6348_GPIO_BASE (0xfffe0400)
#define BCM_6348_SPI_BASE (0xfffe0c00)
#define BCM_6348_SPI2_BASE (0xdeadbeef)
#define BCM_6348_UDC0_BASE (0xfffe1000)
#define BCM_6348_OHCI0_BASE (0xfffe1b00)
#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
@ -195,14 +257,27 @@ enum bcm63xx_regs_set {
#define BCM_6348_MPI_BASE (0xfffe2000)
#define BCM_6348_PCMCIA_BASE (0xfffe2054)
#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
#define BCM_6348_M2M_BASE (0xfffe2800)
#define BCM_6348_DSL_BASE (0xfffe3000)
#define BCM_6348_ENET0_BASE (0xfffe6000)
#define BCM_6348_ENET1_BASE (0xfffe6800)
#define BCM_6348_ENETDMA_BASE (0xfffe7000)
#define BCM_6348_ENETDMAC_BASE (0xfffe7100)
#define BCM_6348_ENETDMAS_BASE (0xfffe7200)
#define BCM_6348_ENETSW_BASE (0xdeadbeef)
#define BCM_6348_EHCI0_BASE (0xdeadbeef)
#define BCM_6348_SDRAM_BASE (0xfffe2300)
#define BCM_6348_MEMC_BASE (0xdeadbeef)
#define BCM_6348_DDR_BASE (0xdeadbeef)
#define BCM_6348_ATM_BASE (0xfffe4000)
#define BCM_6348_XTM_BASE (0xdeadbeef)
#define BCM_6348_XTMDMA_BASE (0xdeadbeef)
#define BCM_6348_XTMDMAC_BASE (0xdeadbeef)
#define BCM_6348_XTMDMAS_BASE (0xdeadbeef)
#define BCM_6348_PCM_BASE (0xdeadbeef)
#define BCM_6348_PCMDMA_BASE (0xdeadbeef)
#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
/*
* 6358 register sets base address
@ -215,6 +290,7 @@ enum bcm63xx_regs_set {
#define BCM_6358_UART1_BASE (0xfffe0120)
#define BCM_6358_GPIO_BASE (0xfffe0080)
#define BCM_6358_SPI_BASE (0xdeadbeef)
#define BCM_6358_SPI2_BASE (0xfffe0800)
#define BCM_6358_UDC0_BASE (0xfffe0800)
#define BCM_6358_OHCI0_BASE (0xfffe1400)
#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
@ -222,214 +298,175 @@ enum bcm63xx_regs_set {
#define BCM_6358_MPI_BASE (0xfffe1000)
#define BCM_6358_PCMCIA_BASE (0xfffe1054)
#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
#define BCM_6358_M2M_BASE (0xdeadbeef)
#define BCM_6358_DSL_BASE (0xfffe3000)
#define BCM_6358_ENET0_BASE (0xfffe4000)
#define BCM_6358_ENET1_BASE (0xfffe4800)
#define BCM_6358_ENETDMA_BASE (0xfffe5000)
#define BCM_6358_ENETDMAC_BASE (0xfffe5100)
#define BCM_6358_ENETDMAS_BASE (0xfffe5200)
#define BCM_6358_ENETSW_BASE (0xdeadbeef)
#define BCM_6358_EHCI0_BASE (0xfffe1300)
#define BCM_6358_SDRAM_BASE (0xdeadbeef)
#define BCM_6358_MEMC_BASE (0xfffe1200)
#define BCM_6358_DDR_BASE (0xfffe12a0)
#define BCM_6358_ATM_BASE (0xfffe2000)
#define BCM_6358_XTM_BASE (0xdeadbeef)
#define BCM_6358_XTMDMA_BASE (0xdeadbeef)
#define BCM_6358_XTMDMAC_BASE (0xdeadbeef)
#define BCM_6358_XTMDMAS_BASE (0xdeadbeef)
#define BCM_6358_PCM_BASE (0xfffe1600)
#define BCM_6358_PCMDMA_BASE (0xfffe1800)
#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
/*
* 6368 register sets base address
*/
#define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
#define BCM_6368_PERF_BASE (0xb0000000)
#define BCM_6368_TIMER_BASE (0xb0000040)
#define BCM_6368_WDT_BASE (0xb000005c)
#define BCM_6368_UART0_BASE (0xb0000100)
#define BCM_6368_UART1_BASE (0xb0000120)
#define BCM_6368_GPIO_BASE (0xb0000080)
#define BCM_6368_SPI_BASE (0xdeadbeef)
#define BCM_6368_SPI2_BASE (0xb0000800)
#define BCM_6368_UDC0_BASE (0xdeadbeef)
#define BCM_6368_OHCI0_BASE (0xb0001600)
#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
#define BCM_6368_MPI_BASE (0xb0001000)
#define BCM_6368_PCMCIA_BASE (0xb0001054)
#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
#define BCM_6368_M2M_BASE (0xdeadbeef)
#define BCM_6368_DSL_BASE (0xdeadbeef)
#define BCM_6368_ENET0_BASE (0xdeadbeef)
#define BCM_6368_ENET1_BASE (0xdeadbeef)
#define BCM_6368_ENETDMA_BASE (0xb0006800)
#define BCM_6368_ENETDMAC_BASE (0xb0006a00)
#define BCM_6368_ENETDMAS_BASE (0xb0006c00)
#define BCM_6368_ENETSW_BASE (0xb0f00000)
#define BCM_6368_EHCI0_BASE (0xb0001500)
#define BCM_6368_SDRAM_BASE (0xdeadbeef)
#define BCM_6368_MEMC_BASE (0xb0001200)
#define BCM_6368_DDR_BASE (0xb0001280)
#define BCM_6368_ATM_BASE (0xdeadbeef)
#define BCM_6368_XTM_BASE (0xb0001800)
#define BCM_6368_XTMDMA_BASE (0xb0005000)
#define BCM_6368_XTMDMAC_BASE (0xb0005200)
#define BCM_6368_XTMDMAS_BASE (0xb0005400)
#define BCM_6368_PCM_BASE (0xb0004000)
#define BCM_6368_PCMDMA_BASE (0xb0005800)
#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
extern const unsigned long *bcm63xx_regs_base;
#define __GEN_RSET_BASE(__cpu, __rset) \
case RSET_## __rset : \
return BCM_## __cpu ##_## __rset ##_BASE;
#define __GEN_RSET(__cpu) \
switch (set) { \
__GEN_RSET_BASE(__cpu, DSL_LMEM) \
__GEN_RSET_BASE(__cpu, PERF) \
__GEN_RSET_BASE(__cpu, TIMER) \
__GEN_RSET_BASE(__cpu, WDT) \
__GEN_RSET_BASE(__cpu, UART0) \
__GEN_RSET_BASE(__cpu, UART1) \
__GEN_RSET_BASE(__cpu, GPIO) \
__GEN_RSET_BASE(__cpu, SPI) \
__GEN_RSET_BASE(__cpu, SPI2) \
__GEN_RSET_BASE(__cpu, UDC0) \
__GEN_RSET_BASE(__cpu, OHCI0) \
__GEN_RSET_BASE(__cpu, OHCI_PRIV) \
__GEN_RSET_BASE(__cpu, USBH_PRIV) \
__GEN_RSET_BASE(__cpu, MPI) \
__GEN_RSET_BASE(__cpu, PCMCIA) \
__GEN_RSET_BASE(__cpu, DSL) \
__GEN_RSET_BASE(__cpu, ENET0) \
__GEN_RSET_BASE(__cpu, ENET1) \
__GEN_RSET_BASE(__cpu, ENETDMA) \
__GEN_RSET_BASE(__cpu, ENETDMAC) \
__GEN_RSET_BASE(__cpu, ENETDMAS) \
__GEN_RSET_BASE(__cpu, ENETSW) \
__GEN_RSET_BASE(__cpu, EHCI0) \
__GEN_RSET_BASE(__cpu, SDRAM) \
__GEN_RSET_BASE(__cpu, MEMC) \
__GEN_RSET_BASE(__cpu, DDR) \
__GEN_RSET_BASE(__cpu, M2M) \
__GEN_RSET_BASE(__cpu, ATM) \
__GEN_RSET_BASE(__cpu, XTM) \
__GEN_RSET_BASE(__cpu, XTMDMA) \
__GEN_RSET_BASE(__cpu, XTMDMAC) \
__GEN_RSET_BASE(__cpu, XTMDMAS) \
__GEN_RSET_BASE(__cpu, PCM) \
__GEN_RSET_BASE(__cpu, PCMDMA) \
__GEN_RSET_BASE(__cpu, PCMDMAC) \
__GEN_RSET_BASE(__cpu, PCMDMAS) \
}
#define __GEN_CPU_REGS_TABLE(__cpu) \
[RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
[RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
[RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \
[RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \
[RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \
[RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
[RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
[RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
[RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \
[RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
[RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
[RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
[RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
[RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
[RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
[RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
[RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
[RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
[RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \
[RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \
[RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \
[RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \
[RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \
[RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \
[RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \
[RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \
[RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \
[RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \
[RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \
[RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \
[RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \
[RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \
[RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \
[RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \
[RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
[RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
{
#ifdef BCMCPU_RUNTIME_DETECT
return bcm63xx_regs_base[set];
#else
#ifdef CONFIG_BCM63XX_CPU_6338
switch (set) {
case RSET_DSL_LMEM:
return BCM_6338_DSL_LMEM_BASE;
case RSET_PERF:
return BCM_6338_PERF_BASE;
case RSET_TIMER:
return BCM_6338_TIMER_BASE;
case RSET_WDT:
return BCM_6338_WDT_BASE;
case RSET_UART0:
return BCM_6338_UART0_BASE;
case RSET_UART1:
return BCM_6338_UART1_BASE;
case RSET_GPIO:
return BCM_6338_GPIO_BASE;
case RSET_SPI:
return BCM_6338_SPI_BASE;
case RSET_UDC0:
return BCM_6338_UDC0_BASE;
case RSET_OHCI0:
return BCM_6338_OHCI0_BASE;
case RSET_OHCI_PRIV:
return BCM_6338_OHCI_PRIV_BASE;
case RSET_USBH_PRIV:
return BCM_6338_USBH_PRIV_BASE;
case RSET_MPI:
return BCM_6338_MPI_BASE;
case RSET_PCMCIA:
return BCM_6338_PCMCIA_BASE;
case RSET_DSL:
return BCM_6338_DSL_BASE;
case RSET_ENET0:
return BCM_6338_ENET0_BASE;
case RSET_ENET1:
return BCM_6338_ENET1_BASE;
case RSET_ENETDMA:
return BCM_6338_ENETDMA_BASE;
case RSET_EHCI0:
return BCM_6338_EHCI0_BASE;
case RSET_SDRAM:
return BCM_6338_SDRAM_BASE;
case RSET_MEMC:
return BCM_6338_MEMC_BASE;
case RSET_DDR:
return BCM_6338_DDR_BASE;
}
__GEN_RSET(6338)
#endif
#ifdef CONFIG_BCM63XX_CPU_6345
switch (set) {
case RSET_DSL_LMEM:
return BCM_6345_DSL_LMEM_BASE;
case RSET_PERF:
return BCM_6345_PERF_BASE;
case RSET_TIMER:
return BCM_6345_TIMER_BASE;
case RSET_WDT:
return BCM_6345_WDT_BASE;
case RSET_UART0:
return BCM_6345_UART0_BASE;
case RSET_UART1:
return BCM_6345_UART1_BASE;
case RSET_GPIO:
return BCM_6345_GPIO_BASE;
case RSET_SPI:
return BCM_6345_SPI_BASE;
case RSET_UDC0:
return BCM_6345_UDC0_BASE;
case RSET_OHCI0:
return BCM_6345_OHCI0_BASE;
case RSET_OHCI_PRIV:
return BCM_6345_OHCI_PRIV_BASE;
case RSET_USBH_PRIV:
return BCM_6345_USBH_PRIV_BASE;
case RSET_MPI:
return BCM_6345_MPI_BASE;
case RSET_PCMCIA:
return BCM_6345_PCMCIA_BASE;
case RSET_DSL:
return BCM_6345_DSL_BASE;
case RSET_ENET0:
return BCM_6345_ENET0_BASE;
case RSET_ENET1:
return BCM_6345_ENET1_BASE;
case RSET_ENETDMA:
return BCM_6345_ENETDMA_BASE;
case RSET_EHCI0:
return BCM_6345_EHCI0_BASE;
case RSET_SDRAM:
return BCM_6345_SDRAM_BASE;
case RSET_MEMC:
return BCM_6345_MEMC_BASE;
case RSET_DDR:
return BCM_6345_DDR_BASE;
}
__GEN_RSET(6345)
#endif
#ifdef CONFIG_BCM63XX_CPU_6348
switch (set) {
case RSET_DSL_LMEM:
return BCM_6348_DSL_LMEM_BASE;
case RSET_PERF:
return BCM_6348_PERF_BASE;
case RSET_TIMER:
return BCM_6348_TIMER_BASE;
case RSET_WDT:
return BCM_6348_WDT_BASE;
case RSET_UART0:
return BCM_6348_UART0_BASE;
case RSET_UART1:
return BCM_6348_UART1_BASE;
case RSET_GPIO:
return BCM_6348_GPIO_BASE;
case RSET_SPI:
return BCM_6348_SPI_BASE;
case RSET_UDC0:
return BCM_6348_UDC0_BASE;
case RSET_OHCI0:
return BCM_6348_OHCI0_BASE;
case RSET_OHCI_PRIV:
return BCM_6348_OHCI_PRIV_BASE;
case RSET_USBH_PRIV:
return BCM_6348_USBH_PRIV_BASE;
case RSET_MPI:
return BCM_6348_MPI_BASE;
case RSET_PCMCIA:
return BCM_6348_PCMCIA_BASE;
case RSET_DSL:
return BCM_6348_DSL_BASE;
case RSET_ENET0:
return BCM_6348_ENET0_BASE;
case RSET_ENET1:
return BCM_6348_ENET1_BASE;
case RSET_ENETDMA:
return BCM_6348_ENETDMA_BASE;
case RSET_EHCI0:
return BCM_6348_EHCI0_BASE;
case RSET_SDRAM:
return BCM_6348_SDRAM_BASE;
case RSET_MEMC:
return BCM_6348_MEMC_BASE;
case RSET_DDR:
return BCM_6348_DDR_BASE;
}
__GEN_RSET(6348)
#endif
#ifdef CONFIG_BCM63XX_CPU_6358
switch (set) {
case RSET_DSL_LMEM:
return BCM_6358_DSL_LMEM_BASE;
case RSET_PERF:
return BCM_6358_PERF_BASE;
case RSET_TIMER:
return BCM_6358_TIMER_BASE;
case RSET_WDT:
return BCM_6358_WDT_BASE;
case RSET_UART0:
return BCM_6358_UART0_BASE;
case RSET_UART1:
return BCM_6358_UART1_BASE;
case RSET_GPIO:
return BCM_6358_GPIO_BASE;
case RSET_SPI:
return BCM_6358_SPI_BASE;
case RSET_UDC0:
return BCM_6358_UDC0_BASE;
case RSET_OHCI0:
return BCM_6358_OHCI0_BASE;
case RSET_OHCI_PRIV:
return BCM_6358_OHCI_PRIV_BASE;
case RSET_USBH_PRIV:
return BCM_6358_USBH_PRIV_BASE;
case RSET_MPI:
return BCM_6358_MPI_BASE;
case RSET_PCMCIA:
return BCM_6358_PCMCIA_BASE;
case RSET_ENET0:
return BCM_6358_ENET0_BASE;
case RSET_ENET1:
return BCM_6358_ENET1_BASE;
case RSET_ENETDMA:
return BCM_6358_ENETDMA_BASE;
case RSET_DSL:
return BCM_6358_DSL_BASE;
case RSET_EHCI0:
return BCM_6358_EHCI0_BASE;
case RSET_SDRAM:
return BCM_6358_SDRAM_BASE;
case RSET_MEMC:
return BCM_6358_MEMC_BASE;
case RSET_DDR:
return BCM_6358_DDR_BASE;
}
__GEN_RSET(6358)
#endif
#ifdef CONFIG_BCM63XX_CPU_6368
__GEN_RSET(6368)
#endif
#endif
/* unreached */
@ -449,75 +486,114 @@ enum bcm63xx_irq {
IRQ_ENET_PHY,
IRQ_OHCI0,
IRQ_EHCI0,
IRQ_PCMCIA0,
IRQ_ENET0_RXDMA,
IRQ_ENET0_TXDMA,
IRQ_ENET1_RXDMA,
IRQ_ENET1_TXDMA,
IRQ_PCI,
IRQ_PCMCIA,
IRQ_ATM,
IRQ_ENETSW_RXDMA0,
IRQ_ENETSW_RXDMA1,
IRQ_ENETSW_RXDMA2,
IRQ_ENETSW_RXDMA3,
IRQ_ENETSW_TXDMA0,
IRQ_ENETSW_TXDMA1,
IRQ_ENETSW_TXDMA2,
IRQ_ENETSW_TXDMA3,
IRQ_XTM,
IRQ_XTM_DMA0,
};
/*
* 6338 irqs
*/
#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
#define BCM_6338_UART1_IRQ 0
#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6338_ENET1_IRQ 0
#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11)
#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
#define BCM_6338_OHCI0_IRQ 0
#define BCM_6338_EHCI0_IRQ 0
#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
#define BCM_6338_ENET1_RXDMA_IRQ 0
#define BCM_6338_ENET1_TXDMA_IRQ 0
#define BCM_6338_PCI_IRQ 0
#define BCM_6338_PCMCIA_IRQ 0
#define BCM_6338_ATM_IRQ 0
#define BCM_6338_ENETSW_RXDMA0_IRQ 0
#define BCM_6338_ENETSW_RXDMA1_IRQ 0
#define BCM_6338_ENETSW_RXDMA2_IRQ 0
#define BCM_6338_ENETSW_RXDMA3_IRQ 0
#define BCM_6338_ENETSW_TXDMA0_IRQ 0
#define BCM_6338_ENETSW_TXDMA1_IRQ 0
#define BCM_6338_ENETSW_TXDMA2_IRQ 0
#define BCM_6338_ENETSW_TXDMA3_IRQ 0
#define BCM_6338_XTM_IRQ 0
#define BCM_6338_XTM_DMA0_IRQ 0
/*
* 6345 irqs
*/
#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6345_UART1_IRQ 0
#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6345_ENET1_IRQ 0
#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6345_OHCI0_IRQ 0
#define BCM_6345_EHCI0_IRQ 0
#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5)
#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6)
#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9)
#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10)
#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13)
#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14)
#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15)
#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16)
#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17)
#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18)
#define BCM_6345_ENET1_RXDMA_IRQ 0
#define BCM_6345_ENET1_TXDMA_IRQ 0
#define BCM_6345_PCI_IRQ 0
#define BCM_6345_PCMCIA_IRQ 0
#define BCM_6345_ATM_IRQ 0
#define BCM_6345_ENETSW_RXDMA0_IRQ 0
#define BCM_6345_ENETSW_RXDMA1_IRQ 0
#define BCM_6345_ENETSW_RXDMA2_IRQ 0
#define BCM_6345_ENETSW_RXDMA3_IRQ 0
#define BCM_6345_ENETSW_TXDMA0_IRQ 0
#define BCM_6345_ENETSW_TXDMA1_IRQ 0
#define BCM_6345_ENETSW_TXDMA2_IRQ 0
#define BCM_6345_ENETSW_TXDMA3_IRQ 0
#define BCM_6345_XTM_IRQ 0
#define BCM_6345_XTM_DMA0_IRQ 0
/*
* 6348 irqs
*/
#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6348_UART1_IRQ 0
#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6348_EHCI0_IRQ 0
#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
#define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6348_ENETSW_RXDMA0_IRQ 0
#define BCM_6348_ENETSW_RXDMA1_IRQ 0
#define BCM_6348_ENETSW_RXDMA2_IRQ 0
#define BCM_6348_ENETSW_RXDMA3_IRQ 0
#define BCM_6348_ENETSW_TXDMA0_IRQ 0
#define BCM_6348_ENETSW_TXDMA1_IRQ 0
#define BCM_6348_ENETSW_TXDMA2_IRQ 0
#define BCM_6348_ENETSW_TXDMA3_IRQ 0
#define BCM_6348_XTM_IRQ 0
#define BCM_6348_XTM_DMA0_IRQ 0
/*
* 6358 irqs
@ -525,21 +601,108 @@ enum bcm63xx_irq {
#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
#define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19)
#define BCM_6358_ENETSW_RXDMA0_IRQ 0
#define BCM_6358_ENETSW_RXDMA1_IRQ 0
#define BCM_6358_ENETSW_RXDMA2_IRQ 0
#define BCM_6358_ENETSW_RXDMA3_IRQ 0
#define BCM_6358_ENETSW_TXDMA0_IRQ 0
#define BCM_6358_ENETSW_TXDMA1_IRQ 0
#define BCM_6358_ENETSW_TXDMA2_IRQ 0
#define BCM_6358_ENETSW_TXDMA3_IRQ 0
#define BCM_6358_XTM_IRQ 0
#define BCM_6358_XTM_DMA0_IRQ 0
#define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23)
#define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24)
#define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
#define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
/*
* 6368 irqs
*/
#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
#define BCM_6368_ENET0_IRQ 0
#define BCM_6368_ENET1_IRQ 0
#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
#define BCM_6368_PCMCIA_IRQ 0
#define BCM_6368_ENET0_RXDMA_IRQ 0
#define BCM_6368_ENET0_TXDMA_IRQ 0
#define BCM_6368_ENET1_RXDMA_IRQ 0
#define BCM_6368_ENET1_TXDMA_IRQ 0
#define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13)
#define BCM_6368_ATM_IRQ 0
#define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0)
#define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1)
#define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2)
#define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3)
#define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4)
#define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5)
#define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6)
#define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7)
#define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11)
#define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8)
#define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30)
#define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31)
#define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20)
#define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21)
#define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22)
#define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23)
#define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
#define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
extern const int *bcm63xx_irqs;
#define __GEN_CPU_IRQ_TABLE(__cpu) \
[IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
[IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
[IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
[IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
[IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
[IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
[IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
[IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
[IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
[IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
[IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \
[IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \
[IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \
[IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \
[IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \
[IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \
[IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \
[IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \
[IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \
[IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \
[IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \
[IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \
[IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \
[IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \
[IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \
[IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \
static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
{
return bcm63xx_irqs[irq];
@ -550,4 +713,8 @@ static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
*/
unsigned int bcm63xx_get_memory_size(void);
void bcm63xx_machine_halt(void);
void bcm63xx_machine_reboot(void);
#endif /* !BCM63XX_CPU_H_ */

2
arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
View File

@ -14,6 +14,8 @@ static inline unsigned long bcm63xx_gpio_count(void)
return 8;
case BCM6345_CPU_ID:
return 16;
case BCM6368_CPU_ID:
return 38;
case BCM6348_CPU_ID:
default:
return 37;

2
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
View File

@ -49,9 +49,11 @@
#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a))
#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a))
#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a))
#define bcm_readq(a) (*(volatile u64 *) BCM_REGS_VA(a))
#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
#define bcm_writeq(v, a) (*(volatile u64 *) BCM_REGS_VA((a)) = (v))
/*
* IO helpers to access register set for current CPU

12
arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
View File

@ -3,13 +3,11 @@
#include <bcm63xx_cpu.h>
#define IRQ_MIPS_BASE 0
#define IRQ_INTERNAL_BASE 8
#define IRQ_EXT_BASE (IRQ_MIPS_BASE + 3)
#define IRQ_EXT_0 (IRQ_EXT_BASE + 0)
#define IRQ_EXT_1 (IRQ_EXT_BASE + 1)
#define IRQ_EXT_2 (IRQ_EXT_BASE + 2)
#define IRQ_EXT_3 (IRQ_EXT_BASE + 3)
#define IRQ_EXTERNAL_BASE 100
#define IRQ_EXT_0 (IRQ_EXTERNAL_BASE + 0)
#define IRQ_EXT_1 (IRQ_EXTERNAL_BASE + 1)
#define IRQ_EXT_2 (IRQ_EXTERNAL_BASE + 2)
#define IRQ_EXT_3 (IRQ_EXTERNAL_BASE + 3)
#endif /* ! BCM63XX_IRQ_H_ */

231
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
View File

@ -83,30 +83,86 @@
CKCTL_6358_USBSU_EN | \
CKCTL_6358_EPHY_EN)
#define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
#define CKCTL_6368_VDSL_AFE_EN (1 << 3)
#define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
#define CKCTL_6368_VDSL_EN (1 << 5)
#define CKCTL_6368_PHYMIPS_EN (1 << 6)
#define CKCTL_6368_SWPKT_USB_EN (1 << 7)
#define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
#define CKCTL_6368_SPI_CLK_EN (1 << 9)
#define CKCTL_6368_USBD_CLK_EN (1 << 10)
#define CKCTL_6368_SAR_CLK_EN (1 << 11)
#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12)
#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13)
#define CKCTL_6368_PCM_CLK_EN (1 << 14)
#define CKCTL_6368_USBH_CLK_EN (1 << 15)
#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
#define CKCTL_6368_NAND_CLK_EN (1 << 17)
#define CKCTL_6368_IPSEC_CLK_EN (1 << 17)
#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
CKCTL_6368_SWPKT_SAR_EN | \
CKCTL_6368_SPI_CLK_EN | \
CKCTL_6368_USBD_CLK_EN | \
CKCTL_6368_SAR_CLK_EN | \
CKCTL_6368_ROBOSW_CLK_EN | \
CKCTL_6368_UTOPIA_CLK_EN | \
CKCTL_6368_PCM_CLK_EN | \
CKCTL_6368_USBH_CLK_EN | \
CKCTL_6368_DISABLE_GLESS_EN | \
CKCTL_6368_NAND_CLK_EN | \
CKCTL_6368_IPSEC_CLK_EN)
/* System PLL Control register */
#define PERF_SYS_PLL_CTL_REG 0x8
#define SYS_PLL_SOFT_RESET 0x1
/* Interrupt Mask register */
#define PERF_IRQMASK_REG 0xc
#define PERF_IRQMASK_6338_REG 0xc
#define PERF_IRQMASK_6345_REG 0xc
#define PERF_IRQMASK_6348_REG 0xc
#define PERF_IRQMASK_6358_REG 0xc
#define PERF_IRQMASK_6368_REG 0x20
/* Interrupt Status register */
#define PERF_IRQSTAT_REG 0x10
#define PERF_IRQSTAT_6338_REG 0x10
#define PERF_IRQSTAT_6345_REG 0x10
#define PERF_IRQSTAT_6348_REG 0x10
#define PERF_IRQSTAT_6358_REG 0x10
#define PERF_IRQSTAT_6368_REG 0x28
/* External Interrupt Configuration register */
#define PERF_EXTIRQ_CFG_REG 0x14
#define EXTIRQ_CFG_SENSE(x) (1 << (x))
#define EXTIRQ_CFG_STAT(x) (1 << (x + 5))
#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10))
#define EXTIRQ_CFG_MASK(x) (1 << (x + 15))
#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20))
#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25))
#define PERF_EXTIRQ_CFG_REG_6338 0x14
#define PERF_EXTIRQ_CFG_REG_6348 0x14
#define PERF_EXTIRQ_CFG_REG_6358 0x14
#define PERF_EXTIRQ_CFG_REG_6368 0x18
#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10)
#define EXTIRQ_CFG_MASK_ALL (0xf << 15)
#define PERF_EXTIRQ_CFG_REG2_6368 0x1c
/* for 6348 only */
#define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
#define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5))
#define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10))
#define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15))
#define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20))
#define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25))
#define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10)
#define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15)
/* for all others */
#define EXTIRQ_CFG_SENSE(x) (1 << (x))
#define EXTIRQ_CFG_STAT(x) (1 << (x + 4))
#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8))
#define EXTIRQ_CFG_MASK(x) (1 << (x + 12))
#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16))
#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20))
#define EXTIRQ_CFG_CLEAR_ALL (0xf << 8)
#define EXTIRQ_CFG_MASK_ALL (0xf << 12)
/* Soft Reset register */
#define PERF_SOFTRESET_REG 0x28
#define PERF_SOFTRESET_6368_REG 0x10
#define SOFTRESET_6338_SPI_MASK (1 << 0)
#define SOFTRESET_6338_ENET_MASK (1 << 2)
@ -147,6 +203,15 @@
SOFTRESET_6348_ACLC_MASK | \
SOFTRESET_6348_ADSLMIPSPLL_MASK)
#define SOFTRESET_6368_SPI_MASK (1 << 0)
#define SOFTRESET_6368_MPI_MASK (1 << 3)
#define SOFTRESET_6368_EPHY_MASK (1 << 6)
#define SOFTRESET_6368_SAR_MASK (1 << 7)
#define SOFTRESET_6368_ENETSW_MASK (1 << 10)
#define SOFTRESET_6368_USBS_MASK (1 << 11)
#define SOFTRESET_6368_USBH_MASK (1 << 12)
#define SOFTRESET_6368_PCM_MASK (1 << 13)
/* MIPS PLL control register */
#define PERF_MIPSPLLCTL_REG 0x34
#define MIPSPLLCTL_N1_SHIFT 20
@ -372,6 +437,7 @@
#define GPIO_CTL_LO_REG 0x4
#define GPIO_DATA_HI_REG 0x8
#define GPIO_DATA_LO_REG 0xC
#define GPIO_DATA_LO_REG_6345 0x8
/* GPIO mux registers and constants */
#define GPIO_MODE_REG 0x18
@ -402,6 +468,44 @@
#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
#define GPIO_MODE_6358_UTOPIA (1 << 12)
#define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0)
#define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1)
#define GPIO_MODE_6368_SYS_IRQ (1 << 2)
#define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3)
#define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4)
#define GPIO_MODE_6368_INET_LED (1 << 5)
#define GPIO_MODE_6368_EPHY0_LED (1 << 6)
#define GPIO_MODE_6368_EPHY1_LED (1 << 7)
#define GPIO_MODE_6368_EPHY2_LED (1 << 8)
#define GPIO_MODE_6368_EPHY3_LED (1 << 9)
#define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10)
#define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11)
#define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12)
#define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13)
#define GPIO_MODE_6368_USBD_LED (1 << 14)
#define GPIO_MODE_6368_NTR_PULSE (1 << 15)
#define GPIO_MODE_6368_PCI_REQ1 (1 << 16)
#define GPIO_MODE_6368_PCI_GNT1 (1 << 17)
#define GPIO_MODE_6368_PCI_INTB (1 << 18)
#define GPIO_MODE_6368_PCI_REQ0 (1 << 19)
#define GPIO_MODE_6368_PCI_GNT0 (1 << 20)
#define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22)
#define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23)
#define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24)
#define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25)
#define GPIO_MODE_6368_EBI_CS2 (1 << 26)
#define GPIO_MODE_6368_EBI_CS3 (1 << 27)
#define GPIO_MODE_6368_SPI_SSN2 (1 << 28)
#define GPIO_MODE_6368_SPI_SSN3 (1 << 29)
#define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
#define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
#define GPIO_BASEMODE_6368_REG 0x38
#define GPIO_BASEMODE_6368_UART2 0x1
#define GPIO_BASEMODE_6368_GPIO 0x0
#define GPIO_BASEMODE_6368_MASK 0x7
/* those bits must be kept as read in gpio basemode register*/
/*************************************************************************
* _REG relative to RSET_ENET
@ -547,6 +651,56 @@
#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
/*************************************************************************
* _REG relative to RSET_ENETDMAC
*************************************************************************/
/* Channel Configuration register */
#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
#define ENETDMAC_CHANCFG_EN_SHIFT 0
#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
#define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
/* Interrupt Control/Status register */
#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
#define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
#define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
#define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
/* Interrupt Mask register */
#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
/* Maximum Burst Length */
#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
/*************************************************************************
* _REG relative to RSET_ENETDMAS
*************************************************************************/
/* Ring Start Address register */
#define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
/* State Ram Word 2 */
#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
/* State Ram Word 3 */
#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
/* State Ram Word 4 */
#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
/*************************************************************************
* _REG relative to RSET_ENETSW
*************************************************************************/
/* MIB register */
#define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
#define ENETSW_MIB_REG_COUNT 47
/*************************************************************************
* _REG relative to RSET_OHCI_PRIV
*************************************************************************/
@ -562,7 +716,9 @@
* _REG relative to RSET_USBH_PRIV
*************************************************************************/
#define USBH_PRIV_SWAP_REG 0x0
#define USBH_PRIV_SWAP_6358_REG 0x0
#define USBH_PRIV_SWAP_6368_REG 0x1c
#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
@ -572,7 +728,13 @@
#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
#define USBH_PRIV_TEST_REG 0x24
#define USBH_PRIV_TEST_6358_REG 0x24
#define USBH_PRIV_TEST_6368_REG 0x14
#define USBH_PRIV_SETUP_6368_REG 0x28
#define USBH_PRIV_SETUP_IOC_SHIFT 4
#define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
/*************************************************************************
@ -734,6 +896,8 @@
#define SDRAM_CFG_BANK_SHIFT 13
#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
#define SDRAM_MBASE_REG 0xc
#define SDRAM_PRIO_REG 0x2C
#define SDRAM_PRIO_MIPS_SHIFT 29
#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
@ -768,4 +932,45 @@
#define DMIPSPLLCFG_N2_SHIFT 29
#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
#define DDR_DMIPSPLLCFG_6368_REG 0x20
#define DMIPSPLLCFG_6368_P1_SHIFT 0
#define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
#define DMIPSPLLCFG_6368_P2_SHIFT 4
#define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
#define DMIPSPLLCFG_6368_NDIV_SHIFT 16
#define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
#define DDR_DMIPSPLLDIV_6368_REG 0x24
#define DMIPSPLLDIV_6368_MDIV_SHIFT 0
#define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
/*************************************************************************
* _REG relative to RSET_M2M
*************************************************************************/
#define M2M_RX 0
#define M2M_TX 1
#define M2M_SRC_REG(x) ((x) * 0x40 + 0x00)
#define M2M_DST_REG(x) ((x) * 0x40 + 0x04)
#define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08)
#define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c)
#define M2M_CTRL_ENABLE_MASK (1 << 0)
#define M2M_CTRL_IRQEN_MASK (1 << 1)
#define M2M_CTRL_ERROR_CLR_MASK (1 << 6)
#define M2M_CTRL_DONE_CLR_MASK (1 << 7)
#define M2M_CTRL_NOINC_MASK (1 << 8)
#define M2M_CTRL_PCMCIASWAP_MASK (1 << 9)
#define M2M_CTRL_SWAPBYTE_MASK (1 << 10)
#define M2M_CTRL_ENDIAN_MASK (1 << 11)
#define M2M_STAT_REG(x) ((x) * 0x40 + 0x10)
#define M2M_STAT_DONE (1 << 0)
#define M2M_STAT_ERROR (1 << 1)
#define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
#define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
#endif /* BCM63XX_REGS_H_ */

42
arch/mips/include/asm/mach-bcm63xx/ioremap.h Normal file
View File

@ -0,0 +1,42 @@
#ifndef BCM63XX_IOREMAP_H_
#define BCM63XX_IOREMAP_H_
#include <bcm63xx_cpu.h>
static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
{
return phys_addr;
}
static inline int is_bcm63xx_internal_registers(phys_t offset)
{
switch (bcm63xx_get_cpu_id()) {
case BCM6338_CPU_ID:
case BCM6345_CPU_ID:
case BCM6348_CPU_ID:
case BCM6358_CPU_ID:
if (offset >= 0xfff00000)
return 1;
break;
case BCM6368_CPU_ID:
if (offset >= 0xb0000000 && offset < 0xb1000000)
return 1;
break;
}
return 0;
}
static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
unsigned long flags)
{
if (is_bcm63xx_internal_registers(offset))
return (void __iomem *)offset;
return NULL;
}
static inline int plat_iounmap(const volatile void __iomem *addr)
{
return is_bcm63xx_internal_registers((unsigned long)addr);
}
#endif /* BCM63XX_IOREMAP_H_ */

7
arch/mips/include/asm/mach-bcm63xx/irq.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __ASM_MACH_BCM63XX_IRQ_H
#define __ASM_MACH_BCM63XX_IRQ_H
#define NR_IRQS 128
#define MIPS_CPU_IRQ_BASE 0
#endif

23
arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
View File

@ -24,24 +24,33 @@
#define cpu_has_llsc 1
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_ic_fills_f_dc 1
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_icache_snoops_remote_store 0
#define cpu_icache_snoops_remote_store 1
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 1
#define cpu_has_mips64r2 0
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#if defined(CONFIG_CPU_XLR)
#define cpu_has_userlocal 0
#define cpu_has_dc_aliases 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r2 0
#elif defined(CONFIG_CPU_XLP)
#define cpu_has_userlocal 1
#define cpu_has_mips32r2 1
#define cpu_has_mips64r2 1
#define cpu_has_dc_aliases 1
#else
#error "Unknown Netlogic CPU"
#endif
#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */

9
arch/mips/include/asm/mipsregs.h
View File

@ -1106,7 +1106,7 @@ do { \
#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
/* BMIPS4380 */
/* BMIPS43xx */
#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
@ -1667,6 +1667,13 @@ __BUILD_SET_C0(config)
__BUILD_SET_C0(intcontrol)
__BUILD_SET_C0(intctl)
__BUILD_SET_C0(srsmap)
__BUILD_SET_C0(brcm_config_0)
__BUILD_SET_C0(brcm_bus_pll)
__BUILD_SET_C0(brcm_reset)
__BUILD_SET_C0(brcm_cmt_intr)
__BUILD_SET_C0(brcm_cmt_ctrl)
__BUILD_SET_C0(brcm_config)
__BUILD_SET_C0(brcm_mode)
#endif /* !__ASSEMBLY__ */

6
arch/mips/include/asm/module.h
View File

@ -74,7 +74,9 @@ search_module_dbetables(unsigned long addr)
}
#endif
#ifdef CONFIG_CPU_MIPS32_R1
#ifdef CONFIG_CPU_BMIPS
#define MODULE_PROC_FAMILY "BMIPS "
#elif defined CONFIG_CPU_MIPS32_R1
#define MODULE_PROC_FAMILY "MIPS32_R1 "
#elif defined CONFIG_CPU_MIPS32_R2
#define MODULE_PROC_FAMILY "MIPS32_R2 "
@ -120,6 +122,8 @@ search_module_dbetables(unsigned long addr)
#define MODULE_PROC_FAMILY "OCTEON "
#elif defined CONFIG_CPU_XLR
#define MODULE_PROC_FAMILY "XLR "
#elif defined CONFIG_CPU_XLP
#define MODULE_PROC_FAMILY "XLP "
#else
#error MODULE_PROC_FAMILY undefined for your processor configuration
#endif

76
arch/mips/include/asm/netlogic/common.h Normal file
View File

@ -0,0 +1,76 @@
/*
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
* reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the NetLogic
* license below:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _NETLOGIC_COMMON_H_
#define _NETLOGIC_COMMON_H_
/*
* Common SMP definitions
*/
#define RESET_VEC_PHYS 0x1fc00000
#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10))
#define BOOT_THREAD_MODE 0
#define BOOT_NMI_LOCK 4
#define BOOT_NMI_HANDLER 8
#ifndef __ASSEMBLY__
struct irq_desc;
extern struct plat_smp_ops nlm_smp_ops;
extern char nlm_reset_entry[], nlm_reset_entry_end[];
void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
void nlm_smp_irq_init(void);
void nlm_boot_secondary_cpus(void);
int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
void nlm_rmiboot_preboot(void);
static inline void
nlm_set_nmi_handler(void *handler)
{
char *reset_data;
reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
*(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler;
}
/*
* Misc.
*/
unsigned int nlm_get_cpu_frequency(void);
extern unsigned long nlm_common_ebase;
extern int nlm_threads_per_core;
extern uint32_t nlm_cpumask, nlm_coremask;
#endif
#endif /* _NETLOGIC_COMMON_H_ */

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/*
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
* reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the NetLogic
* license below:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __NLM_HAL_HALDEFS_H__
#define __NLM_HAL_HALDEFS_H__
/*
* This file contains platform specific memory mapped IO implementation
* and will provide a way to read 32/64 bit memory mapped registers in
* all ABIs
*/
#if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP)
#error "o32 compile not supported on XLP yet"
#endif
/*
* For o32 compilation, we have to disable interrupts and enable KX bit to
* access 64 bit addresses or data.
*
* We need to disable interrupts because we save just the lower 32 bits of
* registers in interrupt handling. So if we get hit by an interrupt while
* using the upper 32 bits of a register, we lose.
*/
static inline uint32_t nlm_save_flags_kx(void)
{
return change_c0_status(ST0_KX | ST0_IE, ST0_KX);
}
static inline uint32_t nlm_save_flags_cop2(void)
{
return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2);
}
static inline void nlm_restore_flags(uint32_t sr)
{
write_c0_status(sr);
}
/*
* The n64 implementations are simple, the o32 implementations when they
* are added, will have to disable interrupts and enable KX before doing
* 64 bit ops.
*/
static inline uint32_t
nlm_read_reg(uint64_t base, uint32_t reg)
{
volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
return *addr;
}
static inline void
nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
{
volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
*addr = val;
}
static inline uint64_t
nlm_read_reg64(uint64_t base, uint32_t reg)
{
uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
return *ptr;
}
static inline void
nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
{
uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
*ptr = val;
}
/*
* Routines to store 32/64 bit values to 64 bit addresses,
* used when going thru XKPHYS to access registers
*/
static inline uint32_t
nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
{
return nlm_read_reg(base, reg);
}
static inline void
nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
{
nlm_write_reg(base, reg, val);
}
static inline uint64_t
nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
{
return nlm_read_reg64(base, reg);
}
static inline void
nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
{
nlm_write_reg64(base, reg, val);
}
/* Location where IO base is mapped */
extern uint64_t nlm_io_base;
#if defined(CONFIG_CPU_XLP)
static inline uint64_t
nlm_pcicfg_base(uint32_t devoffset)
{
return nlm_io_base + devoffset;
}
static inline uint64_t
nlm_xkphys_map_pcibar0(uint64_t pcibase)
{
uint64_t paddr;
paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
return (uint64_t)0x9000000000000000 | paddr;
}
#elif defined(CONFIG_CPU_XLR)
static inline uint64_t
nlm_mmio_base(uint32_t devoffset)
{
return nlm_io_base + devoffset;
}
#endif
#endif

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/*
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
* reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the NetLogic
* license below:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __NLM_HAL_BRIDGE_H__
#define __NLM_HAL_BRIDGE_H__
/**
* @file_name mio.h
* @author Netlogic Microsystems
* @brief Basic definitions of XLP memory and io subsystem
*/
/*
* BRIDGE specific registers
*
* These registers start after the PCIe header, which has 0x40
* standard entries
*/
#define BRIDGE_MODE 0x00
#define BRIDGE_PCI_CFG_BASE 0x01
#define BRIDGE_PCI_CFG_LIMIT 0x02
#define BRIDGE_PCIE_CFG_BASE 0x03
#define BRIDGE_PCIE_CFG_LIMIT 0x04
#define BRIDGE_BUSNUM_BAR0 0x05
#define BRIDGE_BUSNUM_BAR1 0x06
#define BRIDGE_BUSNUM_BAR2 0x07
#define BRIDGE_BUSNUM_BAR3 0x08
#define BRIDGE_BUSNUM_BAR4 0x09
#define BRIDGE_BUSNUM_BAR5 0x0a
#define BRIDGE_BUSNUM_BAR6 0x0b
#define BRIDGE_FLASH_BAR0 0x0c
#define BRIDGE_FLASH_BAR1 0x0d
#define BRIDGE_FLASH_BAR2 0x0e
#define BRIDGE_FLASH_BAR3 0x0f
#define BRIDGE_FLASH_LIMIT0 0x10
#define BRIDGE_FLASH_LIMIT1 0x11
#define BRIDGE_FLASH_LIMIT2 0x12
#define BRIDGE_FLASH_LIMIT3 0x13
#define BRIDGE_DRAM_BAR(i) (0x14 + (i))
#define BRIDGE_DRAM_BAR0 0x14
#define BRIDGE_DRAM_BAR1 0x15
#define BRIDGE_DRAM_BAR2 0x16
#define BRIDGE_DRAM_BAR3 0x17
#define BRIDGE_DRAM_BAR4 0x18
#define BRIDGE_DRAM_BAR5 0x19
#define BRIDGE_DRAM_BAR6 0x1a
#define BRIDGE_DRAM_BAR7 0x1b
#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i))
#define BRIDGE_DRAM_LIMIT0 0x1c
#define BRIDGE_DRAM_LIMIT1 0x1d
#define BRIDGE_DRAM_LIMIT2 0x1e
#define BRIDGE_DRAM_LIMIT3 0x1f
#define BRIDGE_DRAM_LIMIT4 0x20
#define BRIDGE_DRAM_LIMIT5 0x21
#define BRIDGE_DRAM_LIMIT6 0x22
#define BRIDGE_DRAM_LIMIT7 0x23
#define BRIDGE_DRAM_NODE_TRANSLN0 0x24
#define BRIDGE_DRAM_NODE_TRANSLN1 0x25
#define BRIDGE_DRAM_NODE_TRANSLN2 0x26
#define BRIDGE_DRAM_NODE_TRANSLN3 0x27
#define BRIDGE_DRAM_NODE_TRANSLN4 0x28
#define BRIDGE_DRAM_NODE_TRANSLN5 0x29
#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a
#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b
#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c
#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d
#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e
#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f
#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30
#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31
#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32
#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33
#define BRIDGE_PCIEMEM_BASE0 0x34
#define BRIDGE_PCIEMEM_BASE1 0x35
#define BRIDGE_PCIEMEM_BASE2 0x36
#define BRIDGE_PCIEMEM_BASE3 0x37
#define BRIDGE_PCIEMEM_LIMIT0 0x38
#define BRIDGE_PCIEMEM_LIMIT1 0x39
#define BRIDGE_PCIEMEM_LIMIT2 0x3a
#define BRIDGE_PCIEMEM_LIMIT3 0x3b
#define BRIDGE_PCIEIO_BASE0 0x3c
#define BRIDGE_PCIEIO_BASE1 0x3d
#define BRIDGE_PCIEIO_BASE2 0x3e
#define BRIDGE_PCIEIO_BASE3 0x3f
#define BRIDGE_PCIEIO_LIMIT0 0x40
#define BRIDGE_PCIEIO_LIMIT1 0x41
#define BRIDGE_PCIEIO_LIMIT2 0x42
#define BRIDGE_PCIEIO_LIMIT3 0x43
#define BRIDGE_PCIEMEM_BASE4 0x44
#define BRIDGE_PCIEMEM_BASE5 0x45
#define BRIDGE_PCIEMEM_BASE6 0x46
#define BRIDGE_PCIEMEM_LIMIT4 0x47
#define BRIDGE_PCIEMEM_LIMIT5 0x48
#define BRIDGE_PCIEMEM_LIMIT6 0x49
#define BRIDGE_PCIEIO_BASE4 0x4a
#define BRIDGE_PCIEIO_BASE5 0x4b
#define BRIDGE_PCIEIO_BASE6 0x4c
#define BRIDGE_PCIEIO_LIMIT4 0x4d
#define BRIDGE_PCIEIO_LIMIT5 0x4e
#define BRIDGE_PCIEIO_LIMIT6 0x4f
#define BRIDGE_NBU_EVENT_CNT_CTL 0x50
#define BRIDGE_EVNTCTR1_LOW 0x51
#define BRIDGE_EVNTCTR1_HI 0x52
#define BRIDGE_EVNT_CNT_CTL2 0x53
#define BRIDGE_EVNTCTR2_LOW 0x54
#define BRIDGE_EVNTCTR2_HI 0x55
#define BRIDGE_TRACEBUF_MATCH0 0x56
#define BRIDGE_TRACEBUF_MATCH1 0x57
#define BRIDGE_TRACEBUF_MATCH_LOW 0x58
#define BRIDGE_TRACEBUF_MATCH_HI 0x59
#define BRIDGE_TRACEBUF_CTRL 0x5a
#define BRIDGE_TRACEBUF_INIT 0x5b
#define BRIDGE_TRACEBUF_ACCESS 0x5c
#define BRIDGE_TRACEBUF_READ_DATA0 0x5d
#define BRIDGE_TRACEBUF_READ_DATA1 0x5d
#define BRIDGE_TRACEBUF_READ_DATA2 0x5f
#define BRIDGE_TRACEBUF_READ_DATA3 0x60
#define BRIDGE_TRACEBUF_STATUS 0x61
#define BRIDGE_ADDRESS_ERROR0 0x62
#define BRIDGE_ADDRESS_ERROR1 0x63
#define BRIDGE_ADDRESS_ERROR2 0x64
#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65
#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66
#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67
#define BRIDGE_LINE_FLUSH0 0x68
#define BRIDGE_LINE_FLUSH1 0x69
#define BRIDGE_NODE_ID 0x6a
#define BRIDGE_ERROR_INTERRUPT_EN 0x6b
#define BRIDGE_PCIE0_WEIGHT 0x2c0
#define BRIDGE_PCIE1_WEIGHT 0x2c1
#define BRIDGE_PCIE2_WEIGHT 0x2c2
#define BRIDGE_PCIE3_WEIGHT 0x2c3
#define BRIDGE_USB_WEIGHT 0x2c4
#define BRIDGE_NET_WEIGHT 0x2c5
#define BRIDGE_POE_WEIGHT 0x2c6
#define BRIDGE_CMS_WEIGHT 0x2c7
#define BRIDGE_DMAENG_WEIGHT 0x2c8
#define BRIDGE_SEC_WEIGHT 0x2c9
#define BRIDGE_COMP_WEIGHT 0x2ca
#define BRIDGE_GIO_WEIGHT 0x2cb
#define BRIDGE_FLASH_WEIGHT 0x2cc
#ifndef __ASSEMBLY__
#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r)
#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v)
#define nlm_get_bridge_pcibase(node) \
nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
#define nlm_get_bridge_regbase(node) \
(nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
#endif /* __ASSEMBLY__ */
#endif /* __NLM_HAL_BRIDGE_H__ */

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/*
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
* reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the NetLogic
* license below:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __NLM_HAL_CPUCONTROL_H__
#define __NLM_HAL_CPUCONTROL_H__
#define CPU_BLOCKID_IFU 0
#define CPU_BLOCKID_ICU 1
#define CPU_BLOCKID_IEU 2
#define CPU_BLOCKID_LSU 3
#define CPU_BLOCKID_MMU 4
#define CPU_BLOCKID_PRF 5
#define CPU_BLOCKID_SCH 7
#define CPU_BLOCKID_SCU 8
#define CPU_BLOCKID_FPU 9
#define CPU_BLOCKID_MAP 10
#define LSU_DEFEATURE 0x304
#define LSU_CERRLOG_REGID 0x09
#define SCHED_DEFEATURE 0x700
/* Offsets of interest from the 'MAP' Block */
#define MAP_THREADMODE 0x00
#define MAP_EXT_EBASE_ENABLE 0x04
#define MAP_CCDI_CONFIG 0x08
#define MAP_THRD0_CCDI_STATUS 0x0c
#define MAP_THRD1_CCDI_STATUS 0x10
#define MAP_THRD2_CCDI_STATUS 0x14
#define MAP_THRD3_CCDI_STATUS 0x18
#define MAP_THRD0_DEBUG_MODE 0x1c
#define MAP_THRD1_DEBUG_MODE 0x20
#define MAP_THRD2_DEBUG_MODE 0x24
#define MAP_THRD3_DEBUG_MODE 0x28
#define MAP_MISC_STATE 0x60
#define MAP_DEBUG_READ_CTL 0x64
#define MAP_DEBUG_READ_REG0 0x68
#define MAP_DEBUG_READ_REG1 0x6c
#define MMU_SETUP 0x400
#define MMU_LFSRSEED 0x401
#define MMU_HPW_NUM_PAGE_LVL 0x410
#define MMU_PGWKR_PGDBASE 0x411
#define MMU_PGWKR_PGDSHFT 0x412
#define MMU_PGWKR_PGDMASK 0x413
#define MMU_PGWKR_PUDSHFT 0x414
#define MMU_PGWKR_PUDMASK 0x415
#define MMU_PGWKR_PMDSHFT 0x416
#define MMU_PGWKR_PMDMASK 0x417
#define MMU_PGWKR_PTESHFT 0x418
#define MMU_PGWKR_PTEMASK 0x419
#endif /* __NLM_CPUCONTROL_H__ */

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/*
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
* reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the NetLogic
* license below:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __NLM_HAL_IOMAP_H__
#define __NLM_HAL_IOMAP_H__
#define XLP_DEFAULT_IO_BASE 0x18000000
#define NMI_BASE 0xbfc00000
#define XLP_IO_CLK 133333333
#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */
#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE)
#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE)
#define XLP_IO_SIZE (64 << 20) /* ECFG space size */
#define XLP_IO_PCI_HDRSZ 0x100
#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8)
#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \
((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12))
#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0)
/* coherent inter chip */
#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1)
#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2)
#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3)
#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4)
#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i)
#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0)
#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1)
#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2)
#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3)
#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i)
#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0)
#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1)
#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2)
#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3)
#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0)
#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1)
#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2)
#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3)
#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i)
#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0)
#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1)
#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i)
#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2)
#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3)
#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4)
/* system management */
#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5)
#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6)
#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0)
#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1)
#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2)
/* SD flash */
#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3)
#define XLP_IO_MMC_OFFSET(node, slot) \
((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
/* PCI config header register id's */
#define XLP_PCI_CFGREG0 0x00
#define XLP_PCI_CFGREG1 0x01
#define XLP_PCI_CFGREG2 0x02
#define XLP_PCI_CFGREG3 0x03
#define XLP_PCI_CFGREG4 0x04
#define XLP_PCI_CFGREG5 0x05
#define XLP_PCI_DEVINFO_REG0 0x30
#define XLP_PCI_DEVINFO_REG1 0x31
#define XLP_PCI_DEVINFO_REG2 0x32
#define XLP_PCI_DEVINFO_REG3 0x33
#define XLP_PCI_DEVINFO_REG4 0x34
#define XLP_PCI_DEVINFO_REG5 0x35
#define XLP_PCI_DEVINFO_REG6 0x36
#define XLP_PCI_DEVINFO_REG7 0x37
#define XLP_PCI_DEVSCRATCH_REG0 0x38
#define XLP_PCI_DEVSCRATCH_REG1 0x39
#define XLP_PCI_DEVSCRATCH_REG2 0x3a
#define XLP_PCI_DEVSCRATCH_REG3 0x3b
#define XLP_PCI_MSGSTN_REG 0x3c
#define XLP_PCI_IRTINFO_REG 0x3d
#define XLP_PCI_UCODEINFO_REG 0x3e
#define XLP_PCI_SBB_WT_REG 0x3f
/* PCI IDs for SoC device */
#define PCI_VENDOR_NETLOGIC 0x184e
#define PCI_DEVICE_ID_NLM_ROOT 0x1001
#define PCI_DEVICE_ID_NLM_ICI 0x1002
#define PCI_DEVICE_ID_NLM_PIC 0x1003
#define PCI_DEVICE_ID_NLM_PCIE 0x1004
#define PCI_DEVICE_ID_NLM_EHCI 0x1007
#define PCI_DEVICE_ID_NLM_ILK 0x1008
#define PCI_DEVICE_ID_NLM_NAE 0x1009
#define PCI_DEVICE_ID_NLM_POE 0x100A
#define PCI_DEVICE_ID_NLM_FMN 0x100B
#define PCI_DEVICE_ID_NLM_RAID 0x100D
#define PCI_DEVICE_ID_NLM_SAE 0x100D
#define PCI_DEVICE_ID_NLM_RSA 0x100E
#define PCI_DEVICE_ID_NLM_CMP 0x100F
#define PCI_DEVICE_ID_NLM_UART 0x1010
#define PCI_DEVICE_ID_NLM_I2C 0x1011
#define PCI_DEVICE_ID_NLM_NOR 0x1015
#define PCI_DEVICE_ID_NLM_NAND 0x1016
#define PCI_DEVICE_ID_NLM_MMC 0x1018
#ifndef __ASSEMBLY__
#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r)
#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v)
#endif /* !__ASSEMBLY */
#endif /* __NLM_HAL_IOMAP_H__ */

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/*
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
* reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the NetLogic
* license below:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _NLM_HAL_PIC_H
#define _NLM_HAL_PIC_H
/* PIC Specific registers */
#define PIC_CTRL 0x00
/* PIC control register defines */
#define PIC_CTRL_ITV 32 /* interrupt timeout value */
#define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */
#define PIC_CTRL_ITE 18 /* interrupt timeout enable */
#define PIC_CTRL_STE 10 /* system timer interrupt enable */
#define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */
#define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */
#define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */
#define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */
#define PIC_CTRL_WTE 0 /* watchdog timer enable */
/* PIC Status register defines */
#define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */
#define PIC_ITE_STATUS 32 /* interrupt timeout status */
#define PIC_STS_STATUS 4 /* System timer interrupt status */
#define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */
#define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */
/* PIC IPI control register offsets */
#define PIC_IPICTRL_NMI 32
#define PIC_IPICTRL_RIV 20 /* received interrupt vector */
#define PIC_IPICTRL_IDB 16 /* interrupt destination base */
#define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */
/* PIC IRT register offsets */
#define PIC_IRT_ENABLE 31
#define PIC_IRT_NMI 29
#define PIC_IRT_SCH 28 /* Scheduling scheme */
#define PIC_IRT_RVEC 20 /* Interrupt receive vectors */
#define PIC_IRT_DT 19 /* Destination type */
#define PIC_IRT_DB 16 /* Destination base */
#define PIC_IRT_DTE 0 /* Destination thread enables */
#define PIC_BYTESWAP 0x02
#define PIC_STATUS 0x04
#define PIC_INTR_TIMEOUT 0x06
#define PIC_ICI0_INTR_TIMEOUT 0x08
#define PIC_ICI1_INTR_TIMEOUT 0x0a
#define PIC_ICI2_INTR_TIMEOUT 0x0c
#define PIC_IPI_CTL 0x0e
#define PIC_INT_ACK 0x10
#define PIC_INT_PENDING0 0x12
#define PIC_INT_PENDING1 0x14
#define PIC_INT_PENDING2 0x16
#define PIC_WDOG0_MAXVAL 0x18
#define PIC_WDOG0_COUNT 0x1a
#define PIC_WDOG0_ENABLE0 0x1c
#define PIC_WDOG0_ENABLE1 0x1e
#define PIC_WDOG0_BEATCMD 0x20
#define PIC_WDOG0_BEAT0 0x22
#define PIC_WDOG0_BEAT1 0x24
#define PIC_WDOG1_MAXVAL 0x26
#define PIC_WDOG1_COUNT 0x28
#define PIC_WDOG1_ENABLE0 0x2a
#define PIC_WDOG1_ENABLE1 0x2c
#define PIC_WDOG1_BEATCMD 0x2e
#define PIC_WDOG1_BEAT0 0x30
#define PIC_WDOG1_BEAT1 0x32
#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
#define PIC_TIMER0_MAXVAL 0x34
#define PIC_TIMER1_MAXVAL 0x36
#define PIC_TIMER2_MAXVAL 0x38
#define PIC_TIMER3_MAXVAL 0x3a
#define PIC_TIMER4_MAXVAL 0x3c
#define PIC_TIMER5_MAXVAL 0x3e
#define PIC_TIMER6_MAXVAL 0x40
#define PIC_TIMER7_MAXVAL 0x42
#define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2))
#define PIC_TIMER0_COUNT 0x44
#define PIC_TIMER1_COUNT 0x46
#define PIC_TIMER2_COUNT 0x48
#define PIC_TIMER3_COUNT 0x4a
#define PIC_TIMER4_COUNT 0x4c
#define PIC_TIMER5_COUNT 0x4e
#define PIC_TIMER6_COUNT 0x50
#define PIC_TIMER7_COUNT 0x52
#define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2))
#define PIC_ITE0_N0_N1 0x54
#define PIC_ITE1_N0_N1 0x58
#define PIC_ITE2_N0_N1 0x5c
#define PIC_ITE3_N0_N1 0x60
#define PIC_ITE4_N0_N1 0x64
#define PIC_ITE5_N0_N1 0x68
#define PIC_ITE6_N0_N1 0x6c
#define PIC_ITE7_N0_N1 0x70
#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4))
#define PIC_ITE0_N2_N3 0x56
#define PIC_ITE1_N2_N3 0x5a
#define PIC_ITE2_N2_N3 0x5e
#define PIC_ITE3_N2_N3 0x62
#define PIC_ITE4_N2_N3 0x66
#define PIC_ITE5_N2_N3 0x6a
#define PIC_ITE6_N2_N3 0x6e
#define PIC_ITE7_N2_N3 0x72
#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4))
#define PIC_IRT0 0x74
#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2))
#define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL
/*
* IRT Map
*/
#define PIC_NUM_IRTS 160
#define PIC_IRT_WD_0_INDEX 0
#define PIC_IRT_WD_1_INDEX 1
#define PIC_IRT_WD_NMI_0_INDEX 2
#define PIC_IRT_WD_NMI_1_INDEX 3
#define PIC_IRT_TIMER_0_INDEX 4
#define PIC_IRT_TIMER_1_INDEX 5
#define PIC_IRT_TIMER_2_INDEX 6
#define PIC_IRT_TIMER_3_INDEX 7
#define PIC_IRT_TIMER_4_INDEX 8
#define PIC_IRT_TIMER_5_INDEX 9
#define PIC_IRT_TIMER_6_INDEX 10
#define PIC_IRT_TIMER_7_INDEX 11
#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
#define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX)
/* 11 and 12 */
#define PIC_NUM_MSG_Q_IRTS 32
#define PIC_IRT_MSG_Q0_INDEX 12
#define PIC_IRT_MSG_Q_INDEX(qid) ((qid) + PIC_IRT_MSG_Q0_INDEX)
/* 12 to 43 */
#define PIC_IRT_MSG_0_INDEX 44
#define PIC_IRT_MSG_1_INDEX 45
/* 44 and 45 */
#define PIC_NUM_PCIE_MSIX_IRTS 32
#define PIC_IRT_PCIE_MSIX_0_INDEX 46
#define PIC_IRT_PCIE_MSIX_INDEX(num) ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)
/* 46 to 77 */
#define PIC_NUM_PCIE_LINK_IRTS 4
#define PIC_IRT_PCIE_LINK_0_INDEX 78
#define PIC_IRT_PCIE_LINK_1_INDEX 79
#define PIC_IRT_PCIE_LINK_2_INDEX 80
#define PIC_IRT_PCIE_LINK_3_INDEX 81
#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
/* 78 to 81 */
#define PIC_NUM_NA_IRTS 32
/* 82 to 113 */
#define PIC_IRT_NA_0_INDEX 82
#define PIC_IRT_NA_INDEX(num) ((num) + PIC_IRT_NA_0_INDEX)
#define PIC_IRT_POE_INDEX 114
#define PIC_NUM_USB_IRTS 6
#define PIC_IRT_USB_0_INDEX 115
#define PIC_IRT_EHCI_0_INDEX 115
#define PIC_IRT_EHCI_1_INDEX 118
#define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX)
/* 115 to 120 */
#define PIC_IRT_GDX_INDEX 121
#define PIC_IRT_SEC_INDEX 122
#define PIC_IRT_RSA_INDEX 123
#define PIC_NUM_COMP_IRTS 4
#define PIC_IRT_COMP_0_INDEX 124
#define PIC_IRT_COMP_INDEX(num) ((num) + PIC_IRT_COMP_0_INDEX)
/* 124 to 127 */
#define PIC_IRT_GBU_INDEX 128
#define PIC_IRT_ICC_0_INDEX 129 /* ICC - Inter Chip Coherency */
#define PIC_IRT_ICC_1_INDEX 130
#define PIC_IRT_ICC_2_INDEX 131
#define PIC_IRT_CAM_INDEX 132
#define PIC_IRT_UART_0_INDEX 133
#define PIC_IRT_UART_1_INDEX 134
#define PIC_IRT_I2C_0_INDEX 135
#define PIC_IRT_I2C_1_INDEX 136
#define PIC_IRT_SYS_0_INDEX 137
#define PIC_IRT_SYS_1_INDEX 138
#define PIC_IRT_JTAG_INDEX 139
#define PIC_IRT_PIC_INDEX 140
#define PIC_IRT_NBU_INDEX 141
#define PIC_IRT_TCU_INDEX 142
#define PIC_IRT_GCU_INDEX 143 /* GBC - Global Coherency */
#define PIC_IRT_DMC_0_INDEX 144
#define PIC_IRT_DMC_1_INDEX 145
#define PIC_NUM_GPIO_IRTS 4
#define PIC_IRT_GPIO_0_INDEX 146
#define PIC_IRT_GPIO_INDEX(num) ((num) + PIC_IRT_GPIO_0_INDEX)
/* 146 to 149 */
#define PIC_IRT_NOR_INDEX 150
#define PIC_IRT_NAND_INDEX 151
#define PIC_IRT_SPI_INDEX 152
#define PIC_IRT_MMC_INDEX 153
#define PIC_CLOCK_TIMER 7
#define PIC_IRQ_BASE 8
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
#define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE)
#define PIC_IRT_LAST_IRQ 63
#define PIC_IRQ_IS_IRT(irq) ((irq) >= PIC_IRT_FIRST_IRQ)
/*
* Misc
*/
#define PIC_IRT_VALID 1
#define PIC_LOCAL_SCHEDULING 1
#define PIC_GLOBAL_SCHEDULING 0
#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
/* IRT and h/w interrupt routines */
static inline int
nlm_pic_read_irt(uint64_t base, int irt_index)
{
return nlm_read_pic_reg(base, PIC_IRT(irt_index));
}
static inline uint64_t
nlm_pic_read_control(uint64_t base)
{
return nlm_read_pic_reg(base, PIC_CTRL);
}
static inline void
nlm_pic_write_control(uint64_t base, uint64_t control)
{
nlm_write_pic_reg(base, PIC_CTRL, control);
}
static inline void
nlm_pic_update_control(uint64_t base, uint64_t control)
{
uint64_t val;
val = nlm_read_pic_reg(base, PIC_CTRL);
nlm_write_pic_reg(base, PIC_CTRL, control | val);
}
static inline void
nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
{
uint64_t val;
val = nlm_read_pic_reg(base, PIC_IRT(irt));
val |= cpu & 0xf;
if (cpu > 15)
val |= 1 << 16;
nlm_write_pic_reg(base, PIC_IRT(irt), val);
}
static inline void
nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
int sch, int vec, int dt, int db, int dte)
{
uint64_t val;
val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
((dt & 0x1) << 19) | ((db & 0x7) << 16) |
(dte & 0xffff);
nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
}
static inline void
nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
int sch, int vec, int cpu)
{
nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
(cpu >> 4), /* thread group */
1 << (cpu & 0xf)); /* thread mask */
}
static inline uint64_t
nlm_pic_read_timer(uint64_t base, int timer)
{
return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
}
static inline void
nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
{
nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
}
static inline void
nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
{
uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
int en;
en = (irq > 0);
nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
en, 0, 0, irq, cpu);
/* enable the timer */
pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
}
static inline void
nlm_pic_enable_irt(uint64_t base, int irt)
{
uint64_t reg;
reg = nlm_read_pic_reg(base, PIC_IRT(irt));
nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
}
static inline void
nlm_pic_disable_irt(uint64_t base, int irt)
{
uint32_t reg;
reg = nlm_read_pic_reg(base, PIC_IRT(irt));
nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));
}
static inline void
nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
{
uint64_t ipi;
int node, ncpu;
node = hwt / 32;
ncpu = hwt & 0x1f;
ipi = ((uint64_t)nmi << 31) | (irq << 20) | (node << 17) |
(1 << (ncpu & 0xf));
if (ncpu > 15)
ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */
nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
}
static inline void
nlm_pic_ack(uint64_t base, int irt_num)
{
nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
/* Ack the Status register for Watchdog & System timers */
if (irt_num < 12)
nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
}
static inline void
nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
{
nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, 0);
}
extern uint64_t nlm_pic_base;
int nlm_irq_to_irt(int irq);
int nlm_irt_to_irq(int irt);
#endif /* __ASSEMBLY__ */
#endif /* _NLM_HAL_PIC_H */

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/*
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
* reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the NetLogic
* license below:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __NLM_HAL_SYS_H__
#define __NLM_HAL_SYS_H__
/**
* @file_name sys.h
* @author Netlogic Microsystems
* @brief HAL for System configuration registers
*/
#define SYS_CHIP_RESET 0x00
#define SYS_POWER_ON_RESET_CFG 0x01
#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02
#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03
#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04
#define SYS_EFUSE_DEVICE_CFG3 0x05
#define SYS_EFUSE_DEVICE_CFG4 0x06
#define SYS_EFUSE_DEVICE_CFG5 0x07
#define SYS_EFUSE_DEVICE_CFG6 0x08
#define SYS_EFUSE_DEVICE_CFG7 0x09
#define SYS_PLL_CTRL 0x0a
#define SYS_CPU_RESET 0x0b
#define SYS_CPU_NONCOHERENT_MODE 0x0d
#define SYS_CORE_DFS_DIS_CTRL 0x0e
#define SYS_CORE_DFS_RST_CTRL 0x0f
#define SYS_CORE_DFS_BYP_CTRL 0x10
#define SYS_CORE_DFS_PHA_CTRL 0x11
#define SYS_CORE_DFS_DIV_INC_CTRL 0x12
#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13
#define SYS_CORE_DFS_DIV_VALUE 0x14
#define SYS_RESET 0x15
#define SYS_DFS_DIS_CTRL 0x16
#define SYS_DFS_RST_CTRL 0x17
#define SYS_DFS_BYP_CTRL 0x18
#define SYS_DFS_DIV_INC_CTRL 0x19
#define SYS_DFS_DIV_DEC_CTRL 0x1a
#define SYS_DFS_DIV_VALUE0 0x1b
#define SYS_DFS_DIV_VALUE1 0x1c
#define SYS_SENSE_AMP_DLY 0x1d
#define SYS_SOC_SENSE_AMP_DLY 0x1e
#define SYS_CTRL0 0x1f
#define SYS_CTRL1 0x20
#define SYS_TIMEOUT_BS1 0x21
#define SYS_BYTE_SWAP 0x22
#define SYS_VRM_VID 0x23
#define SYS_PWR_RAM_CMD 0x24
#define SYS_PWR_RAM_ADDR 0x25
#define SYS_PWR_RAM_DATA0 0x26
#define SYS_PWR_RAM_DATA1 0x27
#define SYS_PWR_RAM_DATA2 0x28
#define SYS_PWR_UCODE 0x29
#define SYS_CPU0_PWR_STATUS 0x2a
#define SYS_CPU1_PWR_STATUS 0x2b
#define SYS_CPU2_PWR_STATUS 0x2c
#define SYS_CPU3_PWR_STATUS 0x2d
#define SYS_CPU4_PWR_STATUS 0x2e
#define SYS_CPU5_PWR_STATUS 0x2f
#define SYS_CPU6_PWR_STATUS 0x30
#define SYS_CPU7_PWR_STATUS 0x31
#define SYS_STATUS 0x32
#define SYS_INT_POL 0x33
#define SYS_INT_TYPE 0x34
#define SYS_INT_STATUS 0x35
#define SYS_INT_MASK0 0x36
#define SYS_INT_MASK1 0x37
#define SYS_UCO_S_ECC 0x38
#define SYS_UCO_M_ECC 0x39
#define SYS_UCO_ADDR 0x3a
#define SYS_UCO_INSTR 0x3b
#define SYS_MEM_BIST0 0x3c
#define SYS_MEM_BIST1 0x3d
#define SYS_MEM_BIST2 0x3e
#define SYS_MEM_BIST3 0x3f
#define SYS_MEM_BIST4 0x40
#define SYS_MEM_BIST5 0x41
#define SYS_MEM_BIST6 0x42
#define SYS_MEM_BIST7 0x43
#define SYS_MEM_BIST8 0x44
#define SYS_MEM_BIST9 0x45
#define SYS_MEM_BIST10 0x46
#define SYS_MEM_BIST11 0x47
#define SYS_MEM_BIST12 0x48
#define SYS_SCRTCH0 0x49
#define SYS_SCRTCH1 0x4a
#define SYS_SCRTCH2 0x4b
#define SYS_SCRTCH3 0x4c
#ifndef __ASSEMBLY__
#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v)
#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
extern uint64_t nlm_sys_base;
#endif
#endif

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/*
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
* reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the NetLogic
* license below:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __XLP_HAL_UART_H__
#define __XLP_HAL_UART_H__
/* UART Specific registers */
#define UART_RX_DATA 0x00
#define UART_TX_DATA 0x00
#define UART_INT_EN 0x01
#define UART_INT_ID 0x02
#define UART_FIFO_CTL 0x02
#define UART_LINE_CTL 0x03
#define UART_MODEM_CTL 0x04
#define UART_LINE_STS 0x05
#define UART_MODEM_STS 0x06
#define UART_DIVISOR0 0x00
#define UART_DIVISOR1 0x01
#define BASE_BAUD (XLP_IO_CLK/16)
#define BAUD_DIVISOR(baud) (BASE_BAUD / baud)
/* LCR mask values */
#define LCR_5BITS 0x00
#define LCR_6BITS 0x01
#define LCR_7BITS 0x02
#define LCR_8BITS 0x03
#define LCR_STOPB 0x04
#define LCR_PENAB 0x08
#define LCR_PODD 0x00
#define LCR_PEVEN 0x10
#define LCR_PONE 0x20
#define LCR_PZERO 0x30
#define LCR_SBREAK 0x40
#define LCR_EFR_ENABLE 0xbf
#define LCR_DLAB 0x80
/* MCR mask values */
#define MCR_DTR 0x01
#define MCR_RTS 0x02
#define MCR_DRS 0x04
#define MCR_IE 0x08
#define MCR_LOOPBACK 0x10
/* FCR mask values */
#define FCR_RCV_RST 0x02
#define FCR_XMT_RST 0x04
#define FCR_RX_LOW 0x00
#define FCR_RX_MEDL 0x40
#define FCR_RX_MEDH 0x80
#define FCR_RX_HIGH 0xc0
/* IER mask values */
#define IER_ERXRDY 0x1
#define IER_ETXRDY 0x2
#define IER_ERLS 0x4
#define IER_EMSC 0x8
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
#define nlm_get_uart_pcibase(node, inst) \
nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
#define nlm_get_uart_regbase(node, inst) \
(nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
static inline void
nlm_uart_set_baudrate(uint64_t base, int baud)
{
uint32_t lcr;
lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
/* enable divisor register, and write baud values */
nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
nlm_write_uart_reg(base, UART_DIVISOR0,
(BAUD_DIVISOR(baud) & 0xff));
nlm_write_uart_reg(base, UART_DIVISOR1,
((BAUD_DIVISOR(baud) >> 8) & 0xff));
/* restore default lcr */
nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
}
static inline void
nlm_uart_outbyte(uint64_t base, char c)
{
uint32_t lsr;
for (;;) {
lsr = nlm_read_uart_reg(base, UART_LINE_STS);
if (lsr & 0x20)
break;
}
nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
}
static inline char
nlm_uart_inbyte(uint64_t base)
{
int data, lsr;
for (;;) {
lsr = nlm_read_uart_reg(base, UART_LINE_STS);
if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
data = 0;
break;
}
if (lsr & 0x01) { /* Rx data */
data = nlm_read_uart_reg(base, UART_RX_DATA);
break;
}
}
return (char)data;
}
static inline int
nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
int parity, int int_en, int loopback)
{
uint32_t lcr;
lcr = 0;
if (databits >= 8)
lcr |= LCR_8BITS;
else if (databits == 7)
lcr |= LCR_7BITS;
else if (databits == 6)
lcr |= LCR_6BITS;
else
lcr |= LCR_5BITS;
if (stopbits > 1)
lcr |= LCR_STOPB;
lcr |= parity << 3;
/* setup default lcr */
nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
/* Reset the FIFOs */
nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
nlm_uart_set_baudrate(base, baud);
if (loopback)
nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
if (int_en)
nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
return 0;
}
#endif /* !LOCORE && !__ASSEMBLY__ */
#endif /* __XLP_HAL_UART_H__ */

25
arch/mips/netlogic/xlr/xlr_console.c → arch/mips/include/asm/netlogic/xlp-hal/xlp.h
View File

@ -32,15 +32,20 @@
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <linux/types.h>
#include <asm/netlogic/xlr/iomap.h>
#ifndef _NLM_HAL_XLP_H
#define _NLM_HAL_XLP_H
void prom_putchar(char c)
{
nlm_reg_t *mmio;
#define PIC_UART_0_IRQ 17
#define PIC_UART_1_IRQ 18
mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
while (netlogic_read_reg(mmio, 0x5) == 0)
;
netlogic_write_reg(mmio, 0x0, c);
}
#ifndef __ASSEMBLY__
/* SMP support functions */
void xlp_boot_core0_siblings(void);
void xlp_wakeup_secondary_cpus(void);
void xlp_mmu_init(void);
void nlm_hal_init(void);
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_NLM_XLP_H */

22
arch/mips/include/asm/netlogic/xlr/iomap.h
View File

@ -106,26 +106,4 @@
#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000
#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000
#ifndef __ASSEMBLY__
#include <linux/types.h>
#include <asm/byteorder.h>
typedef volatile __u32 nlm_reg_t;
extern unsigned long netlogic_io_base;
/* FIXME read once in write_reg */
#ifdef CONFIG_CPU_LITTLE_ENDIAN
#define netlogic_read_reg(base, offset) ((base)[(offset)])
#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value))
#else
#define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)]))
#define netlogic_write_reg(base, offset, value) \
((base)[(offset)] = cpu_to_be32((value)))
#endif
#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)]))
#define netlogic_write_reg_le32(base, offset, value) \
((base)[(offset)] = cpu_to_le32((value)))
#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset)))
#endif /* __ASSEMBLY__ */
#endif

84
arch/mips/include/asm/netlogic/xlr/msidef.h Normal file
View File

@ -0,0 +1,84 @@
/*
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
* reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the NetLogic
* license below:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef ASM_RMI_MSIDEF_H
#define ASM_RMI_MSIDEF_H
/*
* Constants for Intel APIC based MSI messages.
* Adapted for the RMI XLR using identical defines
*/
/*
* Shifts for MSI data
*/
#define MSI_DATA_VECTOR_SHIFT 0
#define MSI_DATA_VECTOR_MASK 0x000000ff
#define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & \
MSI_DATA_VECTOR_MASK)
#define MSI_DATA_DELIVERY_MODE_SHIFT 8
#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
#define MSI_DATA_LEVEL_SHIFT 14
#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
#define MSI_DATA_TRIGGER_SHIFT 15
#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
/*
* Shift/mask fields for msi address
*/
#define MSI_ADDR_BASE_HI 0
#define MSI_ADDR_BASE_LO 0xfee00000
#define MSI_ADDR_DEST_MODE_SHIFT 2
#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT)
#define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT)
#define MSI_ADDR_REDIRECTION_SHIFT 3
#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT)
#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT)
#define MSI_ADDR_DEST_ID_SHIFT 12
#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \
MSI_ADDR_DEST_ID_MASK)
#endif /* ASM_RMI_MSIDEF_H */

91
arch/mips/include/asm/netlogic/xlr/pic.h
View File

@ -193,39 +193,72 @@
/* end XLS */
#ifndef __ASSEMBLY__
static inline void pic_send_ipi(u32 ipi)
{
nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
netlogic_write_reg(mmio, PIC_IPI, ipi);
}
static inline u32 pic_read_control(void)
{
nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
return netlogic_read_reg(mmio, PIC_CTRL);
}
static inline void pic_write_control(u32 control)
{
nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
netlogic_write_reg(mmio, PIC_CTRL, control);
}
static inline void pic_update_control(u32 control)
{
nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
netlogic_write_reg(mmio, PIC_CTRL,
(control | netlogic_read_reg(mmio, PIC_CTRL)));
}
#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \
((irq) <= PIC_TIMER_7_IRQ))
#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \
((irq) <= PIC_IRT_LAST_IRQ))
#endif
static inline int
nlm_irq_to_irt(int irq)
{
if (PIC_IRQ_IS_IRT(irq) == 0)
return -1;
return PIC_IRQ_TO_INTR(irq);
}
static inline int
nlm_irt_to_irq(int irt)
{
return PIC_INTR_TO_IRQ(irt);
}
static inline void
nlm_pic_enable_irt(uint64_t base, int irt)
{
uint32_t reg;
reg = nlm_read_reg(base, PIC_IRT_1(irt));
nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31));
}
static inline void
nlm_pic_disable_irt(uint64_t base, int irt)
{
uint32_t reg;
reg = nlm_read_reg(base, PIC_IRT_1(irt));
nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31));
}
static inline void
nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
{
unsigned int tid, pid;
tid = hwt & 0x3;
pid = (hwt >> 2) & 0x07;
nlm_write_reg(base, PIC_IPI,
(pid << 20) | (tid << 16) | (nmi << 8) | irq);
}
static inline void
nlm_pic_ack(uint64_t base, int irt)
{
nlm_write_reg(base, PIC_INT_ACK, 1u << irt);
}
static inline void
nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
{
nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
/* local scheduling, invalid, level by default */
nlm_write_reg(base, PIC_IRT_1(irt),
(1 << 30) | (1 << 6) | irq);
}
extern uint64_t nlm_pic_base;
#endif
#endif /* _ASM_NLM_XLR_PIC_H */

13
arch/mips/include/asm/netlogic/xlr/xlr.h
View File

@ -40,17 +40,8 @@ struct uart_port;
unsigned int nlm_xlr_uart_in(struct uart_port *, int);
void nlm_xlr_uart_out(struct uart_port *, int, int);
/* SMP support functions */
struct irq_desc;
void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
void nlm_smp_irq_init(void);
void nlm_boot_smp_nmi(void);
void prom_pre_boot_secondary_cpus(void);
extern struct plat_smp_ops nlm_smp_ops;
extern unsigned long nlm_common_ebase;
/* SMP helpers */
void xlr_wakeup_secondary_cpus(void);
/* XLS B silicon "Rook" */
static inline unsigned int nlm_chip_is_xls_b(void)

0
drivers/staging/octeon/cvmx-address.h → arch/mips/include/asm/octeon/cvmx-address.h
View File

0
drivers/staging/octeon/cvmx-asxx-defs.h → arch/mips/include/asm/octeon/cvmx-asxx-defs.h
View File

82
arch/mips/include/asm/octeon/cvmx-bootinfo.h
View File

@ -39,7 +39,7 @@
* versions.
*/
#define CVMX_BOOTINFO_MAJ_VER 1
#define CVMX_BOOTINFO_MIN_VER 2
#define CVMX_BOOTINFO_MIN_VER 3
#if (CVMX_BOOTINFO_MAJ_VER == 1)
#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20
@ -116,7 +116,13 @@ struct cvmx_bootinfo {
*/
uint32_t config_flags;
#endif
#if (CVMX_BOOTINFO_MIN_VER >= 3)
/*
* Address of the OF Flattened Device Tree structure
* describing the board.
*/
uint64_t fdt_addr;
#endif
};
#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0)
@ -164,6 +170,22 @@ enum cvmx_board_types_enum {
/* Special 'generic' board type, supports many boards */
CVMX_BOARD_TYPE_GENERIC = 28,
CVMX_BOARD_TYPE_EBH5610 = 29,
CVMX_BOARD_TYPE_LANAI2_A = 30,
CVMX_BOARD_TYPE_LANAI2_U = 31,
CVMX_BOARD_TYPE_EBB5600 = 32,
CVMX_BOARD_TYPE_EBB6300 = 33,
CVMX_BOARD_TYPE_NIC_XLE_10G = 34,
CVMX_BOARD_TYPE_LANAI2_G = 35,
CVMX_BOARD_TYPE_EBT5810 = 36,
CVMX_BOARD_TYPE_NIC10E = 37,
CVMX_BOARD_TYPE_EP6300C = 38,
CVMX_BOARD_TYPE_EBB6800 = 39,
CVMX_BOARD_TYPE_NIC4E = 40,
CVMX_BOARD_TYPE_NIC2E = 41,
CVMX_BOARD_TYPE_EBB6600 = 42,
CVMX_BOARD_TYPE_REDWING = 43,
CVMX_BOARD_TYPE_NIC68_4 = 44,
CVMX_BOARD_TYPE_NIC10E_66 = 45,
CVMX_BOARD_TYPE_MAX,
/*
@ -181,6 +203,23 @@ enum cvmx_board_types_enum {
CVMX_BOARD_TYPE_CUST_NS0216 = 10002,
CVMX_BOARD_TYPE_CUST_NB5 = 10003,
CVMX_BOARD_TYPE_CUST_WMR500 = 10004,
CVMX_BOARD_TYPE_CUST_ITB101 = 10005,
CVMX_BOARD_TYPE_CUST_NTE102 = 10006,
CVMX_BOARD_TYPE_CUST_AGS103 = 10007,
CVMX_BOARD_TYPE_CUST_GST104 = 10008,
CVMX_BOARD_TYPE_CUST_GCT105 = 10009,
CVMX_BOARD_TYPE_CUST_AGS106 = 10010,
CVMX_BOARD_TYPE_CUST_SGM107 = 10011,
CVMX_BOARD_TYPE_CUST_GCT108 = 10012,
CVMX_BOARD_TYPE_CUST_AGS109 = 10013,
CVMX_BOARD_TYPE_CUST_GCT110 = 10014,
CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER = 10015,
CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER = 10016,
CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX = 10017,
CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX = 10018,
CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX = 10019,
CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX = 10020,
CVMX_BOARD_TYPE_CUST_L2_ZINWELL = 10021,
CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
/*
@ -241,6 +280,22 @@ static inline const char *cvmx_board_type_to_string(enum
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_A)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_U)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB5600)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6300)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_10G)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EP6300C)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6800)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC4E)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC2E)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6600)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
/* Customer boards listed here */
@ -249,6 +304,23 @@ static inline const char *cvmx_board_type_to_string(enum
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_ITB101)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NTE102)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS103)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GST104)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT105)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS106)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_SGM107)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT108)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS109)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT110)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ZINWELL)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX)
/* Customer private range */
@ -265,9 +337,9 @@ static inline const char *cvmx_chip_type_to_string(enum
{
switch (type) {
ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL)
ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
}
return "Unsupported Chip";
}

0
drivers/staging/octeon/cvmx-cmd-queue.h → arch/mips/include/asm/octeon/cvmx-cmd-queue.h
View File

1
drivers/staging/octeon/cvmx-config.h → arch/mips/include/asm/octeon/cvmx-config.h
View File

@ -166,4 +166,3 @@ typedef enum {
#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0
#endif /* __CVMX_CONFIG_H__ */

0
drivers/staging/octeon/cvmx-dbg-defs.h → arch/mips/include/asm/octeon/cvmx-dbg-defs.h
View File

643
arch/mips/include/asm/octeon/cvmx-dpi-defs.h Normal file
View File

@ -0,0 +1,643 @@
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2011 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
#ifndef __CVMX_DPI_DEFS_H__
#define __CVMX_DPI_DEFS_H__
#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
union cvmx_dpi_bist_status {
uint64_t u64;
struct cvmx_dpi_bist_status_s {
uint64_t reserved_47_63:17;
uint64_t bist:47;
} s;
struct cvmx_dpi_bist_status_s cn61xx;
struct cvmx_dpi_bist_status_cn63xx {
uint64_t reserved_45_63:19;
uint64_t bist:45;
} cn63xx;
struct cvmx_dpi_bist_status_cn63xxp1 {
uint64_t reserved_37_63:27;
uint64_t bist:37;
} cn63xxp1;
struct cvmx_dpi_bist_status_s cn66xx;
struct cvmx_dpi_bist_status_cn63xx cn68xx;
struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
};
union cvmx_dpi_ctl {
uint64_t u64;
struct cvmx_dpi_ctl_s {
uint64_t reserved_2_63:62;
uint64_t clk:1;
uint64_t en:1;
} s;
struct cvmx_dpi_ctl_cn61xx {
uint64_t reserved_1_63:63;
uint64_t en:1;
} cn61xx;
struct cvmx_dpi_ctl_s cn63xx;
struct cvmx_dpi_ctl_s cn63xxp1;
struct cvmx_dpi_ctl_s cn66xx;
struct cvmx_dpi_ctl_s cn68xx;
struct cvmx_dpi_ctl_s cn68xxp1;
};
union cvmx_dpi_dmax_counts {
uint64_t u64;
struct cvmx_dpi_dmax_counts_s {
uint64_t reserved_39_63:25;
uint64_t fcnt:7;
uint64_t dbell:32;
} s;
struct cvmx_dpi_dmax_counts_s cn61xx;
struct cvmx_dpi_dmax_counts_s cn63xx;
struct cvmx_dpi_dmax_counts_s cn63xxp1;
struct cvmx_dpi_dmax_counts_s cn66xx;
struct cvmx_dpi_dmax_counts_s cn68xx;
struct cvmx_dpi_dmax_counts_s cn68xxp1;
};
union cvmx_dpi_dmax_dbell {
uint64_t u64;
struct cvmx_dpi_dmax_dbell_s {
uint64_t reserved_16_63:48;
uint64_t dbell:16;
} s;
struct cvmx_dpi_dmax_dbell_s cn61xx;
struct cvmx_dpi_dmax_dbell_s cn63xx;
struct cvmx_dpi_dmax_dbell_s cn63xxp1;
struct cvmx_dpi_dmax_dbell_s cn66xx;
struct cvmx_dpi_dmax_dbell_s cn68xx;
struct cvmx_dpi_dmax_dbell_s cn68xxp1;
};
union cvmx_dpi_dmax_err_rsp_status {
uint64_t u64;
struct cvmx_dpi_dmax_err_rsp_status_s {
uint64_t reserved_6_63:58;
uint64_t status:6;
} s;
struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
};
union cvmx_dpi_dmax_ibuff_saddr {
uint64_t u64;
struct cvmx_dpi_dmax_ibuff_saddr_s {
uint64_t reserved_62_63:2;
uint64_t csize:14;
uint64_t reserved_41_47:7;
uint64_t idle:1;
uint64_t saddr:33;
uint64_t reserved_0_6:7;
} s;
struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
uint64_t reserved_62_63:2;
uint64_t csize:14;
uint64_t reserved_41_47:7;
uint64_t idle:1;
uint64_t reserved_36_39:4;
uint64_t saddr:29;
uint64_t reserved_0_6:7;
} cn61xx;
struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
};
union cvmx_dpi_dmax_iflight {
uint64_t u64;
struct cvmx_dpi_dmax_iflight_s {
uint64_t reserved_3_63:61;
uint64_t cnt:3;
} s;
struct cvmx_dpi_dmax_iflight_s cn61xx;
struct cvmx_dpi_dmax_iflight_s cn66xx;
struct cvmx_dpi_dmax_iflight_s cn68xx;
struct cvmx_dpi_dmax_iflight_s cn68xxp1;
};
union cvmx_dpi_dmax_naddr {
uint64_t u64;
struct cvmx_dpi_dmax_naddr_s {
uint64_t reserved_40_63:24;
uint64_t addr:40;
} s;
struct cvmx_dpi_dmax_naddr_cn61xx {
uint64_t reserved_36_63:28;
uint64_t addr:36;
} cn61xx;
struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
struct cvmx_dpi_dmax_naddr_s cn68xx;
struct cvmx_dpi_dmax_naddr_s cn68xxp1;
};
union cvmx_dpi_dmax_reqbnk0 {
uint64_t u64;
struct cvmx_dpi_dmax_reqbnk0_s {
uint64_t state:64;
} s;
struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1;
struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
};
union cvmx_dpi_dmax_reqbnk1 {
uint64_t u64;
struct cvmx_dpi_dmax_reqbnk1_s {
uint64_t state:64;
} s;
struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1;
struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
};
union cvmx_dpi_dma_control {
uint64_t u64;
struct cvmx_dpi_dma_control_s {
uint64_t reserved_62_63:2;
uint64_t dici_mode:1;
uint64_t pkt_en1:1;
uint64_t ffp_dis:1;
uint64_t commit_mode:1;
uint64_t pkt_hp:1;
uint64_t pkt_en:1;
uint64_t reserved_54_55:2;
uint64_t dma_enb:6;
uint64_t reserved_34_47:14;
uint64_t b0_lend:1;
uint64_t dwb_denb:1;
uint64_t dwb_ichk:9;
uint64_t fpa_que:3;
uint64_t o_add1:1;
uint64_t o_ro:1;
uint64_t o_ns:1;
uint64_t o_es:2;
uint64_t o_mode:1;
uint64_t reserved_0_13:14;
} s;
struct cvmx_dpi_dma_control_s cn61xx;
struct cvmx_dpi_dma_control_cn63xx {
uint64_t reserved_61_63:3;
uint64_t pkt_en1:1;
uint64_t ffp_dis:1;
uint64_t commit_mode:1;
uint64_t pkt_hp:1;
uint64_t pkt_en:1;
uint64_t reserved_54_55:2;
uint64_t dma_enb:6;
uint64_t reserved_34_47:14;
uint64_t b0_lend:1;
uint64_t dwb_denb:1;
uint64_t dwb_ichk:9;
uint64_t fpa_que:3;
uint64_t o_add1:1;
uint64_t o_ro:1;
uint64_t o_ns:1;
uint64_t o_es:2;
uint64_t o_mode:1;
uint64_t reserved_0_13:14;
} cn63xx;
struct cvmx_dpi_dma_control_cn63xxp1 {
uint64_t reserved_59_63:5;
uint64_t commit_mode:1;
uint64_t pkt_hp:1;
uint64_t pkt_en:1;
uint64_t reserved_54_55:2;
uint64_t dma_enb:6;
uint64_t reserved_34_47:14;
uint64_t b0_lend:1;
uint64_t dwb_denb:1;
uint64_t dwb_ichk:9;
uint64_t fpa_que:3;
uint64_t o_add1:1;
uint64_t o_ro:1;
uint64_t o_ns:1;
uint64_t o_es:2;
uint64_t o_mode:1;
uint64_t reserved_0_13:14;
} cn63xxp1;
struct cvmx_dpi_dma_control_cn63xx cn66xx;
struct cvmx_dpi_dma_control_s cn68xx;
struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
};
union cvmx_dpi_dma_engx_en {
uint64_t u64;
struct cvmx_dpi_dma_engx_en_s {
uint64_t reserved_8_63:56;
uint64_t qen:8;
} s;
struct cvmx_dpi_dma_engx_en_s cn61xx;
struct cvmx_dpi_dma_engx_en_s cn63xx;
struct cvmx_dpi_dma_engx_en_s cn63xxp1;
struct cvmx_dpi_dma_engx_en_s cn66xx;
struct cvmx_dpi_dma_engx_en_s cn68xx;
struct cvmx_dpi_dma_engx_en_s cn68xxp1;
};
union cvmx_dpi_dma_ppx_cnt {
uint64_t u64;
struct cvmx_dpi_dma_ppx_cnt_s {
uint64_t reserved_16_63:48;
uint64_t cnt:16;
} s;
struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
};
union cvmx_dpi_engx_buf {
uint64_t u64;
struct cvmx_dpi_engx_buf_s {
uint64_t reserved_37_63:27;
uint64_t compblks:5;
uint64_t reserved_9_31:23;
uint64_t base:5;
uint64_t blks:4;
} s;
struct cvmx_dpi_engx_buf_s cn61xx;
struct cvmx_dpi_engx_buf_cn63xx {
uint64_t reserved_8_63:56;
uint64_t base:4;
uint64_t blks:4;
} cn63xx;
struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
struct cvmx_dpi_engx_buf_s cn66xx;
struct cvmx_dpi_engx_buf_s cn68xx;
struct cvmx_dpi_engx_buf_s cn68xxp1;
};
union cvmx_dpi_info_reg {
uint64_t u64;
struct cvmx_dpi_info_reg_s {
uint64_t reserved_8_63:56;
uint64_t ffp:4;
uint64_t reserved_2_3:2;
uint64_t ncb:1;
uint64_t rsl:1;
} s;
struct cvmx_dpi_info_reg_s cn61xx;
struct cvmx_dpi_info_reg_s cn63xx;
struct cvmx_dpi_info_reg_cn63xxp1 {
uint64_t reserved_2_63:62;
uint64_t ncb:1;
uint64_t rsl:1;
} cn63xxp1;
struct cvmx_dpi_info_reg_s cn66xx;
struct cvmx_dpi_info_reg_s cn68xx;
struct cvmx_dpi_info_reg_s cn68xxp1;
};
union cvmx_dpi_int_en {
uint64_t u64;
struct cvmx_dpi_int_en_s {
uint64_t reserved_28_63:36;
uint64_t sprt3_rst:1;
uint64_t sprt2_rst:1;
uint64_t sprt1_rst:1;
uint64_t sprt0_rst:1;
uint64_t reserved_23_23:1;
uint64_t req_badfil:1;
uint64_t req_inull:1;
uint64_t req_anull:1;
uint64_t req_undflw:1;
uint64_t req_ovrflw:1;
uint64_t req_badlen:1;
uint64_t req_badadr:1;
uint64_t dmadbo:8;
uint64_t reserved_2_7:6;
uint64_t nfovr:1;
uint64_t nderr:1;
} s;
struct cvmx_dpi_int_en_s cn61xx;
struct cvmx_dpi_int_en_cn63xx {
uint64_t reserved_26_63:38;
uint64_t sprt1_rst:1;
uint64_t sprt0_rst:1;
uint64_t reserved_23_23:1;
uint64_t req_badfil:1;
uint64_t req_inull:1;
uint64_t req_anull:1;
uint64_t req_undflw:1;
uint64_t req_ovrflw:1;
uint64_t req_badlen:1;
uint64_t req_badadr:1;
uint64_t dmadbo:8;
uint64_t reserved_2_7:6;
uint64_t nfovr:1;
uint64_t nderr:1;
} cn63xx;
struct cvmx_dpi_int_en_cn63xx cn63xxp1;
struct cvmx_dpi_int_en_s cn66xx;
struct cvmx_dpi_int_en_cn63xx cn68xx;
struct cvmx_dpi_int_en_cn63xx cn68xxp1;
};
union cvmx_dpi_int_reg {
uint64_t u64;
struct cvmx_dpi_int_reg_s {
uint64_t reserved_28_63:36;
uint64_t sprt3_rst:1;
uint64_t sprt2_rst:1;
uint64_t sprt1_rst:1;
uint64_t sprt0_rst:1;
uint64_t reserved_23_23:1;
uint64_t req_badfil:1;
uint64_t req_inull:1;
uint64_t req_anull:1;
uint64_t req_undflw:1;
uint64_t req_ovrflw:1;
uint64_t req_badlen:1;
uint64_t req_badadr:1;
uint64_t dmadbo:8;
uint64_t reserved_2_7:6;
uint64_t nfovr:1;
uint64_t nderr:1;
} s;
struct cvmx_dpi_int_reg_s cn61xx;
struct cvmx_dpi_int_reg_cn63xx {
uint64_t reserved_26_63:38;
uint64_t sprt1_rst:1;
uint64_t sprt0_rst:1;
uint64_t reserved_23_23:1;
uint64_t req_badfil:1;
uint64_t req_inull:1;
uint64_t req_anull:1;
uint64_t req_undflw:1;
uint64_t req_ovrflw:1;
uint64_t req_badlen:1;
uint64_t req_badadr:1;
uint64_t dmadbo:8;
uint64_t reserved_2_7:6;
uint64_t nfovr:1;
uint64_t nderr:1;
} cn63xx;
struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
struct cvmx_dpi_int_reg_s cn66xx;
struct cvmx_dpi_int_reg_cn63xx cn68xx;
struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
};
union cvmx_dpi_ncbx_cfg {
uint64_t u64;
struct cvmx_dpi_ncbx_cfg_s {
uint64_t reserved_6_63:58;
uint64_t molr:6;
} s;
struct cvmx_dpi_ncbx_cfg_s cn61xx;
struct cvmx_dpi_ncbx_cfg_s cn66xx;
struct cvmx_dpi_ncbx_cfg_s cn68xx;
};
union cvmx_dpi_pint_info {
uint64_t u64;
struct cvmx_dpi_pint_info_s {
uint64_t reserved_14_63:50;
uint64_t iinfo:6;
uint64_t reserved_6_7:2;
uint64_t sinfo:6;
} s;
struct cvmx_dpi_pint_info_s cn61xx;
struct cvmx_dpi_pint_info_s cn63xx;
struct cvmx_dpi_pint_info_s cn63xxp1;
struct cvmx_dpi_pint_info_s cn66xx;
struct cvmx_dpi_pint_info_s cn68xx;
struct cvmx_dpi_pint_info_s cn68xxp1;
};
union cvmx_dpi_pkt_err_rsp {
uint64_t u64;
struct cvmx_dpi_pkt_err_rsp_s {
uint64_t reserved_1_63:63;
uint64_t pkterr:1;
} s;
struct cvmx_dpi_pkt_err_rsp_s cn61xx;
struct cvmx_dpi_pkt_err_rsp_s cn63xx;
struct cvmx_dpi_pkt_err_rsp_s cn63xxp1;
struct cvmx_dpi_pkt_err_rsp_s cn66xx;
struct cvmx_dpi_pkt_err_rsp_s cn68xx;
struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
};
union cvmx_dpi_req_err_rsp {
uint64_t u64;
struct cvmx_dpi_req_err_rsp_s {
uint64_t reserved_8_63:56;
uint64_t qerr:8;
} s;
struct cvmx_dpi_req_err_rsp_s cn61xx;
struct cvmx_dpi_req_err_rsp_s cn63xx;
struct cvmx_dpi_req_err_rsp_s cn63xxp1;
struct cvmx_dpi_req_err_rsp_s cn66xx;
struct cvmx_dpi_req_err_rsp_s cn68xx;
struct cvmx_dpi_req_err_rsp_s cn68xxp1;
};
union cvmx_dpi_req_err_rsp_en {
uint64_t u64;
struct cvmx_dpi_req_err_rsp_en_s {
uint64_t reserved_8_63:56;
uint64_t en:8;
} s;
struct cvmx_dpi_req_err_rsp_en_s cn61xx;
struct cvmx_dpi_req_err_rsp_en_s cn63xx;
struct cvmx_dpi_req_err_rsp_en_s cn63xxp1;
struct cvmx_dpi_req_err_rsp_en_s cn66xx;
struct cvmx_dpi_req_err_rsp_en_s cn68xx;
struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
};
union cvmx_dpi_req_err_rst {
uint64_t u64;
struct cvmx_dpi_req_err_rst_s {
uint64_t reserved_8_63:56;
uint64_t qerr:8;
} s;
struct cvmx_dpi_req_err_rst_s cn61xx;
struct cvmx_dpi_req_err_rst_s cn63xx;
struct cvmx_dpi_req_err_rst_s cn63xxp1;
struct cvmx_dpi_req_err_rst_s cn66xx;
struct cvmx_dpi_req_err_rst_s cn68xx;
struct cvmx_dpi_req_err_rst_s cn68xxp1;
};
union cvmx_dpi_req_err_rst_en {
uint64_t u64;
struct cvmx_dpi_req_err_rst_en_s {
uint64_t reserved_8_63:56;
uint64_t en:8;
} s;
struct cvmx_dpi_req_err_rst_en_s cn61xx;
struct cvmx_dpi_req_err_rst_en_s cn63xx;
struct cvmx_dpi_req_err_rst_en_s cn63xxp1;
struct cvmx_dpi_req_err_rst_en_s cn66xx;
struct cvmx_dpi_req_err_rst_en_s cn68xx;
struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
};
union cvmx_dpi_req_err_skip_comp {
uint64_t u64;
struct cvmx_dpi_req_err_skip_comp_s {
uint64_t reserved_24_63:40;
uint64_t en_rst:8;
uint64_t reserved_8_15:8;
uint64_t en_rsp:8;
} s;
struct cvmx_dpi_req_err_skip_comp_s cn61xx;
struct cvmx_dpi_req_err_skip_comp_s cn66xx;
struct cvmx_dpi_req_err_skip_comp_s cn68xx;
struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
};
union cvmx_dpi_req_gbl_en {
uint64_t u64;
struct cvmx_dpi_req_gbl_en_s {
uint64_t reserved_8_63:56;
uint64_t qen:8;
} s;
struct cvmx_dpi_req_gbl_en_s cn61xx;
struct cvmx_dpi_req_gbl_en_s cn63xx;
struct cvmx_dpi_req_gbl_en_s cn63xxp1;
struct cvmx_dpi_req_gbl_en_s cn66xx;
struct cvmx_dpi_req_gbl_en_s cn68xx;
struct cvmx_dpi_req_gbl_en_s cn68xxp1;
};
union cvmx_dpi_sli_prtx_cfg {
uint64_t u64;
struct cvmx_dpi_sli_prtx_cfg_s {
uint64_t reserved_25_63:39;
uint64_t halt:1;
uint64_t qlm_cfg:4;
uint64_t reserved_17_19:3;
uint64_t rd_mode:1;
uint64_t reserved_14_15:2;
uint64_t molr:6;
uint64_t mps_lim:1;
uint64_t reserved_5_6:2;
uint64_t mps:1;
uint64_t mrrs_lim:1;
uint64_t reserved_2_2:1;
uint64_t mrrs:2;
} s;
struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
struct cvmx_dpi_sli_prtx_cfg_cn63xx {
uint64_t reserved_25_63:39;
uint64_t halt:1;
uint64_t reserved_21_23:3;
uint64_t qlm_cfg:1;
uint64_t reserved_17_19:3;
uint64_t rd_mode:1;
uint64_t reserved_14_15:2;
uint64_t molr:6;
uint64_t mps_lim:1;
uint64_t reserved_5_6:2;
uint64_t mps:1;
uint64_t mrrs_lim:1;
uint64_t reserved_2_2:1;
uint64_t mrrs:2;
} cn63xx;
struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
};
union cvmx_dpi_sli_prtx_err {
uint64_t u64;
struct cvmx_dpi_sli_prtx_err_s {
uint64_t addr:61;
uint64_t reserved_0_2:3;
} s;
struct cvmx_dpi_sli_prtx_err_s cn61xx;
struct cvmx_dpi_sli_prtx_err_s cn63xx;
struct cvmx_dpi_sli_prtx_err_s cn63xxp1;
struct cvmx_dpi_sli_prtx_err_s cn66xx;
struct cvmx_dpi_sli_prtx_err_s cn68xx;
struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
};
union cvmx_dpi_sli_prtx_err_info {
uint64_t u64;
struct cvmx_dpi_sli_prtx_err_info_s {
uint64_t reserved_9_63:55;
uint64_t lock:1;
uint64_t reserved_5_7:3;
uint64_t type:1;
uint64_t reserved_3_3:1;
uint64_t reqq:3;
} s;
struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1;
struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
};
#endif

0
drivers/staging/octeon/cvmx-fau.h → arch/mips/include/asm/octeon/cvmx-fau.h
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0
drivers/staging/octeon/cvmx-fpa-defs.h → arch/mips/include/asm/octeon/cvmx-fpa-defs.h
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0
drivers/staging/octeon/cvmx-fpa.h → arch/mips/include/asm/octeon/cvmx-fpa.h
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0
drivers/staging/octeon/cvmx-gmxx-defs.h → arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
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