thunderbolt: Add downstream PCIe port mappings for Alpine and Titan Ridge
In order to keep PCIe hierarchies consistent across hotplugs, add hard-coded PCIe downstream port to Thunderbolt port for Alpine Ridge and Titan Ridge as well. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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@ -342,10 +342,13 @@ static struct tb_port *tb_find_pcie_down(struct tb_switch *sw,
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* Hard-coded Thunderbolt port to PCIe down port mapping
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* Hard-coded Thunderbolt port to PCIe down port mapping
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* per controller.
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* per controller.
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*/
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*/
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if (tb_switch_is_cactus_ridge(sw))
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if (tb_switch_is_cactus_ridge(sw) ||
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tb_switch_is_alpine_ridge(sw))
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index = !phy_port ? 6 : 7;
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index = !phy_port ? 6 : 7;
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else if (tb_switch_is_falcon_ridge(sw))
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else if (tb_switch_is_falcon_ridge(sw))
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index = !phy_port ? 6 : 8;
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index = !phy_port ? 6 : 8;
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else if (tb_switch_is_titan_ridge(sw))
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index = !phy_port ? 8 : 9;
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else
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else
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goto out;
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goto out;
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@ -608,6 +608,31 @@ static inline bool tb_switch_is_falcon_ridge(const struct tb_switch *sw)
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}
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}
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}
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}
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static inline bool tb_switch_is_alpine_ridge(const struct tb_switch *sw)
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{
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switch (sw->config.device_id) {
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case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE:
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case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE:
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case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE:
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case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE:
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return true;
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default:
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return false;
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}
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}
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static inline bool tb_switch_is_titan_ridge(const struct tb_switch *sw)
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{
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switch (sw->config.device_id) {
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case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE:
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case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE:
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case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE:
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return true;
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default:
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return false;
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}
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}
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/**
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/**
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* tb_switch_is_icm() - Is the switch handled by ICM firmware
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* tb_switch_is_icm() - Is the switch handled by ICM firmware
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* @sw: Switch to check
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* @sw: Switch to check
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