solos: FPGA and firmware update support.
This is just a straight pull in of changes, syncing us up to 0.07 from openadsl.sf.net Signed-off-by: Nathan Williams <nathan@traverse.com.au> Signed-off-by: Simon Farnsworth <simon@farnz.org.uk> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Simon Farnsworth
David Woodhouse
parent
4306cad6fe
commit
7c4015bdff
@ -9,6 +9,7 @@
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*
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* Authors: Nathan Williams <nathan@traverse.com.au>
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* David Woodhouse <dwmw2@infradead.org>
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* Treker Chen <treker@xrio.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -36,8 +37,9 @@
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#include <linux/sysfs.h>
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#include <linux/device.h>
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#include <linux/kobject.h>
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#include <linux/firmware.h>
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#define VERSION "0.04"
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#define VERSION "0.07"
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#define PTAG "solos-pci"
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#define CONFIG_RAM_SIZE 128
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@ -45,16 +47,27 @@
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#define IRQ_EN_ADDR 0x78
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#define FPGA_VER 0x74
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#define IRQ_CLEAR 0x70
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#define BUG_FLAG 0x6C
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#define WRITE_FLASH 0x6C
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#define PORTS 0x68
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#define FLASH_BLOCK 0x64
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#define FLASH_BUSY 0x60
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#define FPGA_MODE 0x5C
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#define FLASH_MODE 0x58
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#define DATA_RAM_SIZE 32768
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#define BUF_SIZE 4096
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#define FPGA_PAGE 528 /* FPGA flash page size*/
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#define SOLOS_PAGE 512 /* Solos flash page size*/
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#define FPGA_BLOCK (FPGA_PAGE * 8) /* FPGA flash block size*/
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#define SOLOS_BLOCK (SOLOS_PAGE * 8) /* Solos flash block size*/
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#define RX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2)
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#define TX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2 + BUF_SIZE)
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static int debug = 0;
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static int atmdebug = 0;
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static int firmware_upgrade = 0;
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static int fpga_upgrade = 0;
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struct pkt_hdr {
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__le16 size;
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@ -80,6 +93,7 @@ struct solos_card {
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spinlock_t cli_queue_lock;
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struct sk_buff_head tx_queue[4];
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struct sk_buff_head cli_queue[4];
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int flash_chip;
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};
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#define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)
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@ -90,11 +104,19 @@ MODULE_VERSION(VERSION);
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MODULE_LICENSE("GPL");
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MODULE_PARM_DESC(debug, "Enable Loopback");
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MODULE_PARM_DESC(atmdebug, "Print ATM data");
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MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
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MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
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module_param(debug, int, 0444);
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module_param(atmdebug, int, 0644);
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module_param(firmware_upgrade, int, 0444);
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module_param(fpga_upgrade, int, 0444);
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static int opens;
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static struct firmware *fw;
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static int flash_offset;
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void flash_upgrade(struct solos_card *);
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void flash_write(struct solos_card *);
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static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
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struct atm_vcc *vcc);
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static int fpga_tx(struct solos_card *);
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@ -180,6 +202,131 @@ static ssize_t console_store(struct device *dev, struct device_attribute *attr,
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static DEVICE_ATTR(console, 0644, console_show, console_store);
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void flash_upgrade(struct solos_card *card){
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uint32_t data32 = 0;
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int blocksize = 0;
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int numblocks = 0;
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dev_info(&card->dev->dev, "Flash upgrade started\n");
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if (card->flash_chip == 0) {
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if (request_firmware((const struct firmware **)&fw,
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"solos-FPGA.bin",&card->dev->dev))
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{
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dev_info(&card->dev->dev,
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"Failed to find firmware\n");
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return;
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}
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blocksize = FPGA_BLOCK;
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} else {
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if (request_firmware((const struct firmware **)&fw,
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"solos-Firmware.bin",&card->dev->dev))
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{
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dev_info(&card->dev->dev,
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"Failed to find firmware\n");
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return;
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}
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blocksize = SOLOS_BLOCK;
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}
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numblocks = fw->size/blocksize;
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dev_info(&card->dev->dev, "Firmware size: %d\n", fw->size);
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dev_info(&card->dev->dev, "Number of blocks: %d\n", numblocks);
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dev_info(&card->dev->dev, "Changing FPGA to Update mode\n");
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iowrite32(1, card->config_regs + FPGA_MODE);
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data32 = ioread32(card->config_regs + FPGA_MODE);
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/*Set mode to Chip Erase*/
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if (card->flash_chip == 0) {
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dev_info(&card->dev->dev,
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"Set FPGA Flash mode to FPGA Chip Erase\n");
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} else {
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dev_info(&card->dev->dev,
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"Set FPGA Flash mode to Solos Chip Erase\n");
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}
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iowrite32((card->flash_chip * 2), card->config_regs + FLASH_MODE);
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flash_offset = 0;
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iowrite32(1, card->config_regs + WRITE_FLASH);
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return;
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}
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void flash_write(struct solos_card *card){
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int block;
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int block_num;
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int blocksize;
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int i;
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uint32_t data32 = 0;
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/*Clear write flag*/
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iowrite32(0, card->config_regs + WRITE_FLASH);
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/*Set mode to Block Write*/
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/*dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n");*/
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iowrite32(((card->flash_chip * 2) + 1), card->config_regs + FLASH_MODE);
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/*When finished programming flash, release firmware and exit*/
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if (fw->size - flash_offset == 0) {
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//release_firmware(fw); /* This crashes for some reason */
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iowrite32(0, card->config_regs + WRITE_FLASH);
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iowrite32(0, card->config_regs + FPGA_MODE);
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iowrite32(0, card->config_regs + FLASH_MODE);
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dev_info(&card->dev->dev, "Returning FPGA to Data mode\n");
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return;
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}
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if (card->flash_chip == 0) {
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blocksize = FPGA_BLOCK;
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} else {
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blocksize = SOLOS_BLOCK;
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}
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/*Calculate block size*/
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if ((fw->size - flash_offset) > blocksize) {
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block = blocksize;
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} else {
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block = fw->size - flash_offset;
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}
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block_num = flash_offset / blocksize;
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//dev_info(&card->dev->dev, "block %d/%d\n",block_num + 1,(fw->size/512/8));
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/*Copy block into RAM*/
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for(i=0;i<block;i++){
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if(i%4 == 0){
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//dev_info(&card->dev->dev, "i: %d\n", i);
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data32=0x00000000;
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}
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switch(i%4){
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case 0:
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data32 |= 0x0000FF00 &
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(*(fw->data + i + flash_offset) << 8);
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break;
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case 1:
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data32 |= 0x000000FF & *(fw->data + i + flash_offset);
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break;
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case 2:
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data32 |= 0xFF000000 &
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(*(fw->data + i + flash_offset) << 24);
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break;
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case 3:
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data32 |= 0x00FF0000 &
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(*(fw->data + i + flash_offset) << 16);
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break;
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}
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if (i%4 == 3) {
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iowrite32(data32, RX_BUF(card, 3) + i - 3);
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}
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}
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i--;
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if (i%4 != 3) {
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iowrite32(data32, RX_BUF(card, 3) + i - (i%4));
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}
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/*Specify block number and then trigger flash write*/
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iowrite32(block_num, card->config_regs + FLASH_BLOCK);
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iowrite32(1, card->config_regs + WRITE_FLASH);
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// iowrite32(0, card->config_regs + WRITE_FLASH);
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flash_offset += block;
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return;
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}
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static irqreturn_t solos_irq(int irq, void *dev_id)
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{
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struct solos_card *card = dev_id;
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@ -207,6 +354,17 @@ void solos_bh(unsigned long card_arg)
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uint32_t card_flags;
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uint32_t tx_mask;
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uint32_t rx_done = 0;
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uint32_t data32;
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data32 = ioread32(card->config_regs + FPGA_MODE);
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if (data32 != 0) {
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data32 = ioread32(card->config_regs + FLASH_BUSY);
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if (data32 == 0) {
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flash_write(card);
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}
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return;
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}
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card_flags = ioread32(card->config_regs + FLAGS_ADDR);
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@ -680,6 +838,15 @@ static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
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// Enable IRQs
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iowrite32(1, card->config_regs + IRQ_EN_ADDR);
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if(firmware_upgrade != 0){
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card->flash_chip = 1;
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flash_upgrade(card);
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} else {
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if(fpga_upgrade != 0){
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card->flash_chip = 0;
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flash_upgrade(card);
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}
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}
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return 0;
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out_unmap_both:
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