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tools/power/x86/intel-speed-select: Unify TRL levels

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TRL supports different levels including SSE/AVX2/AVX512.

Avoid using hardcoded level name and structure fields, so that a loop can
be used to parse each TRL level instead. This reduces several lines of
source code.

No functional changes are expected.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
[srinivas.pandruvada@linux.intel.com: changelog edits]
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
This commit is contained in:
Zhang Rui 2022-08-20 18:11:21 +08:00 committed by Srinivas Pandruvada
parent 6f561677c2
commit 7c7e7c0d39
3 changed files with 45 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
tools/power/x86/intel-speed-select/isst-core.c
View File

@ -6,6 +6,25 @@
#include "isst.h"
int isst_get_trl_max_levels(void)
{
return 3;
}
char *isst_get_trl_level_name(int level)
{
switch (level) {
case 0:
return "sse";
case 1:
return "avx2";
case 2:
return "avx512";
default:
return NULL;
}
}
int isst_write_pm_config(struct isst_id *id, int cp_state)
{
unsigned int req, resp;
@ -795,6 +814,8 @@ int isst_get_process_ctdp(struct isst_id *id, int tdp_level, struct isst_pkg_ctd
for (i = 0; i <= pkg_dev->levels; ++i) {
struct isst_pkg_ctdp_level_info *ctdp_level;
int trl_max_levels = isst_get_trl_max_levels();
int j;
if (tdp_level != 0xff && i != tdp_level)
continue;
@ -838,8 +859,8 @@ int isst_get_process_ctdp(struct isst_id *id, int tdp_level, struct isst_pkg_ctd
ctdp_level->tdp_ratio = ctdp_level->sse_p1;
}
isst_get_get_trl_from_msr(id, ctdp_level->trl_sse_active_cores);
isst_get_trl_bucket_info(id, &ctdp_level->buckets_info);
isst_get_get_trl_from_msr(id, ctdp_level->trl_ratios[0]);
isst_get_trl_bucket_info(id, &ctdp_level->trl_cores);
continue;
}
@ -861,24 +882,16 @@ int isst_get_process_ctdp(struct isst_id *id, int tdp_level, struct isst_pkg_ctd
if (ret)
return ret;
ret = isst_get_trl_bucket_info(id, &ctdp_level->buckets_info);
ret = isst_get_trl_bucket_info(id, &ctdp_level->trl_cores);
if (ret)
return ret;
ret = isst_get_get_trl(id, i, 0,
ctdp_level->trl_sse_active_cores);
if (ret)
return ret;
ret = isst_get_get_trl(id, i, 1,
ctdp_level->trl_avx_active_cores);
if (ret)
return ret;
ret = isst_get_get_trl(id, i, 2,
ctdp_level->trl_avx_512_active_cores);
if (ret)
return ret;
for (j = 0; j < trl_max_levels; j++) {
ret = isst_get_get_trl(id, i, j,
ctdp_level->trl_ratios[j]);
if (ret)
return ret;
}
isst_get_uncore_p0_p1_info(id, i, ctdp_level);
isst_get_p1_info(id, i, ctdp_level);

48
tools/power/x86/intel-speed-select/isst-display.c
View File

@ -354,6 +354,7 @@ void isst_ctdp_display_information(struct isst_id *id, FILE *outf, int tdp_level
char header[256];
char value[512];
static int level;
int trl_max_levels = isst_get_trl_max_levels();
int i;
if (pkg_dev->processed)
@ -361,7 +362,7 @@ void isst_ctdp_display_information(struct isst_id *id, FILE *outf, int tdp_level
for (i = 0; i <= pkg_dev->levels; ++i) {
struct isst_pkg_ctdp_level_info *ctdp_level;
int j;
int j, k;
ctdp_level = &pkg_dev->ctdp_level[i];
if (!ctdp_level->processed)
@ -505,54 +506,21 @@ void isst_ctdp_display_information(struct isst_id *id, FILE *outf, int tdp_level
format_and_print(outf, level + 2, header, value);
}
snprintf(header, sizeof(header), "turbo-ratio-limits-sse");
format_and_print(outf, level + 2, header, NULL);
for (j = 0; j < 8; ++j) {
snprintf(header, sizeof(header), "bucket-%d", j);
format_and_print(outf, level + 3, header, NULL);
snprintf(header, sizeof(header), "core-count");
snprintf(value, sizeof(value), "%llu", (ctdp_level->buckets_info >> (j * 8)) & 0xff);
format_and_print(outf, level + 4, header, value);
snprintf(header, sizeof(header),
"max-turbo-frequency(MHz)");
snprintf(value, sizeof(value), "%d",
ctdp_level->trl_sse_active_cores[j] *
DISP_FREQ_MULTIPLIER);
format_and_print(outf, level + 4, header, value);
}
if (ctdp_level->trl_avx_active_cores[0]) {
snprintf(header, sizeof(header), "turbo-ratio-limits-avx2");
for (k = 0; k < trl_max_levels; k++) {
snprintf(header, sizeof(header), "turbo-ratio-limits-%s", isst_get_trl_level_name(k));
format_and_print(outf, level + 2, header, NULL);
for (j = 0; j < 8; ++j) {
snprintf(header, sizeof(header), "bucket-%d", j);
format_and_print(outf, level + 3, header, NULL);
snprintf(header, sizeof(header), "core-count");
snprintf(value, sizeof(value), "%llu", (ctdp_level->buckets_info >> (j * 8)) & 0xff);
snprintf(value, sizeof(value), "%llu", (ctdp_level->trl_cores >> (j * 8)) & 0xff);
format_and_print(outf, level + 4, header, value);
snprintf(header, sizeof(header), "max-turbo-frequency(MHz)");
snprintf(value, sizeof(value), "%d", ctdp_level->trl_avx_active_cores[j] * DISP_FREQ_MULTIPLIER);
format_and_print(outf, level + 4, header, value);
}
}
if (ctdp_level->trl_avx_512_active_cores[0]) {
snprintf(header, sizeof(header), "turbo-ratio-limits-avx512");
format_and_print(outf, level + 2, header, NULL);
for (j = 0; j < 8; ++j) {
snprintf(header, sizeof(header), "bucket-%d", j);
format_and_print(outf, level + 3, header, NULL);
snprintf(header, sizeof(header), "core-count");
snprintf(value, sizeof(value), "%llu", (ctdp_level->buckets_info >> (j * 8)) & 0xff);
format_and_print(outf, level + 4, header, value);
snprintf(header, sizeof(header), "max-turbo-frequency(MHz)");
snprintf(value, sizeof(value), "%d", ctdp_level->trl_avx_512_active_cores[j] * DISP_FREQ_MULTIPLIER);
snprintf(value, sizeof(value), "%d", ctdp_level->trl_ratios[k][j] * DISP_FREQ_MULTIPLIER);
format_and_print(outf, level + 4, header, value);
}
}

11
tools/power/x86/intel-speed-select/isst.h
View File

@ -28,6 +28,8 @@
#include <stdarg.h>
#include <sys/ioctl.h>
#include <linux/isst_if.h>
#define BIT(x) (1 << (x))
#define BIT_ULL(nr) (1ULL << (nr))
#define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (sizeof(long) * 8 - 1 - (h))))
@ -153,10 +155,8 @@ struct isst_pkg_ctdp_level_info {
size_t core_cpumask_size;
cpu_set_t *core_cpumask;
int cpu_count;
unsigned long long buckets_info;
int trl_sse_active_cores[ISST_TRL_MAX_ACTIVE_CORES];
int trl_avx_active_cores[ISST_TRL_MAX_ACTIVE_CORES];
int trl_avx_512_active_cores[ISST_TRL_MAX_ACTIVE_CORES];
unsigned long long trl_cores; /* Buckets info */
int trl_ratios[TRL_MAX_LEVELS][ISST_TRL_MAX_ACTIVE_CORES];
int kobj_bucket_index;
int active_bucket;
int fact_max_index;
@ -205,6 +205,9 @@ extern int isst_send_mbox_command(unsigned int cpu, unsigned char command,
extern int isst_send_msr_command(unsigned int cpu, unsigned int command,
int write, unsigned long long *req_resp);
extern int isst_get_trl_max_levels(void);
extern char *isst_get_trl_level_name(int level);
extern int isst_get_ctdp_levels(struct isst_id *id, struct isst_pkg_ctdp *pkg_dev);
extern int isst_get_ctdp_control(struct isst_id *id, int config_index,
struct isst_pkg_ctdp_level_info *ctdp_level);