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drm/amd/amdgpu: add additional page fault settings for gfx11

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Add three additional page fault settings.

V2: move reg offset definition to header file. (Alex)
V3: add all shift/mask definitions of used reg. (Hawking)

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Chengming Gui 2022-06-20 15:52:29 +08:00 committed by Alex Deucher
parent 53bd83dfff
commit 7c8e4a2572
3 changed files with 56 additions and 4 deletions
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32
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
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@ -26,13 +26,10 @@
#include "gc/gc_11_0_0_offset.h"
#include "gc/gc_11_0_0_sh_mask.h"
#include "gc/gc_11_0_0_default.h"
#include "navi10_enum.h"
#include "soc15_common.h"
#define regGCVM_L2_CNTL3_DEFAULT 0x80100007
#define regGCVM_L2_CNTL4_DEFAULT 0x000000c1
#define regGCVM_L2_CNTL5_DEFAULT 0x00003fe0
static const char *gfxhub_client_ids[] = {
"CB/DB",
"Reserved",
@ -414,12 +411,39 @@ static void gfxhub_v3_0_set_fault_enable_default(struct amdgpu_device *adev,
{
u32 tmp;
/* NO halt CP when page fault */
tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);
tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);
WREG32_SOC15(GC, 0, regCP_DEBUG, tmp);
/**
* Set GRBM_GFX_INDEX in broad cast mode
* before programming GL1C_UTCL0_CNTL1 and SQG_CONFIG
*/
WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, regGRBM_GFX_INDEX_DEFAULT);
/**
* Retry respond mode: RETRY
* Error (no retry) respond mode: SUCCESS
*/
tmp = RREG32_SOC15(GC, 0, regGL1C_UTCL0_CNTL1);
tmp = REG_SET_FIELD(tmp, GL1C_UTCL0_CNTL1, RESP_MODE, 0);
tmp = REG_SET_FIELD(tmp, GL1C_UTCL0_CNTL1, RESP_FAULT_MODE, 0x2);
WREG32_SOC15(GC, 0, regGL1C_UTCL0_CNTL1, tmp);
/* These registers are not accessible to VF-SRIOV.
* The PF will program them instead.
*/
if (amdgpu_sriov_vf(adev))
return;
/* Disable SQ XNACK interrupt for all VMIDs */
tmp = RREG32_SOC15(GC, 0, regSQG_CONFIG);
tmp = REG_SET_FIELD(tmp, SQG_CONFIG, XNACK_INTR_MASK,
SQG_CONFIG__XNACK_INTR_MASK_MASK >>
SQG_CONFIG__XNACK_INTR_MASK__SHIFT);
WREG32_SOC15(GC, 0, regSQG_CONFIG, tmp);
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

3
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
View File

@ -4221,6 +4221,7 @@
#define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0
#define regGB_EDC_MODE 0x1e1e
#define regGB_EDC_MODE_BASE_IDX 0
#define regCP_DEBUG 0x1e1f
#define regCP_DEBUG_BASE_IDX 0
#define regCP_CPC_DEBUG 0x1e21
#define regCP_CPC_DEBUG_BASE_IDX 0
@ -8306,6 +8307,8 @@
#define regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX 1
#define regGL1C_STATUS 0x2d41
#define regGL1C_STATUS_BASE_IDX 1
#define regGL1C_UTCL0_CNTL1 0x2d42
#define regGL1C_UTCL0_CNTL1_BASE_IDX 1
#define regGL1C_UTCL0_CNTL2 0x2d43
#define regGL1C_UTCL0_CNTL2_BASE_IDX 1
#define regGL1C_UTCL0_STATUS 0x2d44

25
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h
View File

@ -29424,6 +29424,31 @@
#define GL1C_STATUS__TAG_EVICT_MASK 0x04000000L
#define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION_MASK 0x78000000L
#define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET_MASK 0x80000000L
//GL1C_UTCL0_CNTL1
#define GL1C_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
#define GL1C_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
#define GL1C_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
#define GL1C_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3
#define GL1C_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
#define GL1C_UTCL0_CNTL1__CLIENTID__SHIFT 0x7
#define GL1C_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13
#define GL1C_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
#define GL1C_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a
#define GL1C_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
#define GL1C_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define GL1C_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define GL1C_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
#define GL1C_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
#define GL1C_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
#define GL1C_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L
#define GL1C_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
#define GL1C_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L
#define GL1C_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L
#define GL1C_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
#define GL1C_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L
#define GL1C_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x06000000L
#define GL1C_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
#define GL1C_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
//GL1C_UTCL0_CNTL2
#define GL1C_UTCL0_CNTL2__SPARE__SHIFT 0x0
#define GL1C_UTCL0_CNTL2__COMP_SYNC_DISABLE__SHIFT 0x8