ssb: Fix pcicore cardbus mode
This fixes the pcicore driver to not die a horrible crash death when inserting a cardbus card. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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53521d8c90
commit
7cb4461520
@ -11,6 +11,7 @@
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#include <linux/ssb/ssb.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/ssb/ssb_embedded.h>
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#include "ssb_private.h"
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@ -27,6 +28,18 @@ void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
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ssb_write32(pc->dev, offset, value);
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}
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static inline
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u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
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{
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return ssb_read16(pc->dev, offset);
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}
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static inline
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void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
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{
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ssb_write16(pc->dev, offset, value);
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}
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/**************************************************
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* Code for hostmode operation.
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**************************************************/
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@ -117,8 +130,10 @@ static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
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u32 addr = 0;
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u32 tmp;
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if (unlikely(pc->cardbusmode && dev > 1))
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/* We do only have one cardbus device behind the bridge. */
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if (pc->cardbusmode && (dev >= 1))
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goto out;
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if (bus == 0) {
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/* Type 0 transaction */
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if (unlikely(dev >= SSB_PCI_SLOT_MAX))
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@ -318,7 +333,16 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
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pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
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udelay(1); /* Assertion time demanded by the PCI standard */
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/*TODO cardbus mode */
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if (pc->dev->bus->has_cardbus_slot) {
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ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
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pc->cardbusmode = 1;
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/* GPIO 1 resets the bridge */
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ssb_gpio_out(pc->dev->bus, 1, 1);
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ssb_gpio_outen(pc->dev->bus, 1, 1);
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pcicore_write16(pc, SSB_PCICORE_SPROM(0),
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pcicore_read16(pc, SSB_PCICORE_SPROM(0))
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| 0x0400);
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}
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/* 64MB I/O window */
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
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@ -557,6 +557,7 @@ static int ssb_fetch_invariants(struct ssb_bus *bus,
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goto out;
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memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
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memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
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bus->has_cardbus_slot = iv.has_cardbus_slot;
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out:
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return err;
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}
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@ -282,6 +282,8 @@ struct ssb_bus {
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struct ssb_boardinfo boardinfo;
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/* Contents of the SPROM. */
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struct ssb_sprom sprom;
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/* If the board has a cardbus slot, this is set to true. */
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bool has_cardbus_slot;
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#ifdef CONFIG_SSB_EMBEDDED
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/* Lock for GPIO register access. */
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@ -299,8 +301,13 @@ struct ssb_bus {
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/* The initialization-invariants. */
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struct ssb_init_invariants {
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/* Versioning information about the PCB. */
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struct ssb_boardinfo boardinfo;
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/* The SPROM information. That's either stored in an
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* EEPROM or NVRAM on the board. */
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struct ssb_sprom sprom;
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/* If the board has a cardbus slot, this is set to true. */
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bool has_cardbus_slot;
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};
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/* Type of function to fetch the invariants. */
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typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
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@ -51,6 +51,11 @@
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#define SSB_PCICORE_SBTOPCI1_MASK 0xFC000000
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#define SSB_PCICORE_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
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#define SSB_PCICORE_SBTOPCI2_MASK 0xC0000000
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#define SSB_PCICORE_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
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#define SSB_PCICORE_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
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#define SSB_PCICORE_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
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#define SSB_PCICORE_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
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#define SSB_PCICORE_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
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/* SBtoPCIx */
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#define SSB_PCICORE_SBTOPCI_MEM 0x00000000
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