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spi: cadence-qspi: set maximum chip-select to 4

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Change the maximum chip-select count in cadence-qspi to 4 instead of 16.
The value gets used as default ->num_chipselect when the num-cs DT
property isn't received from devicetree. It also determines the
cqspi->f_pdata array size.

Hardware only supports values up to 4; see cqspi_chipselect() that sets
CS using a one-bit-per-CS 4-bit register field.

Add a static_assert() call as a defensive measure to ensure we stay
under the SPI subsystem limit. It got set to 4 when introduced in
4d8ff6b0991d ("spi: Add multi-cs memories support in SPI core") and
later increased to 16 in 2f8c7c3715f2 ("spi: Raise limit on number of
chip selects").

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://msgid.link/r/20240209-cdns-qspi-cs-v1-2-a4f9dfed9ab4@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Théo Lebrun 2024-02-09 14:45:31 +01:00 committed by Mark Brown
parent 0d62c64a8e
commit 7cc3522aed
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1 changed files with 3 additions and 1 deletions
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4
drivers/spi/spi-cadence-quadspi.c
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@ -31,7 +31,9 @@
#include <linux/timer.h>
#define CQSPI_NAME "cadence-qspi"
#define CQSPI_MAX_CHIPSELECT 16
#define CQSPI_MAX_CHIPSELECT 4
static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX);
/* Quirks */
#define CQSPI_NEEDS_WR_DELAY BIT(0)