amd64_edac: add module registration routines
Also, link into Kbuild by adding Kconfig and Makefile entries. Borislav: - Kconfig/Makefile splitting - use zero-sized arrays for the sysfs attrs if not enabled - rename sysfs attrs to more conform values - shorten CONFIG_ names - make multiple structure members assignment vertically aligned - fix/cleanup comments - fix function return value patterns - fix err labels - fix a memleak bug caught by Ingo - remove the NUMA dependency and use num_k8_northbrides for initializing a driver instance per NB. - do not copy the pvt contents into the mci struct in amd64_init_2nd_stage() and save it in the mci->pvt_info void ptr instead. - cleanup debug calls - simplify amd64_setup_pci_device() Reviewed-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Doug Thompson
Borislav Petkov
parent
f9431992b6
commit
7d6034d321
@ -58,6 +58,32 @@ config EDAC_MM_EDAC
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occurred so that a particular failing memory module can be
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replaced. If unsure, select 'Y'.
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config EDAC_AMD64
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tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
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depends on EDAC_MM_EDAC && X86 && PCI
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default m
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help
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Support for error detection and correction on the AMD 64
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Families of Memory Controllers (K8, F10h and F11h)
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config EDAC_AMD64_ERROR_INJECTION
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bool "Sysfs Error Injection facilities"
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depends on EDAC_AMD64
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help
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Recent Opterons (Family 10h and later) provide for Memory Error
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Injection into the ECC detection circuits. The amd64_edac module
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allows the operator/user to inject Uncorrectable and Correctable
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errors into DRAM.
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When enabled, in each of the respective memory controller directories
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(/sys/devices/system/edac/mc/mcX), there are 3 input files:
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- inject_section (0..3, 16-byte section of 64-byte cacheline),
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- inject_word (0..8, 16-bit word of 16-byte section),
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- inject_ecc_vector (hex ecc vector: select bits of inject word)
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In addition, there are two control files, inject_read and inject_write,
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which trigger the DRAM ECC Read and Write respectively.
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config EDAC_AMD76X
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tristate "AMD 76x (760, 762, 768)"
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@ -30,6 +30,13 @@ obj-$(CONFIG_EDAC_I3000) += i3000_edac.o
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obj-$(CONFIG_EDAC_X38) += x38_edac.o
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obj-$(CONFIG_EDAC_I82860) += i82860_edac.o
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obj-$(CONFIG_EDAC_R82600) += r82600_edac.o
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amd64_edac_mod-y := amd64_edac_err_types.o amd64_edac.o
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amd64_edac_mod-$(CONFIG_EDAC_DEBUG) += amd64_edac_dbg.o
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amd64_edac_mod-$(CONFIG_EDAC_AMD64_ERROR_INJECTION) += amd64_edac_inj.o
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obj-$(CONFIG_EDAC_AMD64) += amd64_edac_mod.o
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obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o
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obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac.o
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obj-$(CONFIG_EDAC_MV64X60) += mv64x60_edac.o
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@ -1,4 +1,5 @@
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#include "amd64_edac.h"
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#include <asm/k8.h>
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static struct edac_pci_ctl_info *amd64_ctl_pci;
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@ -2978,3 +2979,376 @@ static int amd64_check_ecc_enabled(struct amd64_pvt *pvt)
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return ret;
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}
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struct mcidev_sysfs_attribute sysfs_attrs[ARRAY_SIZE(amd64_dbg_attrs) +
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ARRAY_SIZE(amd64_inj_attrs) +
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1];
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struct mcidev_sysfs_attribute terminator = { .attr = { .name = NULL } };
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static void amd64_set_mc_sysfs_attributes(struct mem_ctl_info *mci)
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{
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unsigned int i = 0, j = 0;
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for (; i < ARRAY_SIZE(amd64_dbg_attrs); i++)
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sysfs_attrs[i] = amd64_dbg_attrs[i];
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for (j = 0; j < ARRAY_SIZE(amd64_inj_attrs); j++, i++)
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sysfs_attrs[i] = amd64_inj_attrs[j];
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sysfs_attrs[i] = terminator;
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mci->mc_driver_sysfs_attributes = sysfs_attrs;
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}
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static void amd64_setup_mci_misc_attributes(struct mem_ctl_info *mci)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2;
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mci->edac_ctl_cap = EDAC_FLAG_NONE;
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mci->edac_cap = EDAC_FLAG_NONE;
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if (pvt->nbcap & K8_NBCAP_SECDED)
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mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
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if (pvt->nbcap & K8_NBCAP_CHIPKILL)
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mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
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mci->edac_cap = amd64_determine_edac_cap(pvt);
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mci->mod_name = EDAC_MOD_STR;
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mci->mod_ver = EDAC_AMD64_VERSION;
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mci->ctl_name = get_amd_family_name(pvt->mc_type_index);
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mci->dev_name = pci_name(pvt->dram_f2_ctl);
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mci->ctl_page_to_phys = NULL;
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/* IMPORTANT: Set the polling 'check' function in this module */
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mci->edac_check = amd64_check;
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/* memory scrubber interface */
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mci->set_sdram_scrub_rate = amd64_set_scrub_rate;
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mci->get_sdram_scrub_rate = amd64_get_scrub_rate;
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}
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/*
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* Init stuff for this DRAM Controller device.
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*
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* Due to a hardware feature on Fam10h CPUs, the Enable Extended Configuration
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* Space feature MUST be enabled on ALL Processors prior to actually reading
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* from the ECS registers. Since the loading of the module can occur on any
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* 'core', and cores don't 'see' all the other processors ECS data when the
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* others are NOT enabled. Our solution is to first enable ECS access in this
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* routine on all processors, gather some data in a amd64_pvt structure and
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* later come back in a finish-setup function to perform that final
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* initialization. See also amd64_init_2nd_stage() for that.
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*/
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static int amd64_probe_one_instance(struct pci_dev *dram_f2_ctl,
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int mc_type_index)
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{
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struct amd64_pvt *pvt = NULL;
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int err = 0, ret;
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ret = -ENOMEM;
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pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL);
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if (!pvt)
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goto err_exit;
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pvt->mc_node_id = get_mc_node_id_from_pdev(dram_f2_ctl);
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pvt->dram_f2_ctl = dram_f2_ctl;
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pvt->ext_model = boot_cpu_data.x86_model >> 4;
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pvt->mc_type_index = mc_type_index;
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pvt->ops = family_ops(mc_type_index);
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pvt->old_mcgctl = 0;
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/*
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* We have the dram_f2_ctl device as an argument, now go reserve its
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* sibling devices from the PCI system.
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*/
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ret = -ENODEV;
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err = amd64_reserve_mc_sibling_devices(pvt, mc_type_index);
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if (err)
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goto err_free;
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ret = -EINVAL;
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err = amd64_check_ecc_enabled(pvt);
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if (err)
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goto err_put;
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/*
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* Key operation here: setup of HW prior to performing ops on it. Some
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* setup is required to access ECS data. After this is performed, the
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* 'teardown' function must be called upon error and normal exit paths.
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*/
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if (boot_cpu_data.x86 >= 0x10)
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amd64_setup(pvt);
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/*
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* Save the pointer to the private data for use in 2nd initialization
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* stage
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*/
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pvt_lookup[pvt->mc_node_id] = pvt;
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return 0;
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err_put:
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amd64_free_mc_sibling_devices(pvt);
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err_free:
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kfree(pvt);
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err_exit:
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return ret;
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}
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/*
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* This is the finishing stage of the init code. Needs to be performed after all
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* MCs' hardware have been prepped for accessing extended config space.
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*/
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static int amd64_init_2nd_stage(struct amd64_pvt *pvt)
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{
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int node_id = pvt->mc_node_id;
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struct mem_ctl_info *mci;
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int ret, err = 0;
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amd64_read_mc_registers(pvt);
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ret = -ENODEV;
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if (pvt->ops->probe_valid_hardware) {
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err = pvt->ops->probe_valid_hardware(pvt);
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if (err)
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goto err_exit;
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}
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/*
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* We need to determine how many memory channels there are. Then use
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* that information for calculating the size of the dynamic instance
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* tables in the 'mci' structure
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*/
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pvt->channel_count = pvt->ops->early_channel_count(pvt);
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if (pvt->channel_count < 0)
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goto err_exit;
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ret = -ENOMEM;
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mci = edac_mc_alloc(0, CHIPSELECT_COUNT, pvt->channel_count, node_id);
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if (!mci)
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goto err_exit;
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mci->pvt_info = pvt;
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mci->dev = &pvt->dram_f2_ctl->dev;
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amd64_setup_mci_misc_attributes(mci);
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if (amd64_init_csrows(mci))
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mci->edac_cap = EDAC_FLAG_NONE;
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amd64_enable_ecc_error_reporting(mci);
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amd64_set_mc_sysfs_attributes(mci);
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ret = -ENODEV;
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if (edac_mc_add_mc(mci)) {
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debugf1("failed edac_mc_add_mc()\n");
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goto err_add_mc;
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}
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mci_lookup[node_id] = mci;
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pvt_lookup[node_id] = NULL;
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return 0;
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err_add_mc:
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edac_mc_free(mci);
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err_exit:
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debugf0("failure to init 2nd stage: ret=%d\n", ret);
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amd64_restore_ecc_error_reporting(pvt);
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if (boot_cpu_data.x86 > 0xf)
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amd64_teardown(pvt);
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amd64_free_mc_sibling_devices(pvt);
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kfree(pvt_lookup[pvt->mc_node_id]);
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pvt_lookup[node_id] = NULL;
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return ret;
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}
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static int __devinit amd64_init_one_instance(struct pci_dev *pdev,
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const struct pci_device_id *mc_type)
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{
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int ret = 0;
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debugf0("(MC node=%d,mc_type='%s')\n",
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get_mc_node_id_from_pdev(pdev),
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get_amd_family_name(mc_type->driver_data));
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ret = pci_enable_device(pdev);
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if (ret < 0)
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ret = -EIO;
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else
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ret = amd64_probe_one_instance(pdev, mc_type->driver_data);
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if (ret < 0)
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debugf0("ret=%d\n", ret);
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return ret;
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}
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static void __devexit amd64_remove_one_instance(struct pci_dev *pdev)
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{
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struct mem_ctl_info *mci;
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struct amd64_pvt *pvt;
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/* Remove from EDAC CORE tracking list */
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mci = edac_mc_del_mc(&pdev->dev);
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if (!mci)
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return;
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pvt = mci->pvt_info;
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amd64_restore_ecc_error_reporting(pvt);
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if (boot_cpu_data.x86 > 0xf)
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amd64_teardown(pvt);
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amd64_free_mc_sibling_devices(pvt);
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kfree(pvt);
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mci->pvt_info = NULL;
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mci_lookup[pvt->mc_node_id] = NULL;
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/* Free the EDAC CORE resources */
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edac_mc_free(mci);
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}
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/*
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* This table is part of the interface for loading drivers for PCI devices. The
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* PCI core identifies what devices are on a system during boot, and then
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* inquiry this table to see if this driver is for a given device found.
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*/
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static const struct pci_device_id amd64_pci_table[] __devinitdata = {
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{
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.class = 0,
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.class_mask = 0,
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.driver_data = K8_CPUS
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},
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{
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_10H_NB_DRAM,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.class = 0,
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.class_mask = 0,
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.driver_data = F10_CPUS
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},
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{
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_11H_NB_DRAM,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.class = 0,
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.class_mask = 0,
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.driver_data = F11_CPUS
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},
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{0, }
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};
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MODULE_DEVICE_TABLE(pci, amd64_pci_table);
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static struct pci_driver amd64_pci_driver = {
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.name = EDAC_MOD_STR,
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.probe = amd64_init_one_instance,
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.remove = __devexit_p(amd64_remove_one_instance),
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.id_table = amd64_pci_table,
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};
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static void amd64_setup_pci_device(void)
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{
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struct mem_ctl_info *mci;
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struct amd64_pvt *pvt;
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if (amd64_ctl_pci)
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return;
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mci = mci_lookup[0];
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if (mci) {
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pvt = mci->pvt_info;
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amd64_ctl_pci =
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edac_pci_create_generic_ctl(&pvt->dram_f2_ctl->dev,
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EDAC_MOD_STR);
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if (!amd64_ctl_pci) {
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pr_warning("%s(): Unable to create PCI control\n",
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__func__);
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pr_warning("%s(): PCI error report via EDAC not set\n",
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__func__);
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}
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}
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}
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static int __init amd64_edac_init(void)
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{
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int nb, err = -ENODEV;
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edac_printk(KERN_INFO, EDAC_MOD_STR, EDAC_AMD64_VERSION "\n");
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opstate_init();
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if (cache_k8_northbridges() < 0)
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goto err_exit;
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err = pci_register_driver(&amd64_pci_driver);
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if (err)
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return err;
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/*
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* At this point, the array 'pvt_lookup[]' contains pointers to alloc'd
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* amd64_pvt structs. These will be used in the 2nd stage init function
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* to finish initialization of the MC instances.
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*/
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for (nb = 0; nb < num_k8_northbridges; nb++) {
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if (!pvt_lookup[nb])
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continue;
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err = amd64_init_2nd_stage(pvt_lookup[nb]);
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if (err)
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goto err_exit;
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}
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amd64_setup_pci_device();
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return 0;
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err_exit:
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debugf0("'finish_setup' stage failed\n");
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pci_unregister_driver(&amd64_pci_driver);
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return err;
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}
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static void __exit amd64_edac_exit(void)
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{
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if (amd64_ctl_pci)
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edac_pci_release_generic_ctl(amd64_ctl_pci);
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pci_unregister_driver(&amd64_pci_driver);
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}
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module_init(amd64_edac_init);
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module_exit(amd64_edac_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, "
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"Dave Peterson, Thayne Harbaugh");
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MODULE_DESCRIPTION("MC support for AMD64 memory controllers - "
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EDAC_AMD64_VERSION);
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module_param(edac_op_state, int, 0444);
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MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
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@ -577,6 +577,21 @@ extern const char *ii_msgs[4];
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extern const char *ext_msgs[32];
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extern const char *htlink_msgs[8];
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#ifdef CONFIG_EDAC_DEBUG
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#define NUM_DBG_ATTRS 9
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#else
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#define NUM_DBG_ATTRS 0
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#endif
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#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
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#define NUM_INJ_ATTRS 5
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#else
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#define NUM_INJ_ATTRS 0
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#endif
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extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
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amd64_inj_attrs[NUM_INJ_ATTRS];
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/*
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* Each of the PCI Device IDs types have their own set of hardware accessor
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* functions and per device encoding/decoding logic.
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||||
|
||||
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Reference in New Issue
Block a user