clocksource/drivers/sun5i: Remove duplication of code and data
Move the clocksource and clock_event_device structs into the main struct sun5i_timer, and update the code for the new layout. This removes a lot of duplication of both code and data. Signed-off-by: Mans Rullgard <mans@mansr.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20230630201800.16501-2-mans@mansr.com
This commit is contained in:
Mans Rullgard
Daniel Lezcano
parent
bd0f3aac47
commit
7ded803873
@ -35,31 +35,26 @@
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#define TIMER_SYNC_TICKS 3
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struct sun5i_timer {
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/* Pointless struct to minimise diff */
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struct _sun5i_timer {
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void __iomem *base;
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struct clk *clk;
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struct notifier_block clk_rate_cb;
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u32 ticks_per_jiffy;
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};
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#define to_sun5i_timer(x) \
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container_of(x, struct sun5i_timer, clk_rate_cb)
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struct sun5i_timer_clksrc {
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struct sun5i_timer timer;
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struct sun5i_timer {
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struct _sun5i_timer timer;
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struct clocksource clksrc;
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};
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#define to_sun5i_timer_clksrc(x) \
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container_of(x, struct sun5i_timer_clksrc, clksrc)
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struct sun5i_timer_clkevt {
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struct sun5i_timer timer;
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struct clock_event_device clkevt;
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};
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#define to_sun5i_timer_clkevt(x) \
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container_of(x, struct sun5i_timer_clkevt, clkevt)
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#define nb_to_sun5i_timer(x) \
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container_of(x, struct sun5i_timer, timer.clk_rate_cb)
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#define clksrc_to_sun5i_timer(x) \
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container_of(x, struct sun5i_timer, clksrc)
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#define clkevt_to_sun5i_timer(x) \
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container_of(x, struct sun5i_timer, clkevt)
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/*
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* When we disable a timer, we need to wait at least for 2 cycles of
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@ -67,7 +62,7 @@ struct sun5i_timer_clkevt {
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* that is already setup and runs at the same frequency than the other
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* timers, and we never will be disabled.
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*/
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static void sun5i_clkevt_sync(struct sun5i_timer_clkevt *ce)
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static void sun5i_clkevt_sync(struct sun5i_timer *ce)
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{
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u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1));
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@ -75,7 +70,7 @@ static void sun5i_clkevt_sync(struct sun5i_timer_clkevt *ce)
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cpu_relax();
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}
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static void sun5i_clkevt_time_stop(struct sun5i_timer_clkevt *ce, u8 timer)
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static void sun5i_clkevt_time_stop(struct sun5i_timer *ce, u8 timer)
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{
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u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
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writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer));
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@ -83,12 +78,12 @@ static void sun5i_clkevt_time_stop(struct sun5i_timer_clkevt *ce, u8 timer)
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sun5i_clkevt_sync(ce);
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}
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static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay)
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static void sun5i_clkevt_time_setup(struct sun5i_timer *ce, u8 timer, u32 delay)
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{
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writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer));
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}
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static void sun5i_clkevt_time_start(struct sun5i_timer_clkevt *ce, u8 timer, bool periodic)
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static void sun5i_clkevt_time_start(struct sun5i_timer *ce, u8 timer, bool periodic)
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{
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u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
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@ -103,7 +98,7 @@ static void sun5i_clkevt_time_start(struct sun5i_timer_clkevt *ce, u8 timer, boo
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static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt)
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{
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struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
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struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
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sun5i_clkevt_time_stop(ce, 0);
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return 0;
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@ -111,7 +106,7 @@ static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt)
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static int sun5i_clkevt_set_oneshot(struct clock_event_device *clkevt)
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{
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struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
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struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
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sun5i_clkevt_time_stop(ce, 0);
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sun5i_clkevt_time_start(ce, 0, false);
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@ -120,7 +115,7 @@ static int sun5i_clkevt_set_oneshot(struct clock_event_device *clkevt)
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static int sun5i_clkevt_set_periodic(struct clock_event_device *clkevt)
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{
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struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
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struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
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sun5i_clkevt_time_stop(ce, 0);
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sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy);
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@ -131,7 +126,7 @@ static int sun5i_clkevt_set_periodic(struct clock_event_device *clkevt)
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static int sun5i_clkevt_next_event(unsigned long evt,
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struct clock_event_device *clkevt)
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{
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struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
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struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
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sun5i_clkevt_time_stop(ce, 0);
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sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS);
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@ -142,7 +137,7 @@ static int sun5i_clkevt_next_event(unsigned long evt,
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static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
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{
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struct sun5i_timer_clkevt *ce = dev_id;
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struct sun5i_timer *ce = dev_id;
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writel(0x1, ce->timer.base + TIMER_IRQ_ST_REG);
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ce->clkevt.event_handler(&ce->clkevt);
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@ -152,17 +147,16 @@ static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
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static u64 sun5i_clksrc_read(struct clocksource *clksrc)
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{
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struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc);
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struct sun5i_timer *cs = clksrc_to_sun5i_timer(clksrc);
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return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1));
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}
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static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
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unsigned long event, void *data)
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static int sun5i_rate_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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struct sun5i_timer *timer = to_sun5i_timer(nb);
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struct sun5i_timer_clksrc *cs = container_of(timer, struct sun5i_timer_clksrc, timer);
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struct sun5i_timer *cs = nb_to_sun5i_timer(nb);
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switch (event) {
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case PRE_RATE_CHANGE:
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@ -171,6 +165,8 @@ static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
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case POST_RATE_CHANGE:
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clocksource_register_hz(&cs->clksrc, ndata->new_rate);
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clockevents_update_freq(&cs->clkevt, ndata->new_rate);
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cs->timer.ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ);
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break;
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default:
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@ -181,41 +177,12 @@ static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
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}
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static int __init sun5i_setup_clocksource(struct device_node *node,
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void __iomem *base,
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struct clk *clk, int irq)
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struct sun5i_timer *cs,
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unsigned long rate)
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{
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struct sun5i_timer_clksrc *cs;
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unsigned long rate;
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void __iomem *base = cs->timer.base;
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int ret;
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cs = kzalloc(sizeof(*cs), GFP_KERNEL);
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if (!cs)
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return -ENOMEM;
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("Couldn't enable parent clock\n");
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goto err_free;
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}
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rate = clk_get_rate(clk);
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if (!rate) {
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pr_err("Couldn't get parent clock rate\n");
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ret = -EINVAL;
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goto err_disable_clk;
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}
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cs->timer.base = base;
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cs->timer.clk = clk;
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cs->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clksrc;
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cs->timer.clk_rate_cb.next = NULL;
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ret = clk_notifier_register(clk, &cs->timer.clk_rate_cb);
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if (ret) {
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pr_err("Unable to register clock notifier.\n");
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goto err_disable_clk;
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}
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writel(~0, base + TIMER_INTVAL_LO_REG(1));
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writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
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base + TIMER_CTL_REG(1));
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@ -229,72 +196,20 @@ static int __init sun5i_setup_clocksource(struct device_node *node,
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ret = clocksource_register_hz(&cs->clksrc, rate);
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if (ret) {
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pr_err("Couldn't register clock source.\n");
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goto err_remove_notifier;
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return ret;
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}
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return 0;
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err_remove_notifier:
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clk_notifier_unregister(clk, &cs->timer.clk_rate_cb);
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err_disable_clk:
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clk_disable_unprepare(clk);
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err_free:
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kfree(cs);
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return ret;
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}
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static int sun5i_rate_cb_clkevt(struct notifier_block *nb,
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unsigned long event, void *data)
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static int __init sun5i_setup_clockevent(struct device_node *node,
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struct sun5i_timer *ce,
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unsigned long rate, int irq)
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{
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struct clk_notifier_data *ndata = data;
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struct sun5i_timer *timer = to_sun5i_timer(nb);
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struct sun5i_timer_clkevt *ce = container_of(timer, struct sun5i_timer_clkevt, timer);
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if (event == POST_RATE_CHANGE) {
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clockevents_update_freq(&ce->clkevt, ndata->new_rate);
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ce->timer.ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ);
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}
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return NOTIFY_DONE;
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}
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static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem *base,
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struct clk *clk, int irq)
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{
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struct sun5i_timer_clkevt *ce;
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unsigned long rate;
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void __iomem *base = ce->timer.base;
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int ret;
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u32 val;
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ce = kzalloc(sizeof(*ce), GFP_KERNEL);
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if (!ce)
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return -ENOMEM;
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("Couldn't enable parent clock\n");
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goto err_free;
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}
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rate = clk_get_rate(clk);
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if (!rate) {
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pr_err("Couldn't get parent clock rate\n");
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ret = -EINVAL;
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goto err_disable_clk;
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}
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ce->timer.base = base;
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ce->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
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ce->timer.clk = clk;
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ce->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clkevt;
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ce->timer.clk_rate_cb.next = NULL;
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ret = clk_notifier_register(clk, &ce->timer.clk_rate_cb);
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if (ret) {
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pr_err("Unable to register clock notifier.\n");
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goto err_disable_clk;
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}
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ce->clkevt.name = node->name;
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ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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ce->clkevt.set_next_event = sun5i_clkevt_next_event;
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@ -317,27 +232,25 @@ static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem
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"sun5i_timer0", ce);
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if (ret) {
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pr_err("Unable to register interrupt\n");
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goto err_remove_notifier;
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return ret;
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}
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return 0;
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err_remove_notifier:
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clk_notifier_unregister(clk, &ce->timer.clk_rate_cb);
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err_disable_clk:
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clk_disable_unprepare(clk);
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err_free:
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kfree(ce);
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return ret;
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}
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static int __init sun5i_timer_init(struct device_node *node)
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{
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struct sun5i_timer *st;
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struct reset_control *rstc;
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void __iomem *timer_base;
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struct clk *clk;
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unsigned long rate;
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int irq, ret;
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st = kzalloc(sizeof(*st), GFP_KERNEL);
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if (!st)
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return -ENOMEM;
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timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (IS_ERR(timer_base)) {
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pr_err("Can't map registers\n");
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@ -356,15 +269,48 @@ static int __init sun5i_timer_init(struct device_node *node)
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return PTR_ERR(clk);
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("Couldn't enable parent clock\n");
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goto err_free;
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}
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rate = clk_get_rate(clk);
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if (!rate) {
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pr_err("Couldn't get parent clock rate\n");
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ret = -EINVAL;
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goto err_disable_clk;
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}
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st->timer.base = timer_base;
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st->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
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st->timer.clk = clk;
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st->timer.clk_rate_cb.notifier_call = sun5i_rate_cb;
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st->timer.clk_rate_cb.next = NULL;
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ret = clk_notifier_register(clk, &st->timer.clk_rate_cb);
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if (ret) {
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pr_err("Unable to register clock notifier.\n");
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goto err_disable_clk;
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}
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rstc = of_reset_control_get(node, NULL);
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if (!IS_ERR(rstc))
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reset_control_deassert(rstc);
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ret = sun5i_setup_clocksource(node, timer_base, clk, irq);
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ret = sun5i_setup_clocksource(node, st, rate);
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if (ret)
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return ret;
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goto err_remove_notifier;
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return sun5i_setup_clockevent(node, timer_base, clk, irq);
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return sun5i_setup_clockevent(node, st, rate, irq);
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err_remove_notifier:
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clk_notifier_unregister(clk, &st->timer.clk_rate_cb);
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err_disable_clk:
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clk_disable_unprepare(clk);
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err_free:
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kfree(st);
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return ret;
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}
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TIMER_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
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sun5i_timer_init);
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