clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs
The PCIe GDSCs can be shared with other masters and should use the APCS collapse-vote register when updating the power state. This is specifically also needed to be able to disable power domains that have been enabled by boot firmware using the vote register. Following other recent Qualcomm platforms, describe this register and the corresponding mask for the PCIe (and _phy) GDSCs. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-5-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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@ -2998,6 +2998,8 @@ static struct clk_branch gcc_video_axi1_clk = {
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static struct gdsc pcie_0_gdsc = {
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.gdscr = 0x6b004,
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.collapse_ctrl = 0x52020,
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.collapse_mask = BIT(0),
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.pd = {
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.name = "pcie_0_gdsc",
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},
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@ -3007,6 +3009,8 @@ static struct gdsc pcie_0_gdsc = {
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static struct gdsc pcie_0_phy_gdsc = {
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.gdscr = 0x6c000,
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.collapse_ctrl = 0x52020,
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.collapse_mask = BIT(3),
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.pd = {
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.name = "pcie_0_phy_gdsc",
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},
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@ -3016,6 +3020,8 @@ static struct gdsc pcie_0_phy_gdsc = {
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static struct gdsc pcie_1_gdsc = {
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.gdscr = 0x8d004,
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.collapse_ctrl = 0x52020,
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.collapse_mask = BIT(1),
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.pd = {
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.name = "pcie_1_gdsc",
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},
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@ -3025,6 +3031,8 @@ static struct gdsc pcie_1_gdsc = {
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static struct gdsc pcie_1_phy_gdsc = {
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.gdscr = 0x8e000,
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.collapse_ctrl = 0x52020,
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.collapse_mask = BIT(4),
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.pd = {
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.name = "pcie_1_phy_gdsc",
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},
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