intel_idle: Fix SPR C6 optimization
The Sapphire Rapids (SPR) C6 optimization was added to the end of the 'spr_idle_state_table_update()' function. However, the function has a 'return' which may happen before the optimization has a chance to run. And this may prevent the optimization from happening. This is an unlikely scenario, but possible if user boots with, say, the 'intel_idle.preferred_cstates=6' kernel boot option. This patch fixes the issue by eliminating the problematic 'return' statement. Fixes: 3a9cf77b60dc ("intel_idle: add core C6 optimization for SPR") Suggested-by: Jan Beulich <jbeulich@suse.com> Reported-by: Jan Beulich <jbeulich@suse.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> [ rjw: Minor changelog edits ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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@ -1581,11 +1581,9 @@ static void __init spr_idle_state_table_update(void)
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unsigned long long msr;
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/* Check if user prefers C1E over C1. */
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if (preferred_states_mask & BIT(2)) {
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if (preferred_states_mask & BIT(1))
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/* Both can't be enabled, stick to the defaults. */
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return;
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if ((preferred_states_mask & BIT(2)) &&
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!(preferred_states_mask & BIT(1))) {
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/* Disable C1 and enable C1E. */
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spr_cstates[0].flags |= CPUIDLE_FLAG_UNUSABLE;
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spr_cstates[1].flags &= ~CPUIDLE_FLAG_UNUSABLE;
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