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spi: spi-dw: fix all sparse warnings

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The dw_{read,write}[lw] macros produce sparse warnings everytime they
are used.  The "read" ones cause:

warning: cast removes address space of expression
warning: incorrect type in argument 1 (different address spaces)
   expected void const volatile [noderef] <asn:2>*addr
   got unsigned int *<noident>

And the "write" ones:

warning: cast removes address space of expression
warning: incorrect type in argument 2 (different address spaces)
   expected void volatile [noderef] <asn:2>*addr
   got unsigned int *<noident>

Fix this by removing struct dw_spi_reg and converting all the register
offsets to #defines. Then convert the macros into inlined functions so
that proper type checking can occur.

While here, also fix the three sparse warnings in spi-dw-mid.c due to
the return value of ioremap_nocache being stored in a u32 * not a
void __iomem *.

With these changes the spi-dw* files all build with no sparse warnings.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: Feng Tang <feng.tang@intel.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
H Hartley Sweeten
2011-09-20 11:06:17 -07:00
committed by Grant Likely
parent 3e3ea71627
commit 7eb187b3cd
3 changed files with 89 additions and 79 deletions
Download Patch File Download Diff File Expand all files Collapse all files

97
drivers/spi/spi-dw.h
View File

@ -4,6 +4,33 @@
#include <linux/io.h>
#include <linux/scatterlist.h>
/* Register offsets */
#define DW_SPI_CTRL0 0x00
#define DW_SPI_CTRL1 0x04
#define DW_SPI_SSIENR 0x08
#define DW_SPI_MWCR 0x0c
#define DW_SPI_SER 0x10
#define DW_SPI_BAUDR 0x14
#define DW_SPI_TXFLTR 0x18
#define DW_SPI_RXFLTR 0x1c
#define DW_SPI_TXFLR 0x20
#define DW_SPI_RXFLR 0x24
#define DW_SPI_SR 0x28
#define DW_SPI_IMR 0x2c
#define DW_SPI_ISR 0x30
#define DW_SPI_RISR 0x34
#define DW_SPI_TXOICR 0x38
#define DW_SPI_RXOICR 0x3c
#define DW_SPI_RXUICR 0x40
#define DW_SPI_MSTICR 0x44
#define DW_SPI_ICR 0x48
#define DW_SPI_DMACR 0x4c
#define DW_SPI_DMATDLR 0x50
#define DW_SPI_DMARDLR 0x54
#define DW_SPI_IDR 0x58
#define DW_SPI_VERSION 0x5c
#define DW_SPI_DR 0x60
/* Bit fields in CTRLR0 */
#define SPI_DFS_OFFSET 0
@ -55,35 +82,6 @@ enum dw_ssi_type {
SSI_NS_MICROWIRE,
};
struct dw_spi_reg {
u32 ctrl0;
u32 ctrl1;
u32 ssienr;
u32 mwcr;
u32 ser;
u32 baudr;
u32 txfltr;
u32 rxfltr;
u32 txflr;
u32 rxflr;
u32 sr;
u32 imr;
u32 isr;
u32 risr;
u32 txoicr;
u32 rxoicr;
u32 rxuicr;
u32 msticr;
u32 icr;
u32 dmacr;
u32 dmatdlr;
u32 dmardlr;
u32 idr;
u32 version;
u32 dr; /* Currently oper as 32 bits,
though only low 16 bits matters */
} __packed;
struct dw_spi;
struct dw_spi_dma_ops {
int (*dma_init)(struct dw_spi *dws);
@ -161,23 +159,34 @@ struct dw_spi {
#endif
};
#define dw_readl(dw, name) \
__raw_readl(&(((struct dw_spi_reg *)dw->regs)->name))
#define dw_writel(dw, name, val) \
__raw_writel((val), &(((struct dw_spi_reg *)dw->regs)->name))
#define dw_readw(dw, name) \
__raw_readw(&(((struct dw_spi_reg *)dw->regs)->name))
#define dw_writew(dw, name, val) \
__raw_writew((val), &(((struct dw_spi_reg *)dw->regs)->name))
static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
{
return __raw_readl(dws->regs + offset);
}
static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
{
__raw_writel(val, dws->regs + offset);
}
static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
{
return __raw_readw(dws->regs + offset);
}
static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
{
__raw_writew(val, dws->regs + offset);
}
static inline void spi_enable_chip(struct dw_spi *dws, int enable)
{
dw_writel(dws, ssienr, (enable ? 1 : 0));
dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
}
static inline void spi_set_clk(struct dw_spi *dws, u16 div)
{
dw_writel(dws, baudr, div);
dw_writel(dws, DW_SPI_BAUDR, div);
}
static inline void spi_chip_sel(struct dw_spi *dws, u16 cs)
@ -188,7 +197,7 @@ static inline void spi_chip_sel(struct dw_spi *dws, u16 cs)
if (dws->cs_control)
dws->cs_control(1);
dw_writel(dws, ser, 1 << cs);
dw_writel(dws, DW_SPI_SER, 1 << cs);
}
/* Disable IRQ bits */
@ -196,8 +205,8 @@ static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
{
u32 new_mask;
new_mask = dw_readl(dws, imr) & ~mask;
dw_writel(dws, imr, new_mask);
new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
dw_writel(dws, DW_SPI_IMR, new_mask);
}
/* Enable IRQ bits */
@ -205,8 +214,8 @@ static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
{
u32 new_mask;
new_mask = dw_readl(dws, imr) | mask;
dw_writel(dws, imr, new_mask);
new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
dw_writel(dws, DW_SPI_IMR, new_mask);
}
/*