powerpc/powernv: remove unused NPU DMA code
None of these routines were ever used anywhere in the kernel tree since they were added to the kernel. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Christoph Hellwig
Michael Ellerman
parent
c498a4f9a7
commit
7eb3cf7619
@ -116,8 +116,6 @@ typedef struct {
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/* Number of users of the external (Nest) MMU */
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/* Number of users of the external (Nest) MMU */
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atomic_t copros;
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atomic_t copros;
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/* NPU NMMU context */
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struct npu_context *npu_context;
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struct hash_mm_context *hash_context;
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struct hash_mm_context *hash_context;
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unsigned long vdso_base;
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unsigned long vdso_base;
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@ -11,35 +11,13 @@
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#define _ASM_POWERNV_H
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#define _ASM_POWERNV_H
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#ifdef CONFIG_PPC_POWERNV
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#ifdef CONFIG_PPC_POWERNV
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#define NPU2_WRITE 1
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extern void powernv_set_nmmu_ptcr(unsigned long ptcr);
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extern void powernv_set_nmmu_ptcr(unsigned long ptcr);
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extern struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
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unsigned long flags,
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void (*cb)(struct npu_context *, void *),
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void *priv);
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extern void pnv_npu2_destroy_context(struct npu_context *context,
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struct pci_dev *gpdev);
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extern int pnv_npu2_handle_fault(struct npu_context *context, uintptr_t *ea,
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unsigned long *flags, unsigned long *status,
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int count);
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void pnv_program_cpu_hotplug_lpcr(unsigned int cpu, u64 lpcr_val);
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void pnv_program_cpu_hotplug_lpcr(unsigned int cpu, u64 lpcr_val);
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void pnv_tm_init(void);
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void pnv_tm_init(void);
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#else
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#else
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static inline void powernv_set_nmmu_ptcr(unsigned long ptcr) { }
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static inline void powernv_set_nmmu_ptcr(unsigned long ptcr) { }
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static inline struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
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unsigned long flags,
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struct npu_context *(*cb)(struct npu_context *, void *),
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void *priv) { return ERR_PTR(-ENODEV); }
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static inline void pnv_npu2_destroy_context(struct npu_context *context,
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struct pci_dev *gpdev) { }
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static inline int pnv_npu2_handle_fault(struct npu_context *context,
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uintptr_t *ea, unsigned long *flags,
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unsigned long *status, int count) {
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return -ENODEV;
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}
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static inline void pnv_tm_init(void) { }
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static inline void pnv_tm_init(void) { }
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#endif
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#endif
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@ -179,7 +179,6 @@ static int radix__init_new_context(struct mm_struct *mm)
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*/
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*/
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asm volatile("ptesync;isync" : : : "memory");
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asm volatile("ptesync;isync" : : : "memory");
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mm->context.npu_context = NULL;
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mm->context.hash_context = NULL;
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mm->context.hash_context = NULL;
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return index;
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return index;
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@ -22,12 +22,6 @@
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#include "pci.h"
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#include "pci.h"
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/*
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* spinlock to protect initialisation of an npu_context for a particular
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* mm_struct.
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*/
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static DEFINE_SPINLOCK(npu_context_lock);
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static struct pci_dev *get_pci_dev(struct device_node *dn)
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static struct pci_dev *get_pci_dev(struct device_node *dn)
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{
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{
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struct pci_dn *pdn = PCI_DN(dn);
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struct pci_dn *pdn = PCI_DN(dn);
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@ -375,15 +369,6 @@ struct npu_comp {
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/* An NPU descriptor, valid for POWER9 only */
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/* An NPU descriptor, valid for POWER9 only */
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struct npu {
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struct npu {
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int index;
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int index;
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__be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
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unsigned int mmio_atsd_count;
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/* Bitmask for MMIO register usage */
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unsigned long mmio_atsd_usage;
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/* Do we need to explicitly flush the nest mmu? */
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bool nmmu_flush;
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struct npu_comp npucomp;
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struct npu_comp npucomp;
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};
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};
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@ -640,534 +625,8 @@ struct iommu_table_group *pnv_npu_compound_attach(struct pnv_ioda_pe *pe)
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}
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}
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#endif /* CONFIG_IOMMU_API */
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#endif /* CONFIG_IOMMU_API */
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/* Maximum number of nvlinks per npu */
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#define NV_MAX_LINKS 6
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/* Maximum index of npu2 hosts in the system. Always < NV_MAX_NPUS */
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static int max_npu2_index;
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struct npu_context {
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struct mm_struct *mm;
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struct pci_dev *npdev[NV_MAX_NPUS][NV_MAX_LINKS];
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struct mmu_notifier mn;
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struct kref kref;
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bool nmmu_flush;
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/* Callback to stop translation requests on a given GPU */
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void (*release_cb)(struct npu_context *context, void *priv);
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/*
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* Private pointer passed to the above callback for usage by
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* device drivers.
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*/
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void *priv;
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};
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struct mmio_atsd_reg {
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struct npu *npu;
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int reg;
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};
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/*
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* Find a free MMIO ATSD register and mark it in use. Return -ENOSPC
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* if none are available.
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*/
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static int get_mmio_atsd_reg(struct npu *npu)
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{
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int i;
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for (i = 0; i < npu->mmio_atsd_count; i++) {
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if (!test_bit(i, &npu->mmio_atsd_usage))
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if (!test_and_set_bit_lock(i, &npu->mmio_atsd_usage))
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return i;
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}
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return -ENOSPC;
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}
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static void put_mmio_atsd_reg(struct npu *npu, int reg)
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{
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clear_bit_unlock(reg, &npu->mmio_atsd_usage);
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}
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/* MMIO ATSD register offsets */
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#define XTS_ATSD_LAUNCH 0
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#define XTS_ATSD_AVA 1
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#define XTS_ATSD_STAT 2
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static unsigned long get_atsd_launch_val(unsigned long pid, unsigned long psize)
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{
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unsigned long launch = 0;
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if (psize == MMU_PAGE_COUNT) {
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/* IS set to invalidate entire matching PID */
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launch |= PPC_BIT(12);
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} else {
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/* AP set to invalidate region of psize */
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launch |= (u64)mmu_get_ap(psize) << PPC_BITLSHIFT(17);
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}
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/* PRS set to process-scoped */
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launch |= PPC_BIT(13);
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/* PID */
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launch |= pid << PPC_BITLSHIFT(38);
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/* Leave "No flush" (bit 39) 0 so every ATSD performs a flush */
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return launch;
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}
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static void mmio_atsd_regs_write(struct mmio_atsd_reg
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mmio_atsd_reg[NV_MAX_NPUS], unsigned long offset,
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unsigned long val)
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{
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struct npu *npu;
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int i, reg;
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for (i = 0; i <= max_npu2_index; i++) {
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reg = mmio_atsd_reg[i].reg;
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if (reg < 0)
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continue;
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npu = mmio_atsd_reg[i].npu;
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__raw_writeq_be(val, npu->mmio_atsd_regs[reg] + offset);
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}
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}
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static void mmio_invalidate_pid(struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS],
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unsigned long pid)
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{
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unsigned long launch = get_atsd_launch_val(pid, MMU_PAGE_COUNT);
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/* Invalidating the entire process doesn't use a va */
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mmio_atsd_regs_write(mmio_atsd_reg, XTS_ATSD_LAUNCH, launch);
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}
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static void mmio_invalidate_range(struct mmio_atsd_reg
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mmio_atsd_reg[NV_MAX_NPUS], unsigned long pid,
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unsigned long start, unsigned long psize)
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{
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unsigned long launch = get_atsd_launch_val(pid, psize);
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/* Write all VAs first */
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mmio_atsd_regs_write(mmio_atsd_reg, XTS_ATSD_AVA, start);
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/* Issue one barrier for all address writes */
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eieio();
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/* Launch */
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mmio_atsd_regs_write(mmio_atsd_reg, XTS_ATSD_LAUNCH, launch);
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}
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#define mn_to_npu_context(x) container_of(x, struct npu_context, mn)
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static void mmio_invalidate_wait(
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struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS])
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{
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struct npu *npu;
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int i, reg;
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/* Wait for all invalidations to complete */
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for (i = 0; i <= max_npu2_index; i++) {
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if (mmio_atsd_reg[i].reg < 0)
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continue;
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/* Wait for completion */
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npu = mmio_atsd_reg[i].npu;
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reg = mmio_atsd_reg[i].reg;
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while (__raw_readq(npu->mmio_atsd_regs[reg] + XTS_ATSD_STAT))
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cpu_relax();
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}
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}
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/*
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* Acquires all the address translation shootdown (ATSD) registers required to
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* launch an ATSD on all links this npu_context is active on.
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*/
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static void acquire_atsd_reg(struct npu_context *npu_context,
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struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS])
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{
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int i, j;
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struct npu *npu;
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struct pci_dev *npdev;
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for (i = 0; i <= max_npu2_index; i++) {
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mmio_atsd_reg[i].reg = -1;
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for (j = 0; j < NV_MAX_LINKS; j++) {
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/*
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* There are no ordering requirements with respect to
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* the setup of struct npu_context, but to ensure
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* consistent behaviour we need to ensure npdev[][] is
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* only read once.
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*/
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npdev = READ_ONCE(npu_context->npdev[i][j]);
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if (!npdev)
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continue;
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npu = pci_bus_to_host(npdev->bus)->npu;
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if (!npu)
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continue;
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mmio_atsd_reg[i].npu = npu;
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mmio_atsd_reg[i].reg = get_mmio_atsd_reg(npu);
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while (mmio_atsd_reg[i].reg < 0) {
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mmio_atsd_reg[i].reg = get_mmio_atsd_reg(npu);
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cpu_relax();
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}
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break;
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}
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}
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}
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/*
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* Release previously acquired ATSD registers. To avoid deadlocks the registers
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* must be released in the same order they were acquired above in
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* acquire_atsd_reg.
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*/
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static void release_atsd_reg(struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS])
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{
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int i;
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for (i = 0; i <= max_npu2_index; i++) {
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/*
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* We can't rely on npu_context->npdev[][] being the same here
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* as when acquire_atsd_reg() was called, hence we use the
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* values stored in mmio_atsd_reg during the acquire phase
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* rather than re-reading npdev[][].
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*/
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if (mmio_atsd_reg[i].reg < 0)
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continue;
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put_mmio_atsd_reg(mmio_atsd_reg[i].npu, mmio_atsd_reg[i].reg);
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}
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}
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/*
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* Invalidate a virtual address range
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*/
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static void mmio_invalidate(struct npu_context *npu_context,
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unsigned long start, unsigned long size)
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{
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struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS];
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unsigned long pid = npu_context->mm->context.id;
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unsigned long atsd_start = 0;
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unsigned long end = start + size - 1;
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int atsd_psize = MMU_PAGE_COUNT;
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/*
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* Convert the input range into one of the supported sizes. If the range
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* doesn't fit, use the next larger supported size. Invalidation latency
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* is high, so over-invalidation is preferred to issuing multiple
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* invalidates.
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*
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* A 4K page size isn't supported by NPU/GPU ATS, so that case is
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* ignored.
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*/
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if (size == SZ_64K) {
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atsd_start = start;
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atsd_psize = MMU_PAGE_64K;
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} else if (ALIGN_DOWN(start, SZ_2M) == ALIGN_DOWN(end, SZ_2M)) {
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atsd_start = ALIGN_DOWN(start, SZ_2M);
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atsd_psize = MMU_PAGE_2M;
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} else if (ALIGN_DOWN(start, SZ_1G) == ALIGN_DOWN(end, SZ_1G)) {
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atsd_start = ALIGN_DOWN(start, SZ_1G);
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atsd_psize = MMU_PAGE_1G;
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}
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if (npu_context->nmmu_flush)
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/*
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* Unfortunately the nest mmu does not support flushing specific
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* addresses so we have to flush the whole mm once before
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* shooting down the GPU translation.
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*/
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flush_all_mm(npu_context->mm);
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/*
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* Loop over all the NPUs this process is active on and launch
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* an invalidate.
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*/
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acquire_atsd_reg(npu_context, mmio_atsd_reg);
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if (atsd_psize == MMU_PAGE_COUNT)
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mmio_invalidate_pid(mmio_atsd_reg, pid);
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else
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mmio_invalidate_range(mmio_atsd_reg, pid, atsd_start,
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atsd_psize);
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mmio_invalidate_wait(mmio_atsd_reg);
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/*
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* The GPU requires two flush ATSDs to ensure all entries have been
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* flushed. We use PID 0 as it will never be used for a process on the
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* GPU.
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*/
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mmio_invalidate_pid(mmio_atsd_reg, 0);
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mmio_invalidate_wait(mmio_atsd_reg);
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mmio_invalidate_pid(mmio_atsd_reg, 0);
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mmio_invalidate_wait(mmio_atsd_reg);
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release_atsd_reg(mmio_atsd_reg);
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}
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static void pnv_npu2_mn_release(struct mmu_notifier *mn,
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struct mm_struct *mm)
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{
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|
||||||
struct npu_context *npu_context = mn_to_npu_context(mn);
|
|
||||||
|
|
||||||
/* Call into device driver to stop requests to the NMMU */
|
|
||||||
if (npu_context->release_cb)
|
|
||||||
npu_context->release_cb(npu_context, npu_context->priv);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* There should be no more translation requests for this PID, but we
|
|
||||||
* need to ensure any entries for it are removed from the TLB.
|
|
||||||
*/
|
|
||||||
mmio_invalidate(npu_context, 0, ~0UL);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void pnv_npu2_mn_invalidate_range(struct mmu_notifier *mn,
|
|
||||||
struct mm_struct *mm,
|
|
||||||
unsigned long start, unsigned long end)
|
|
||||||
{
|
|
||||||
struct npu_context *npu_context = mn_to_npu_context(mn);
|
|
||||||
mmio_invalidate(npu_context, start, end - start);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct mmu_notifier_ops nv_nmmu_notifier_ops = {
|
|
||||||
.release = pnv_npu2_mn_release,
|
|
||||||
.invalidate_range = pnv_npu2_mn_invalidate_range,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Call into OPAL to setup the nmmu context for the current task in
|
|
||||||
* the NPU. This must be called to setup the context tables before the
|
|
||||||
* GPU issues ATRs. pdev should be a pointed to PCIe GPU device.
|
|
||||||
*
|
|
||||||
* A release callback should be registered to allow a device driver to
|
|
||||||
* be notified that it should not launch any new translation requests
|
|
||||||
* as the final TLB invalidate is about to occur.
|
|
||||||
*
|
|
||||||
* Returns an error if there no contexts are currently available or a
|
|
||||||
* npu_context which should be passed to pnv_npu2_handle_fault().
|
|
||||||
*
|
|
||||||
* mmap_sem must be held in write mode and must not be called from interrupt
|
|
||||||
* context.
|
|
||||||
*/
|
|
||||||
struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
|
|
||||||
unsigned long flags,
|
|
||||||
void (*cb)(struct npu_context *, void *),
|
|
||||||
void *priv)
|
|
||||||
{
|
|
||||||
int rc;
|
|
||||||
u32 nvlink_index;
|
|
||||||
struct device_node *nvlink_dn;
|
|
||||||
struct mm_struct *mm = current->mm;
|
|
||||||
struct npu *npu;
|
|
||||||
struct npu_context *npu_context;
|
|
||||||
struct pci_controller *hose;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* At present we don't support GPUs connected to multiple NPUs and I'm
|
|
||||||
* not sure the hardware does either.
|
|
||||||
*/
|
|
||||||
struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);
|
|
||||||
|
|
||||||
if (!npdev)
|
|
||||||
/* No nvlink associated with this GPU device */
|
|
||||||
return ERR_PTR(-ENODEV);
|
|
||||||
|
|
||||||
/* We only support DR/PR/HV in pnv_npu2_map_lpar_dev() */
|
|
||||||
if (flags & ~(MSR_DR | MSR_PR | MSR_HV))
|
|
||||||
return ERR_PTR(-EINVAL);
|
|
||||||
|
|
||||||
nvlink_dn = of_parse_phandle(npdev->dev.of_node, "ibm,nvlink", 0);
|
|
||||||
if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index",
|
|
||||||
&nvlink_index)))
|
|
||||||
return ERR_PTR(-ENODEV);
|
|
||||||
|
|
||||||
if (!mm || mm->context.id == 0) {
|
|
||||||
/*
|
|
||||||
* Kernel thread contexts are not supported and context id 0 is
|
|
||||||
* reserved on the GPU.
|
|
||||||
*/
|
|
||||||
return ERR_PTR(-EINVAL);
|
|
||||||
}
|
|
||||||
|
|
||||||
hose = pci_bus_to_host(npdev->bus);
|
|
||||||
npu = hose->npu;
|
|
||||||
if (!npu)
|
|
||||||
return ERR_PTR(-ENODEV);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* We store the npu pci device so we can more easily get at the
|
|
||||||
* associated npus.
|
|
||||||
*/
|
|
||||||
spin_lock(&npu_context_lock);
|
|
||||||
npu_context = mm->context.npu_context;
|
|
||||||
if (npu_context) {
|
|
||||||
if (npu_context->release_cb != cb ||
|
|
||||||
npu_context->priv != priv) {
|
|
||||||
spin_unlock(&npu_context_lock);
|
|
||||||
return ERR_PTR(-EINVAL);
|
|
||||||
}
|
|
||||||
|
|
||||||
WARN_ON(!kref_get_unless_zero(&npu_context->kref));
|
|
||||||
}
|
|
||||||
spin_unlock(&npu_context_lock);
|
|
||||||
|
|
||||||
if (!npu_context) {
|
|
||||||
/*
|
|
||||||
* We can set up these fields without holding the
|
|
||||||
* npu_context_lock as the npu_context hasn't been returned to
|
|
||||||
* the caller meaning it can't be destroyed. Parallel allocation
|
|
||||||
* is protected against by mmap_sem.
|
|
||||||
*/
|
|
||||||
rc = -ENOMEM;
|
|
||||||
npu_context = kzalloc(sizeof(struct npu_context), GFP_KERNEL);
|
|
||||||
if (npu_context) {
|
|
||||||
kref_init(&npu_context->kref);
|
|
||||||
npu_context->mm = mm;
|
|
||||||
npu_context->mn.ops = &nv_nmmu_notifier_ops;
|
|
||||||
rc = __mmu_notifier_register(&npu_context->mn, mm);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (rc) {
|
|
||||||
kfree(npu_context);
|
|
||||||
return ERR_PTR(rc);
|
|
||||||
}
|
|
||||||
|
|
||||||
mm->context.npu_context = npu_context;
|
|
||||||
}
|
|
||||||
|
|
||||||
npu_context->release_cb = cb;
|
|
||||||
npu_context->priv = priv;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* npdev is a pci_dev pointer setup by the PCI code. We assign it to
|
|
||||||
* npdev[][] to indicate to the mmu notifiers that an invalidation
|
|
||||||
* should also be sent over this nvlink. The notifiers don't use any
|
|
||||||
* other fields in npu_context, so we just need to ensure that when they
|
|
||||||
* deference npu_context->npdev[][] it is either a valid pointer or
|
|
||||||
* NULL.
|
|
||||||
*/
|
|
||||||
WRITE_ONCE(npu_context->npdev[npu->index][nvlink_index], npdev);
|
|
||||||
|
|
||||||
if (!npu->nmmu_flush) {
|
|
||||||
/*
|
|
||||||
* If we're not explicitly flushing ourselves we need to mark
|
|
||||||
* the thread for global flushes
|
|
||||||
*/
|
|
||||||
npu_context->nmmu_flush = false;
|
|
||||||
mm_context_add_copro(mm);
|
|
||||||
} else
|
|
||||||
npu_context->nmmu_flush = true;
|
|
||||||
|
|
||||||
return npu_context;
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL(pnv_npu2_init_context);
|
|
||||||
|
|
||||||
static void pnv_npu2_release_context(struct kref *kref)
|
|
||||||
{
|
|
||||||
struct npu_context *npu_context =
|
|
||||||
container_of(kref, struct npu_context, kref);
|
|
||||||
|
|
||||||
if (!npu_context->nmmu_flush)
|
|
||||||
mm_context_remove_copro(npu_context->mm);
|
|
||||||
|
|
||||||
npu_context->mm->context.npu_context = NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Destroy a context on the given GPU. May free the npu_context if it is no
|
|
||||||
* longer active on any GPUs. Must not be called from interrupt context.
|
|
||||||
*/
|
|
||||||
void pnv_npu2_destroy_context(struct npu_context *npu_context,
|
|
||||||
struct pci_dev *gpdev)
|
|
||||||
{
|
|
||||||
int removed;
|
|
||||||
struct npu *npu;
|
|
||||||
struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);
|
|
||||||
struct device_node *nvlink_dn;
|
|
||||||
u32 nvlink_index;
|
|
||||||
struct pci_controller *hose;
|
|
||||||
|
|
||||||
if (WARN_ON(!npdev))
|
|
||||||
return;
|
|
||||||
|
|
||||||
hose = pci_bus_to_host(npdev->bus);
|
|
||||||
npu = hose->npu;
|
|
||||||
if (!npu)
|
|
||||||
return;
|
|
||||||
nvlink_dn = of_parse_phandle(npdev->dev.of_node, "ibm,nvlink", 0);
|
|
||||||
if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index",
|
|
||||||
&nvlink_index)))
|
|
||||||
return;
|
|
||||||
WRITE_ONCE(npu_context->npdev[npu->index][nvlink_index], NULL);
|
|
||||||
spin_lock(&npu_context_lock);
|
|
||||||
removed = kref_put(&npu_context->kref, pnv_npu2_release_context);
|
|
||||||
spin_unlock(&npu_context_lock);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* We need to do this outside of pnv_npu2_release_context so that it is
|
|
||||||
* outside the spinlock as mmu_notifier_destroy uses SRCU.
|
|
||||||
*/
|
|
||||||
if (removed) {
|
|
||||||
mmu_notifier_unregister(&npu_context->mn,
|
|
||||||
npu_context->mm);
|
|
||||||
|
|
||||||
kfree(npu_context);
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL(pnv_npu2_destroy_context);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Assumes mmap_sem is held for the contexts associated mm.
|
|
||||||
*/
|
|
||||||
int pnv_npu2_handle_fault(struct npu_context *context, uintptr_t *ea,
|
|
||||||
unsigned long *flags, unsigned long *status, int count)
|
|
||||||
{
|
|
||||||
u64 rc = 0, result = 0;
|
|
||||||
int i, is_write;
|
|
||||||
struct page *page[1];
|
|
||||||
const char __user *u;
|
|
||||||
char c;
|
|
||||||
|
|
||||||
/* mmap_sem should be held so the struct_mm must be present */
|
|
||||||
struct mm_struct *mm = context->mm;
|
|
||||||
|
|
||||||
WARN_ON(!rwsem_is_locked(&mm->mmap_sem));
|
|
||||||
|
|
||||||
for (i = 0; i < count; i++) {
|
|
||||||
is_write = flags[i] & NPU2_WRITE;
|
|
||||||
rc = get_user_pages_remote(NULL, mm, ea[i], 1,
|
|
||||||
is_write ? FOLL_WRITE : 0,
|
|
||||||
page, NULL, NULL);
|
|
||||||
|
|
||||||
if (rc != 1) {
|
|
||||||
status[i] = rc;
|
|
||||||
result = -EFAULT;
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Make sure partition scoped tree gets a pte */
|
|
||||||
u = page_address(page[0]);
|
|
||||||
if (__get_user(c, u))
|
|
||||||
result = -EFAULT;
|
|
||||||
|
|
||||||
status[i] = 0;
|
|
||||||
put_page(page[0]);
|
|
||||||
}
|
|
||||||
|
|
||||||
return result;
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL(pnv_npu2_handle_fault);
|
|
||||||
|
|
||||||
int pnv_npu2_init(struct pci_controller *hose)
|
int pnv_npu2_init(struct pci_controller *hose)
|
||||||
{
|
{
|
||||||
unsigned int i;
|
|
||||||
u64 mmio_atsd;
|
|
||||||
static int npu_index;
|
static int npu_index;
|
||||||
struct npu *npu;
|
struct npu *npu;
|
||||||
int ret;
|
int ret;
|
||||||
@ -1176,33 +635,18 @@ int pnv_npu2_init(struct pci_controller *hose)
|
|||||||
if (!npu)
|
if (!npu)
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
|
|
||||||
npu->nmmu_flush = of_property_read_bool(hose->dn, "ibm,nmmu-flush");
|
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(npu->mmio_atsd_regs) &&
|
|
||||||
!of_property_read_u64_index(hose->dn, "ibm,mmio-atsd",
|
|
||||||
i, &mmio_atsd); i++)
|
|
||||||
npu->mmio_atsd_regs[i] = ioremap(mmio_atsd, 32);
|
|
||||||
|
|
||||||
pr_info("NPU%d: Found %d MMIO ATSD registers", hose->global_number, i);
|
|
||||||
npu->mmio_atsd_count = i;
|
|
||||||
npu->mmio_atsd_usage = 0;
|
|
||||||
npu_index++;
|
npu_index++;
|
||||||
if (WARN_ON(npu_index >= NV_MAX_NPUS)) {
|
if (WARN_ON(npu_index >= NV_MAX_NPUS)) {
|
||||||
ret = -ENOSPC;
|
ret = -ENOSPC;
|
||||||
goto fail_exit;
|
goto fail_exit;
|
||||||
}
|
}
|
||||||
max_npu2_index = npu_index;
|
|
||||||
npu->index = npu_index;
|
npu->index = npu_index;
|
||||||
hose->npu = npu;
|
hose->npu = npu;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
fail_exit:
|
fail_exit:
|
||||||
for (i = 0; i < npu->mmio_atsd_count; ++i)
|
|
||||||
iounmap(npu->mmio_atsd_regs[i]);
|
|
||||||
|
|
||||||
kfree(npu);
|
kfree(npu);
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user