net-next/hinic: Add cmdq completion handler
Add cmdq completion handler for getting a notification about the completion of cmdq commands. Signed-off-by: Aviad Krawczyk <aviad.krawczyk@huawei.com> Signed-off-by: Zhao Chen <zhaochen6@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Aviad Krawczyk
David S. Miller
parent
76baca2e92
commit
7ef37fe4c1
@ -40,12 +40,31 @@
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#include "hinic_hw_io.h"
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#include "hinic_hw_dev.h"
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#define CMDQ_CEQE_TYPE_SHIFT 0
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#define CMDQ_CEQE_TYPE_MASK 0x7
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#define CMDQ_CEQE_GET(val, member) \
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(((val) >> CMDQ_CEQE_##member##_SHIFT) \
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& CMDQ_CEQE_##member##_MASK)
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#define CMDQ_WQE_ERRCODE_VAL_SHIFT 20
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#define CMDQ_WQE_ERRCODE_VAL_MASK 0xF
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#define CMDQ_WQE_ERRCODE_GET(val, member) \
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(((val) >> CMDQ_WQE_ERRCODE_##member##_SHIFT) \
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& CMDQ_WQE_ERRCODE_##member##_MASK)
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#define CMDQ_DB_PI_OFF(pi) (((u16)LOWER_8_BITS(pi)) << 3)
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#define CMDQ_DB_ADDR(db_base, pi) ((db_base) + CMDQ_DB_PI_OFF(pi))
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#define CMDQ_WQE_HEADER(wqe) ((struct hinic_cmdq_header *)(wqe))
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#define CMDQ_WQE_COMPLETED(ctrl_info) \
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HINIC_CMDQ_CTRL_GET(ctrl_info, HW_BUSY_BIT)
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#define FIRST_DATA_TO_WRITE_LAST sizeof(u64)
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#define CMDQ_DB_OFF SZ_2K
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@ -145,6 +164,22 @@ void hinic_free_cmdq_buf(struct hinic_cmdqs *cmdqs,
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pci_pool_free(cmdqs->cmdq_buf_pool, cmdq_buf->buf, cmdq_buf->dma_addr);
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}
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static unsigned int cmdq_wqe_size_from_bdlen(enum bufdesc_len len)
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{
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unsigned int wqe_size = 0;
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switch (len) {
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case BUFDESC_LCMD_LEN:
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wqe_size = WQE_LCMD_SIZE;
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break;
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case BUFDESC_SCMD_LEN:
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wqe_size = WQE_SCMD_SIZE;
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break;
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}
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return wqe_size;
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}
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static void cmdq_set_sge_completion(struct hinic_cmdq_completion *completion,
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struct hinic_cmdq_buf *buf_out)
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{
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@ -210,6 +245,15 @@ static void cmdq_set_lcmd_bufdesc(struct hinic_cmdq_wqe_lcmd *wqe_lcmd,
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hinic_set_sge(&wqe_lcmd->buf_desc.sge, buf_in->dma_addr, buf_in->size);
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}
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static void cmdq_set_direct_wqe_data(struct hinic_cmdq_direct_wqe *wqe,
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void *buf_in, u32 in_size)
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{
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struct hinic_cmdq_wqe_scmd *wqe_scmd = &wqe->wqe_scmd;
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wqe_scmd->buf_desc.buf_len = in_size;
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memcpy(wqe_scmd->buf_desc.data, buf_in, in_size);
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}
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static void cmdq_set_lcmd_wqe(struct hinic_cmdq_wqe *wqe,
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enum cmdq_cmd_type cmd_type,
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struct hinic_cmdq_buf *buf_in,
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@ -238,6 +282,36 @@ static void cmdq_set_lcmd_wqe(struct hinic_cmdq_wqe *wqe,
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cmdq_set_lcmd_bufdesc(wqe_lcmd, buf_in);
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}
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static void cmdq_set_direct_wqe(struct hinic_cmdq_wqe *wqe,
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enum cmdq_cmd_type cmd_type,
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void *buf_in, u16 in_size,
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struct hinic_cmdq_buf *buf_out, int wrapped,
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enum hinic_cmd_ack_type ack_type,
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enum hinic_mod_type mod, u8 cmd, u16 prod_idx)
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{
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struct hinic_cmdq_direct_wqe *direct_wqe = &wqe->direct_wqe;
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enum completion_format complete_format;
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struct hinic_cmdq_wqe_scmd *wqe_scmd;
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wqe_scmd = &direct_wqe->wqe_scmd;
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switch (cmd_type) {
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case CMDQ_CMD_SYNC_SGE_RESP:
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complete_format = COMPLETE_SGE;
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cmdq_set_sge_completion(&wqe_scmd->completion, buf_out);
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break;
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case CMDQ_CMD_SYNC_DIRECT_RESP:
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complete_format = COMPLETE_DIRECT;
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wqe_scmd->completion.direct_resp = 0;
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break;
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}
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cmdq_prepare_wqe_ctrl(wqe, wrapped, ack_type, mod, cmd, prod_idx,
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complete_format, DATA_DIRECT, BUFDESC_SCMD_LEN);
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cmdq_set_direct_wqe_data(direct_wqe, buf_in, in_size);
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}
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static void cmdq_wqe_fill(void *dst, void *src)
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{
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memcpy(dst + FIRST_DATA_TO_WRITE_LAST, src + FIRST_DATA_TO_WRITE_LAST,
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@ -352,6 +426,52 @@ static int cmdq_sync_cmd_direct_resp(struct hinic_cmdq *cmdq,
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return 0;
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}
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static int cmdq_set_arm_bit(struct hinic_cmdq *cmdq, void *buf_in,
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u16 in_size)
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{
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struct hinic_cmdq_wqe *curr_cmdq_wqe, cmdq_wqe;
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u16 curr_prod_idx, next_prod_idx;
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struct hinic_wq *wq = cmdq->wq;
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struct hinic_hw_wqe *hw_wqe;
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int wrapped, num_wqebbs;
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/* Keep doorbell index correct */
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spin_lock(&cmdq->cmdq_lock);
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/* WQE_SIZE = WQEBB_SIZE, we will get the wq element and not shadow*/
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hw_wqe = hinic_get_wqe(wq, WQE_SCMD_SIZE, &curr_prod_idx);
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if (IS_ERR(hw_wqe)) {
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spin_unlock(&cmdq->cmdq_lock);
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return -EBUSY;
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}
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curr_cmdq_wqe = &hw_wqe->cmdq_wqe;
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wrapped = cmdq->wrapped;
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num_wqebbs = ALIGN(WQE_SCMD_SIZE, wq->wqebb_size) / wq->wqebb_size;
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next_prod_idx = curr_prod_idx + num_wqebbs;
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if (next_prod_idx >= wq->q_depth) {
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cmdq->wrapped = !cmdq->wrapped;
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next_prod_idx -= wq->q_depth;
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}
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cmdq_set_direct_wqe(&cmdq_wqe, CMDQ_CMD_SYNC_DIRECT_RESP, buf_in,
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in_size, NULL, wrapped, HINIC_CMD_ACK_TYPE_CMDQ,
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HINIC_MOD_COMM, CMDQ_SET_ARM_CMD, curr_prod_idx);
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/* The data that is written to HW should be in Big Endian Format */
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hinic_cpu_to_be32(&cmdq_wqe, WQE_SCMD_SIZE);
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/* cmdq wqe is not shadow, therefore wqe will be written to wq */
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cmdq_wqe_fill(curr_cmdq_wqe, &cmdq_wqe);
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cmdq_set_db(cmdq, HINIC_CMDQ_SYNC, next_prod_idx);
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spin_unlock(&cmdq->cmdq_lock);
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return 0;
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}
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static int cmdq_params_valid(struct hinic_cmdq_buf *buf_in)
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{
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if (buf_in->size > HINIC_CMDQ_MAX_DATA_SIZE)
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@ -388,6 +508,139 @@ int hinic_cmdq_direct_resp(struct hinic_cmdqs *cmdqs,
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mod, cmd, buf_in, resp);
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}
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/**
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* hinic_set_arm_bit - set arm bit for enable interrupt again
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* @cmdqs: the cmdqs
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* @q_type: type of queue to set the arm bit for
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* @q_id: the queue number
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*
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* Return 0 - Success, negative - Failure
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**/
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int hinic_set_arm_bit(struct hinic_cmdqs *cmdqs,
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enum hinic_set_arm_qtype q_type, u32 q_id)
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{
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struct hinic_cmdq *cmdq = &cmdqs->cmdq[HINIC_CMDQ_SYNC];
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struct hinic_hwif *hwif = cmdqs->hwif;
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struct pci_dev *pdev = hwif->pdev;
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struct hinic_cmdq_arm_bit arm_bit;
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int err;
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arm_bit.q_type = q_type;
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arm_bit.q_id = q_id;
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err = cmdq_set_arm_bit(cmdq, &arm_bit, sizeof(arm_bit));
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if (err) {
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dev_err(&pdev->dev, "Failed to set arm for qid %d\n", q_id);
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return err;
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}
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return 0;
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}
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static void clear_wqe_complete_bit(struct hinic_cmdq *cmdq,
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struct hinic_cmdq_wqe *wqe)
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{
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u32 header_info = be32_to_cpu(CMDQ_WQE_HEADER(wqe)->header_info);
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unsigned int bufdesc_len, wqe_size;
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struct hinic_ctrl *ctrl;
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bufdesc_len = HINIC_CMDQ_WQE_HEADER_GET(header_info, BUFDESC_LEN);
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wqe_size = cmdq_wqe_size_from_bdlen(bufdesc_len);
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if (wqe_size == WQE_LCMD_SIZE) {
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struct hinic_cmdq_wqe_lcmd *wqe_lcmd = &wqe->wqe_lcmd;
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ctrl = &wqe_lcmd->ctrl;
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} else {
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struct hinic_cmdq_direct_wqe *direct_wqe = &wqe->direct_wqe;
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struct hinic_cmdq_wqe_scmd *wqe_scmd;
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wqe_scmd = &direct_wqe->wqe_scmd;
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ctrl = &wqe_scmd->ctrl;
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}
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/* clear HW busy bit */
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ctrl->ctrl_info = 0;
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wmb(); /* verify wqe is clear */
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}
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/**
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* cmdq_arm_ceq_handler - cmdq completion event handler for arm command
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* @cmdq: the cmdq of the arm command
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* @wqe: the wqe of the arm command
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*
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* Return 0 - Success, negative - Failure
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**/
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static int cmdq_arm_ceq_handler(struct hinic_cmdq *cmdq,
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struct hinic_cmdq_wqe *wqe)
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{
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struct hinic_cmdq_direct_wqe *direct_wqe = &wqe->direct_wqe;
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struct hinic_cmdq_wqe_scmd *wqe_scmd;
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struct hinic_ctrl *ctrl;
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u32 ctrl_info;
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wqe_scmd = &direct_wqe->wqe_scmd;
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ctrl = &wqe_scmd->ctrl;
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ctrl_info = be32_to_cpu(ctrl->ctrl_info);
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/* HW should toggle the HW BUSY BIT */
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if (!CMDQ_WQE_COMPLETED(ctrl_info))
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return -EBUSY;
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clear_wqe_complete_bit(cmdq, wqe);
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hinic_put_wqe(cmdq->wq, WQE_SCMD_SIZE);
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return 0;
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}
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static void cmdq_update_errcode(struct hinic_cmdq *cmdq, u16 prod_idx,
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int errcode)
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{
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if (cmdq->errcode[prod_idx])
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*cmdq->errcode[prod_idx] = errcode;
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}
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/**
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* cmdq_arm_ceq_handler - cmdq completion event handler for sync command
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* @cmdq: the cmdq of the command
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* @cons_idx: the consumer index to update the error code for
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* @errcode: the error code
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**/
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static void cmdq_sync_cmd_handler(struct hinic_cmdq *cmdq, u16 cons_idx,
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int errcode)
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{
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u16 prod_idx = cons_idx;
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spin_lock(&cmdq->cmdq_lock);
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cmdq_update_errcode(cmdq, prod_idx, errcode);
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wmb(); /* write all before update for the command request */
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if (cmdq->done[prod_idx])
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complete(cmdq->done[prod_idx]);
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spin_unlock(&cmdq->cmdq_lock);
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}
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static int cmdq_cmd_ceq_handler(struct hinic_cmdq *cmdq, u16 ci,
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struct hinic_cmdq_wqe *cmdq_wqe)
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{
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struct hinic_cmdq_wqe_lcmd *wqe_lcmd = &cmdq_wqe->wqe_lcmd;
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struct hinic_status *status = &wqe_lcmd->status;
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struct hinic_ctrl *ctrl = &wqe_lcmd->ctrl;
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int errcode;
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if (!CMDQ_WQE_COMPLETED(be32_to_cpu(ctrl->ctrl_info)))
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return -EBUSY;
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errcode = CMDQ_WQE_ERRCODE_GET(be32_to_cpu(status->status_info), VAL);
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cmdq_sync_cmd_handler(cmdq, ci, errcode);
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clear_wqe_complete_bit(cmdq, cmdq_wqe);
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hinic_put_wqe(cmdq->wq, WQE_LCMD_SIZE);
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return 0;
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}
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/**
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* cmdq_ceq_handler - cmdq completion event handler
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* @handle: private data for the handler(cmdqs)
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@ -395,7 +648,49 @@ int hinic_cmdq_direct_resp(struct hinic_cmdqs *cmdqs,
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**/
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static void cmdq_ceq_handler(void *handle, u32 ceqe_data)
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{
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/* should be implemented */
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enum hinic_cmdq_type cmdq_type = CMDQ_CEQE_GET(ceqe_data, TYPE);
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struct hinic_cmdqs *cmdqs = (struct hinic_cmdqs *)handle;
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struct hinic_cmdq *cmdq = &cmdqs->cmdq[cmdq_type];
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struct hinic_cmdq_header *header;
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struct hinic_hw_wqe *hw_wqe;
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int err, set_arm = 0;
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u32 saved_data;
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u16 ci;
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/* Read the smallest wqe size for getting wqe size */
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while ((hw_wqe = hinic_read_wqe(cmdq->wq, WQE_SCMD_SIZE, &ci))) {
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if (IS_ERR(hw_wqe))
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break;
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header = CMDQ_WQE_HEADER(&hw_wqe->cmdq_wqe);
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saved_data = be32_to_cpu(header->saved_data);
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if (HINIC_SAVED_DATA_GET(saved_data, ARM)) {
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/* arm_bit was set until here */
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set_arm = 0;
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if (cmdq_arm_ceq_handler(cmdq, &hw_wqe->cmdq_wqe))
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break;
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} else {
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set_arm = 1;
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hw_wqe = hinic_read_wqe(cmdq->wq, WQE_LCMD_SIZE, &ci);
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if (IS_ERR(hw_wqe))
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break;
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if (cmdq_cmd_ceq_handler(cmdq, ci, &hw_wqe->cmdq_wqe))
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break;
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}
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}
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if (set_arm) {
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struct hinic_hwif *hwif = cmdqs->hwif;
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struct pci_dev *pdev = hwif->pdev;
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err = hinic_set_arm_bit(cmdqs, HINIC_SET_ARM_CMDQ, cmdq_type);
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if (err)
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dev_err(&pdev->dev, "Failed to set arm for CMDQ\n");
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}
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}
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/**
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@ -100,6 +100,10 @@ enum hinic_cmdq_type {
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HINIC_MAX_CMDQ_TYPES,
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};
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enum hinic_set_arm_qtype {
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HINIC_SET_ARM_CMDQ,
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};
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enum hinic_cmd_ack_type {
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HINIC_CMD_ACK_TYPE_CMDQ,
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};
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@ -110,6 +114,11 @@ struct hinic_cmdq_buf {
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size_t size;
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};
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struct hinic_cmdq_arm_bit {
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u32 q_type;
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u32 q_id;
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};
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struct hinic_cmdq_ctxt_info {
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u64 curr_wqe_page_pfn;
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u64 wq_block_pfn;
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@ -167,6 +176,9 @@ int hinic_cmdq_direct_resp(struct hinic_cmdqs *cmdqs,
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enum hinic_mod_type mod, u8 cmd,
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struct hinic_cmdq_buf *buf_in, u64 *out_param);
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int hinic_set_arm_bit(struct hinic_cmdqs *cmdqs,
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enum hinic_set_arm_qtype q_type, u32 q_id);
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int hinic_init_cmdqs(struct hinic_cmdqs *cmdqs, struct hinic_hwif *hwif,
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void __iomem **db_area);
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