drm/nouveau/fifo/ga100-: initial support
- replaces the hacked-up version that existed solely to support TTM v2. remove earlier hack preventing use of non-stall intr for fences Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
05d271c32e
commit
7f4f35ea5b
@ -86,6 +86,7 @@
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#define PASCAL_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c06f
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#define VOLTA_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c36f
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#define TURING_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c46f
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#define AMPERE_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c56f
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#define AMPERE_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000c76f
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#define NV50_DISP /* if0010.h */ 0x00005070
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@ -56,6 +56,7 @@ struct nvkm_fifo {
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struct {
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#define NVKM_FIFO_NONSTALL_EVENT BIT(0)
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struct nvkm_event event;
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struct nvkm_inth intr;
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} nonstall;
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struct {
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@ -92,5 +93,6 @@ int gm200_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct
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int gp100_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
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int gv100_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
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int tu102_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
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int ga100_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
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int ga102_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
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#endif
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@ -253,6 +253,7 @@ nouveau_channel_ctor(struct nouveau_drm *drm, struct nvif_device *device, bool p
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int version;
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} hosts[] = {
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{ AMPERE_CHANNEL_GPFIFO_B, 0 },
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{ AMPERE_CHANNEL_GPFIFO_A, 0 },
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{ TURING_CHANNEL_GPFIFO_A, 0 },
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{ VOLTA_CHANNEL_GPFIFO_A, 0 },
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{ PASCAL_CHANNEL_GPFIFO_A, 0 },
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@ -365,8 +366,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
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if (ret)
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return ret;
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if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO &&
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chan->user.oclass < AMPERE_CHANNEL_GPFIFO_B) {
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if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) {
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struct {
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struct nvif_event_v0 base;
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struct nvif_chan_event_v0 host;
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@ -348,9 +348,6 @@ nouveau_accel_gr_init(struct nouveau_drm *drm)
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u64 runm;
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int ret;
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if (device->info.family >= NV_DEVICE_INFO_V0_AMPERE)
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return;
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/* Allocate channel that has access to the graphics engine. */
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runm = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_GR);
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if (!runm) {
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@ -473,6 +470,7 @@ nouveau_accel_init(struct nouveau_drm *drm)
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case PASCAL_CHANNEL_GPFIFO_A:
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case VOLTA_CHANNEL_GPFIFO_A:
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case TURING_CHANNEL_GPFIFO_A:
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case AMPERE_CHANNEL_GPFIFO_A:
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case AMPERE_CHANNEL_GPFIFO_B:
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ret = nvc0_fence_create(drm);
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break;
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@ -210,7 +210,7 @@ nv84_fence_create(struct nouveau_drm *drm)
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priv->base.context_new = nv84_fence_context_new;
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priv->base.context_del = nv84_fence_context_del;
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priv->base.uevent = drm->client.device.info.family < NV_DEVICE_INFO_V0_AMPERE;
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priv->base.uevent = true;
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mutex_init(&priv->mutex);
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@ -2590,6 +2590,7 @@ nv170_chipset = {
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.top = { 0x00000001, ga100_top_new },
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.vfn = { 0x00000001, ga100_vfn_new },
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.ce = { 0x000003ff, ga100_ce_new },
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.fifo = { 0x00000001, ga100_fifo_new },
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};
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static const struct nvkm_device_chip
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@ -23,6 +23,7 @@ nvkm-y += nvkm/engine/fifo/gm200.o
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nvkm-y += nvkm/engine/fifo/gp100.o
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nvkm-y += nvkm/engine/fifo/gv100.o
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nvkm-y += nvkm/engine/fifo/tu102.o
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nvkm-y += nvkm/engine/fifo/ga100.o
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nvkm-y += nvkm/engine/fifo/ga102.o
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nvkm-y += nvkm/engine/fifo/ucgrp.o
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@ -124,6 +124,7 @@ nvkm_fifo_init(struct nvkm_engine *engine)
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{
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struct nvkm_fifo *fifo = nvkm_fifo(engine);
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struct nvkm_runq *runq;
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struct nvkm_runl *runl;
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u32 mask = 0;
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if (fifo->func->init_pbdmas) {
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@ -136,7 +137,13 @@ nvkm_fifo_init(struct nvkm_engine *engine)
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runq->func->init(runq);
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}
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fifo->func->init(fifo);
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nvkm_runl_foreach(runl, fifo) {
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if (runl->func->init)
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runl->func->init(runl);
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}
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if (fifo->func->init)
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fifo->func->init(fifo);
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nvkm_inth_allow(&fifo->engine.subdev.inth);
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return 0;
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@ -243,7 +250,7 @@ nvkm_fifo_oneinit(struct nvkm_engine *engine)
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return ret;
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nvkm_runl_foreach(runl, fifo) {
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RUNL_DEBUG(runl, "");
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RUNL_DEBUG(runl, "chan:%06x", runl->chan);
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nvkm_runl_foreach_engn(engn, runl) {
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ENGN_DEBUG(engn, "");
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}
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@ -259,6 +266,14 @@ nvkm_fifo_oneinit(struct nvkm_engine *engine)
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}
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}
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/* Initialise non-stall intr handling. */
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if (fifo->func->nonstall_ctor) {
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ret = fifo->func->nonstall_ctor(fifo);
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if (ret) {
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nvkm_error(subdev, "nonstall %d\n", ret);
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}
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}
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/* Allocate USERD + BAR1 polling area. */
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if (fifo->func->chan.func->userd->bar == 1) {
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struct nvkm_vmm *bar1 = nvkm_bar_bar1_vmm(device);
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550
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
Normal file
550
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
Normal file
@ -0,0 +1,550 @@
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/*
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* Copyright 2021 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include "cgrp.h"
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#include "chan.h"
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#include "chid.h"
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#include "runl.h"
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#include "runq.h"
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#include <core/gpuobj.h>
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#include <subdev/top.h>
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#include <subdev/vfn.h>
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#include <nvif/class.h>
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/*TODO: allocate? */
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#define GA100_FIFO_NONSTALL_VECTOR 0
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static u32
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ga100_chan_doorbell_handle(struct nvkm_chan *chan)
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{
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return (chan->cgrp->runl->doorbell << 16) | chan->id;
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}
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static void
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ga100_chan_stop(struct nvkm_chan *chan)
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{
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struct nvkm_runl *runl = chan->cgrp->runl;
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nvkm_wr32(runl->fifo->engine.subdev.device, runl->chan + (chan->id * 4), 0x00000003);
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}
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static void
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ga100_chan_start(struct nvkm_chan *chan)
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{
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struct nvkm_runl *runl = chan->cgrp->runl;
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struct nvkm_device *device = runl->fifo->engine.subdev.device;
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const int gfid = 0;
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nvkm_wr32(device, runl->chan + (chan->id * 4), 0x00000002);
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nvkm_wr32(device, runl->addr + 0x0090, (gfid << 16) | chan->id); /* INTERNAL_DOORBELL. */
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}
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static void
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ga100_chan_unbind(struct nvkm_chan *chan)
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{
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struct nvkm_runl *runl = chan->cgrp->runl;
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nvkm_wr32(runl->fifo->engine.subdev.device, runl->chan + (chan->id * 4), 0xffffffff);
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}
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static int
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ga100_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv)
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{
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const u32 limit2 = ilog2(length / 8);
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nvkm_kmap(chan->inst);
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nvkm_wo32(chan->inst, 0x010, 0x0000face);
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nvkm_wo32(chan->inst, 0x030, 0x7ffff902);
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nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset));
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nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16));
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nvkm_wo32(chan->inst, 0x084, 0x20400000);
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nvkm_wo32(chan->inst, 0x094, 0x30000000 | devm);
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nvkm_wo32(chan->inst, 0x0e4, priv ? 0x00000020 : 0x00000000);
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nvkm_wo32(chan->inst, 0x0e8, chan->id);
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nvkm_wo32(chan->inst, 0x0f4, 0x00001000 | (priv ? 0x00000100 : 0x00000000));
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nvkm_wo32(chan->inst, 0x0f8, 0x80000000 | GA100_FIFO_NONSTALL_VECTOR);
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nvkm_mo32(chan->inst, 0x218, 0x00000000, 0x00000000);
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nvkm_done(chan->inst);
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return 0;
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}
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static const struct nvkm_chan_func_ramfc
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ga100_chan_ramfc = {
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.write = ga100_chan_ramfc_write,
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.devm = 0xfff,
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.priv = true,
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};
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const struct nvkm_chan_func
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ga100_chan = {
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.inst = &gf100_chan_inst,
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.userd = &gv100_chan_userd,
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.ramfc = &ga100_chan_ramfc,
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.unbind = ga100_chan_unbind,
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.start = ga100_chan_start,
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.stop = ga100_chan_stop,
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.preempt = gk110_chan_preempt,
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.doorbell_handle = ga100_chan_doorbell_handle,
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};
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static void
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ga100_cgrp_preempt(struct nvkm_cgrp *cgrp)
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{
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struct nvkm_runl *runl = cgrp->runl;
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nvkm_wr32(runl->fifo->engine.subdev.device, runl->addr + 0x098, 0x01000000 | cgrp->id);
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}
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const struct nvkm_cgrp_func
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ga100_cgrp = {
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.preempt = ga100_cgrp_preempt,
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};
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static int
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ga100_engn_cxid(struct nvkm_engn *engn, bool *cgid)
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{
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struct nvkm_runl *runl = engn->runl;
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struct nvkm_device *device = runl->fifo->engine.subdev.device;
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u32 stat = nvkm_rd32(device, runl->addr + 0x200 + engn->id * 0x40);
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ENGN_DEBUG(engn, "status %08x", stat);
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*cgid = true;
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switch ((stat & 0x0000e000) >> 13) {
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case 0 /* INVALID */: return -ENODEV;
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case 1 /* VALID */:
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case 5 /* SAVE */: return (stat & 0x00000fff);
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case 6 /* LOAD */: return (stat & 0x0fff0000) >> 16;
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case 7 /* SWITCH */:
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if (nvkm_engine_chsw_load(engn->engine))
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return (stat & 0x0fff0000) >> 16;
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return (stat & 0x00000fff);
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default:
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WARN_ON(1);
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break;
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}
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return -ENODEV;
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}
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const struct nvkm_engn_func
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ga100_engn = {
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.cxid = ga100_engn_cxid,
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.ctor = gk104_ectx_ctor,
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.bind = gv100_ectx_bind,
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};
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const struct nvkm_engn_func
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ga100_engn_ce = {
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.cxid = ga100_engn_cxid,
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.ctor = gv100_ectx_ce_ctor,
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.bind = gv100_ectx_ce_bind,
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};
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static bool
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ga100_runq_idle(struct nvkm_runq *runq)
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{
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struct nvkm_device *device = runq->fifo->engine.subdev.device;
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return !(nvkm_rd32(device, 0x04015c + (runq->id * 0x800)) & 0x0000e000);
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}
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static bool
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ga100_runq_intr_1(struct nvkm_runq *runq, struct nvkm_runl *runl)
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{
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struct nvkm_device *device = runq->fifo->engine.subdev.device;
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u32 inte = nvkm_rd32(device, 0x040180 + (runq->id * 0x800));
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u32 intr = nvkm_rd32(device, 0x040148 + (runq->id * 0x800));
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u32 stat = intr & inte;
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if (!stat) {
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RUNQ_DEBUG(runq, "inte1 %08x %08x", intr, inte);
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return false;
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}
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if (stat & 0x80000000) {
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u32 chid = nvkm_rd32(device, 0x040120 + (runq->id * 0x0800)) & runl->chid->mask;
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struct nvkm_chan *chan;
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unsigned long flags;
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RUNQ_ERROR(runq, "CTXNOTVALID chid:%d", chid);
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chan = nvkm_runl_chan_get_chid(runl, chid, &flags);
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if (chan) {
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nvkm_chan_error(chan, true);
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nvkm_chan_put(&chan, flags);
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}
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nvkm_mask(device, 0x0400ac + (runq->id * 0x800), 0x00030000, 0x00030000);
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stat &= ~0x80000000;
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}
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if (stat) {
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RUNQ_ERROR(runq, "intr1 %08x", stat);
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nvkm_wr32(device, 0x0401a0 + (runq->id * 0x800), stat);
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}
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nvkm_wr32(device, 0x040148 + (runq->id * 0x800), intr);
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return true;
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}
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static bool
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ga100_runq_intr_0(struct nvkm_runq *runq, struct nvkm_runl *runl)
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{
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struct nvkm_device *device = runq->fifo->engine.subdev.device;
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u32 inte = nvkm_rd32(device, 0x040170 + (runq->id * 0x800));
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u32 intr = nvkm_rd32(device, 0x040108 + (runq->id * 0x800));
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u32 stat = intr & inte;
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if (!stat) {
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RUNQ_DEBUG(runq, "inte0 %08x %08x", intr, inte);
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return false;
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}
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/*TODO: expand on this when fixing up gf100's version. */
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if (stat & 0xc6afe000) {
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u32 chid = nvkm_rd32(device, 0x040120 + (runq->id * 0x0800)) & runl->chid->mask;
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struct nvkm_chan *chan;
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unsigned long flags;
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RUNQ_ERROR(runq, "intr0 %08x", stat);
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chan = nvkm_runl_chan_get_chid(runl, chid, &flags);
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if (chan) {
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nvkm_chan_error(chan, true);
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nvkm_chan_put(&chan, flags);
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}
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stat &= ~0xc6afe000;
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}
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if (stat) {
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RUNQ_ERROR(runq, "intr0 %08x", stat);
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nvkm_wr32(device, 0x040190 + (runq->id * 0x800), stat);
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}
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nvkm_wr32(device, 0x040108 + (runq->id * 0x800), intr);
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return true;
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}
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static bool
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ga100_runq_intr(struct nvkm_runq *runq, struct nvkm_runl *runl)
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{
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bool intr0 = ga100_runq_intr_0(runq, runl);
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bool intr1 = ga100_runq_intr_1(runq, runl);
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return intr0 || intr1;
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}
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static void
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ga100_runq_init(struct nvkm_runq *runq)
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{
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struct nvkm_device *device = runq->fifo->engine.subdev.device;
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nvkm_wr32(device, 0x040108 + (runq->id * 0x800), 0xffffffff); /* INTR_0 */
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nvkm_wr32(device, 0x040148 + (runq->id * 0x800), 0xffffffff); /* INTR_1 */
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nvkm_wr32(device, 0x040170 + (runq->id * 0x800), 0xffffffff); /* INTR_0_EN_SET_TREE */
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nvkm_wr32(device, 0x040180 + (runq->id * 0x800), 0xffffffff); /* INTR_1_EN_SET_TREE */
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}
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const struct nvkm_runq_func
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ga100_runq = {
|
||||
.init = ga100_runq_init,
|
||||
.intr = ga100_runq_intr,
|
||||
.idle = ga100_runq_idle,
|
||||
};
|
||||
|
||||
static bool
|
||||
ga100_runl_preempt_pending(struct nvkm_runl *runl)
|
||||
{
|
||||
return nvkm_rd32(runl->fifo->engine.subdev.device, runl->addr + 0x098) & 0x00100000;
|
||||
}
|
||||
|
||||
static void
|
||||
ga100_runl_preempt(struct nvkm_runl *runl)
|
||||
{
|
||||
nvkm_wr32(runl->fifo->engine.subdev.device, runl->addr + 0x098, 0x00000000);
|
||||
}
|
||||
|
||||
static void
|
||||
ga100_runl_allow(struct nvkm_runl *runl, u32 engm)
|
||||
{
|
||||
nvkm_mask(runl->fifo->engine.subdev.device, runl->addr + 0x094, 0x00000001, 0x00000000);
|
||||
}
|
||||
|
||||
static void
|
||||
ga100_runl_block(struct nvkm_runl *runl, u32 engm)
|
||||
{
|
||||
nvkm_mask(runl->fifo->engine.subdev.device, runl->addr + 0x094, 0x00000001, 0x00000001);
|
||||
}
|
||||
|
||||
static bool
|
||||
ga100_runl_pending(struct nvkm_runl *runl)
|
||||
{
|
||||
struct nvkm_device *device = runl->fifo->engine.subdev.device;
|
||||
|
||||
return nvkm_rd32(device, runl->addr + 0x08c) & 0x00008000;
|
||||
}
|
||||
|
||||
static void
|
||||
ga100_runl_commit(struct nvkm_runl *runl, struct nvkm_memory *memory, u32 start, int count)
|
||||
{
|
||||
struct nvkm_device *device = runl->fifo->engine.subdev.device;
|
||||
u64 addr = nvkm_memory_addr(memory) + start;
|
||||
|
||||
nvkm_wr32(device, runl->addr + 0x080, lower_32_bits(addr));
|
||||
nvkm_wr32(device, runl->addr + 0x084, upper_32_bits(addr));
|
||||
nvkm_wr32(device, runl->addr + 0x088, count);
|
||||
}
|
||||
|
||||
static irqreturn_t
|
||||
ga100_runl_intr(struct nvkm_inth *inth)
|
||||
{
|
||||
struct nvkm_runl *runl = container_of(inth, typeof(*runl), inth);
|
||||
struct nvkm_engn *engn;
|
||||
struct nvkm_device *device = runl->fifo->engine.subdev.device;
|
||||
u32 inte = nvkm_rd32(device, runl->addr + 0x120);
|
||||
u32 intr = nvkm_rd32(device, runl->addr + 0x100);
|
||||
u32 stat = intr & inte;
|
||||
u32 info;
|
||||
|
||||
if (!stat) {
|
||||
RUNL_DEBUG(runl, "inte %08x %08x", intr, inte);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
if (stat & 0x00000007) {
|
||||
nvkm_runl_foreach_engn_cond(engn, runl, stat & BIT(engn->id)) {
|
||||
info = nvkm_rd32(device, runl->addr + 0x224 + (engn->id * 0x40));
|
||||
|
||||
tu102_fifo_intr_ctxsw_timeout_info(engn, info);
|
||||
|
||||
nvkm_wr32(device, runl->addr + 0x100, BIT(engn->id));
|
||||
stat &= ~BIT(engn->id);
|
||||
}
|
||||
}
|
||||
|
||||
if (stat & 0x00000300) {
|
||||
nvkm_wr32(device, runl->addr + 0x100, stat & 0x00000300);
|
||||
stat &= ~0x00000300;
|
||||
}
|
||||
|
||||
if (stat & 0x00010000) {
|
||||
if (runl->runq[0]) {
|
||||
if (runl->runq[0]->func->intr(runl->runq[0], runl))
|
||||
stat &= ~0x00010000;
|
||||
}
|
||||
}
|
||||
|
||||
if (stat & 0x00020000) {
|
||||
if (runl->runq[1]) {
|
||||
if (runl->runq[1]->func->intr(runl->runq[1], runl))
|
||||
stat &= ~0x00020000;
|
||||
}
|
||||
}
|
||||
|
||||
if (stat) {
|
||||
RUNL_ERROR(runl, "intr %08x", stat);
|
||||
nvkm_wr32(device, runl->addr + 0x140, stat);
|
||||
}
|
||||
|
||||
nvkm_wr32(device, runl->addr + 0x180, 0x00000001);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void
|
||||
ga100_runl_fini(struct nvkm_runl *runl)
|
||||
{
|
||||
nvkm_mask(runl->fifo->engine.subdev.device, runl->addr + 0x300, 0x80000000, 0x00000000);
|
||||
nvkm_inth_block(&runl->inth);
|
||||
}
|
||||
|
||||
static void
|
||||
ga100_runl_init(struct nvkm_runl *runl)
|
||||
{
|
||||
struct nvkm_fifo *fifo = runl->fifo;
|
||||
struct nvkm_runq *runq;
|
||||
struct nvkm_device *device = fifo->engine.subdev.device;
|
||||
int i;
|
||||
|
||||
/* Submit NULL runlist and preempt. */
|
||||
nvkm_wr32(device, runl->addr + 0x088, 0x00000000);
|
||||
runl->func->preempt(runl);
|
||||
|
||||
/* Enable doorbell. */
|
||||
nvkm_mask(device, runl->addr + 0x300, 0x80000000, 0x80000000);
|
||||
|
||||
nvkm_wr32(device, runl->addr + 0x100, 0xffffffff); /* INTR_0 */
|
||||
nvkm_wr32(device, runl->addr + 0x140, 0xffffffff); /* INTR_0_EN_CLEAR_TREE(0) */
|
||||
nvkm_wr32(device, runl->addr + 0x120, 0x000f1307); /* INTR_0_EN_SET_TREE(0) */
|
||||
nvkm_wr32(device, runl->addr + 0x148, 0xffffffff); /* INTR_0_EN_CLEAR_TREE(1) */
|
||||
nvkm_wr32(device, runl->addr + 0x128, 0x00000000); /* INTR_0_EN_SET_TREE(1) */
|
||||
|
||||
/* Init PBDMA(s). */
|
||||
for (i = 0; i < runl->runq_nr; i++) {
|
||||
runq = runl->runq[i];
|
||||
runq->func->init(runq);
|
||||
}
|
||||
|
||||
nvkm_inth_allow(&runl->inth);
|
||||
}
|
||||
|
||||
const struct nvkm_runl_func
|
||||
ga100_runl = {
|
||||
.init = ga100_runl_init,
|
||||
.fini = ga100_runl_fini,
|
||||
.size = 16,
|
||||
.update = nv50_runl_update,
|
||||
.insert_cgrp = gv100_runl_insert_cgrp,
|
||||
.insert_chan = gv100_runl_insert_chan,
|
||||
.commit = ga100_runl_commit,
|
||||
.wait = nv50_runl_wait,
|
||||
.pending = ga100_runl_pending,
|
||||
.block = ga100_runl_block,
|
||||
.allow = ga100_runl_allow,
|
||||
.preempt = ga100_runl_preempt,
|
||||
.preempt_pending = ga100_runl_preempt_pending,
|
||||
};
|
||||
|
||||
static int
|
||||
ga100_runl_new(struct nvkm_fifo *fifo, int id, u32 addr, struct nvkm_runl **prunl)
|
||||
{
|
||||
struct nvkm_device *device = fifo->engine.subdev.device;
|
||||
struct nvkm_runl *runl;
|
||||
u32 chcfg = nvkm_rd32(device, addr + 0x004);
|
||||
u32 chnum = 1 << (chcfg & 0x0000000f);
|
||||
u32 chaddr = (chcfg & 0xfffffff0);
|
||||
u32 dbcfg = nvkm_rd32(device, addr + 0x008);
|
||||
u32 vector = nvkm_rd32(device, addr + 0x160);
|
||||
int i, ret;
|
||||
|
||||
runl = *prunl = nvkm_runl_new(fifo, id, addr, chnum);
|
||||
if (IS_ERR(runl))
|
||||
return PTR_ERR(runl);
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
u32 pbcfg = nvkm_rd32(device, addr + 0x010 + (i * 0x04));
|
||||
if (pbcfg & 0x80000000) {
|
||||
runl->runq[runl->runq_nr] =
|
||||
nvkm_runq_new(fifo, ((pbcfg & 0x03fffc00) - 0x040000) / 0x800);
|
||||
if (!runl->runq[runl->runq_nr])
|
||||
return -ENOMEM;
|
||||
|
||||
runl->runq_nr++;
|
||||
}
|
||||
}
|
||||
|
||||
ret = nvkm_inth_add(&device->vfn->intr, vector & 0x00000fff, NVKM_INTR_PRIO_NORMAL,
|
||||
&fifo->engine.subdev, ga100_runl_intr, &runl->inth);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
runl->chan = chaddr;
|
||||
runl->doorbell = dbcfg >> 16;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t
|
||||
ga100_fifo_nonstall_intr(struct nvkm_inth *inth)
|
||||
{
|
||||
struct nvkm_fifo *fifo = container_of(inth, typeof(*fifo), nonstall.intr);
|
||||
|
||||
nvkm_event_ntfy(&fifo->nonstall.event, 0, NVKM_FIFO_NONSTALL_EVENT);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void
|
||||
ga100_fifo_nonstall_block(struct nvkm_event *event, int type, int index)
|
||||
{
|
||||
struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), nonstall.event);
|
||||
|
||||
nvkm_inth_block(&fifo->nonstall.intr);
|
||||
}
|
||||
|
||||
static void
|
||||
ga100_fifo_nonstall_allow(struct nvkm_event *event, int type, int index)
|
||||
{
|
||||
struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), nonstall.event);
|
||||
|
||||
nvkm_inth_allow(&fifo->nonstall.intr);
|
||||
}
|
||||
|
||||
const struct nvkm_event_func
|
||||
ga100_fifo_nonstall = {
|
||||
.init = ga100_fifo_nonstall_allow,
|
||||
.fini = ga100_fifo_nonstall_block,
|
||||
};
|
||||
|
||||
int
|
||||
ga100_fifo_nonstall_ctor(struct nvkm_fifo *fifo)
|
||||
{
|
||||
return nvkm_inth_add(&fifo->engine.subdev.device->vfn->intr, GA100_FIFO_NONSTALL_VECTOR,
|
||||
NVKM_INTR_PRIO_NORMAL, &fifo->engine.subdev, ga100_fifo_nonstall_intr,
|
||||
&fifo->nonstall.intr);
|
||||
}
|
||||
|
||||
int
|
||||
ga100_fifo_runl_ctor(struct nvkm_fifo *fifo)
|
||||
{
|
||||
struct nvkm_device *device = fifo->engine.subdev.device;
|
||||
struct nvkm_top_device *tdev;
|
||||
struct nvkm_runl *runl;
|
||||
int id = 0, ret;
|
||||
|
||||
nvkm_list_foreach(tdev, &device->top->device, head, tdev->runlist >= 0) {
|
||||
runl = nvkm_runl_get(fifo, -1, tdev->runlist);
|
||||
if (!runl) {
|
||||
ret = ga100_runl_new(fifo, id++, tdev->runlist, &runl);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (tdev->engine < 0)
|
||||
continue;
|
||||
|
||||
nvkm_runl_add(runl, tdev->engine, (tdev->type == NVKM_ENGINE_CE) ?
|
||||
fifo->func->engn_ce : fifo->func->engn, tdev->type, tdev->inst);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct nvkm_fifo_func
|
||||
ga100_fifo = {
|
||||
.runl_ctor = ga100_fifo_runl_ctor,
|
||||
.mmu_fault = &tu102_fifo_mmu_fault,
|
||||
.nonstall_ctor = ga100_fifo_nonstall_ctor,
|
||||
.nonstall = &ga100_fifo_nonstall,
|
||||
.runl = &ga100_runl,
|
||||
.runq = &ga100_runq,
|
||||
.engn = &ga100_engn,
|
||||
.engn_ce = &ga100_engn_ce,
|
||||
.cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &ga100_cgrp, .force = true },
|
||||
.chan = {{ 0, 0, AMPERE_CHANNEL_GPFIFO_A }, &ga100_chan },
|
||||
};
|
||||
|
||||
int
|
||||
ga100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
|
||||
struct nvkm_fifo **pfifo)
|
||||
{
|
||||
return nvkm_fifo_new_(&ga100_fifo, device, type, inst, pfifo);
|
||||
}
|
||||
@ -19,281 +19,27 @@
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#define ga102_fifo(p) container_of((p), struct ga102_fifo, base.engine)
|
||||
#define ga102_chan(p) container_of((p), struct ga102_chan, object)
|
||||
#include <engine/fifo.h>
|
||||
#include "priv.h"
|
||||
|
||||
#include <core/memory.h>
|
||||
#include <subdev/mmu.h>
|
||||
#include <subdev/timer.h>
|
||||
#include <subdev/top.h>
|
||||
|
||||
#include <nvif/cl0080.h>
|
||||
#include <nvif/if0020.h>
|
||||
#include <nvif/class.h>
|
||||
|
||||
struct ga102_fifo {
|
||||
struct nvkm_fifo base;
|
||||
};
|
||||
|
||||
struct ga102_chan {
|
||||
struct nvkm_object object;
|
||||
|
||||
struct {
|
||||
u32 runl;
|
||||
u32 chan;
|
||||
} ctrl;
|
||||
|
||||
struct nvkm_memory *mthd;
|
||||
struct nvkm_memory *inst;
|
||||
struct nvkm_memory *user;
|
||||
struct nvkm_memory *runl;
|
||||
|
||||
struct nvkm_vmm *vmm;
|
||||
};
|
||||
|
||||
static int
|
||||
ga102_chan_sclass(struct nvkm_object *object, int index, struct nvkm_oclass *oclass)
|
||||
{
|
||||
if (index == 0) {
|
||||
oclass->ctor = nvkm_object_new;
|
||||
oclass->base = (struct nvkm_sclass) { -1, -1, AMPERE_DMA_COPY_B };
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int
|
||||
ga102_chan_map(struct nvkm_object *object, void *argv, u32 argc,
|
||||
enum nvkm_object_map *type, u64 *addr, u64 *size)
|
||||
{
|
||||
struct ga102_chan *chan = ga102_chan(object);
|
||||
struct nvkm_device *device = chan->object.engine->subdev.device;
|
||||
u64 bar2 = nvkm_memory_bar2(chan->user);
|
||||
|
||||
if (bar2 == ~0ULL)
|
||||
return -EFAULT;
|
||||
|
||||
*type = NVKM_OBJECT_MAP_IO;
|
||||
*addr = device->func->resource_addr(device, 3) + bar2;
|
||||
*size = 0x1000;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
ga102_chan_fini(struct nvkm_object *object, bool suspend)
|
||||
{
|
||||
struct ga102_chan *chan = ga102_chan(object);
|
||||
struct nvkm_device *device = chan->object.engine->subdev.device;
|
||||
|
||||
nvkm_wr32(device, chan->ctrl.chan, 0x00000003);
|
||||
|
||||
nvkm_wr32(device, chan->ctrl.runl + 0x098, 0x01000000);
|
||||
nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, chan->ctrl.runl + 0x098) & 0x00100000))
|
||||
break;
|
||||
);
|
||||
|
||||
nvkm_wr32(device, chan->ctrl.runl + 0x088, 0);
|
||||
|
||||
nvkm_wr32(device, chan->ctrl.chan, 0xffffffff);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
ga102_chan_init(struct nvkm_object *object)
|
||||
{
|
||||
struct ga102_chan *chan = ga102_chan(object);
|
||||
struct nvkm_device *device = chan->object.engine->subdev.device;
|
||||
|
||||
nvkm_mask(device, chan->ctrl.runl + 0x300, 0x80000000, 0x80000000);
|
||||
|
||||
nvkm_wr32(device, chan->ctrl.runl + 0x080, lower_32_bits(nvkm_memory_addr(chan->runl)));
|
||||
nvkm_wr32(device, chan->ctrl.runl + 0x084, upper_32_bits(nvkm_memory_addr(chan->runl)));
|
||||
nvkm_wr32(device, chan->ctrl.runl + 0x088, 2);
|
||||
|
||||
nvkm_wr32(device, chan->ctrl.chan, 0x00000002);
|
||||
nvkm_wr32(device, chan->ctrl.runl + 0x0090, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void *
|
||||
ga102_chan_dtor(struct nvkm_object *object)
|
||||
{
|
||||
struct ga102_chan *chan = ga102_chan(object);
|
||||
|
||||
if (chan->vmm) {
|
||||
nvkm_vmm_part(chan->vmm, chan->inst);
|
||||
nvkm_vmm_unref(&chan->vmm);
|
||||
}
|
||||
|
||||
nvkm_memory_unref(&chan->runl);
|
||||
nvkm_memory_unref(&chan->user);
|
||||
nvkm_memory_unref(&chan->inst);
|
||||
nvkm_memory_unref(&chan->mthd);
|
||||
return chan;
|
||||
}
|
||||
|
||||
static const struct nvkm_object_func
|
||||
ga102_chan = {
|
||||
.dtor = ga102_chan_dtor,
|
||||
.init = ga102_chan_init,
|
||||
.fini = ga102_chan_fini,
|
||||
.map = ga102_chan_map,
|
||||
.sclass = ga102_chan_sclass,
|
||||
};
|
||||
|
||||
static int
|
||||
ga102_chan_new(struct nvkm_device *device,
|
||||
const struct nvkm_oclass *oclass, void *argv, u32 argc, struct nvkm_object **pobject)
|
||||
{
|
||||
struct nvif_chan_v0 *args = argv;
|
||||
struct nvkm_top_device *tdev;
|
||||
struct nvkm_vmm *vmm;
|
||||
struct nvkm_memory *userd;
|
||||
struct ga102_chan *chan;
|
||||
int ret;
|
||||
|
||||
if (argc != sizeof(*args))
|
||||
return -ENOSYS;
|
||||
|
||||
vmm = nvkm_uvmm_search(oclass->client, args->vmm);
|
||||
if (IS_ERR(vmm))
|
||||
return PTR_ERR(vmm);
|
||||
|
||||
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
|
||||
return -ENOMEM;
|
||||
|
||||
nvkm_object_ctor(&ga102_chan, oclass, &chan->object);
|
||||
*pobject = &chan->object;
|
||||
|
||||
list_for_each_entry(tdev, &device->top->device, head) {
|
||||
if (tdev->type == NVKM_ENGINE_CE) {
|
||||
chan->ctrl.runl = tdev->runlist;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!chan->ctrl.runl)
|
||||
return -ENODEV;
|
||||
|
||||
chan->ctrl.chan = nvkm_rd32(device, chan->ctrl.runl + 0x004) & 0xfffffff0;
|
||||
|
||||
args->chid = 0;
|
||||
args->inst = 0;
|
||||
args->token = nvkm_rd32(device, chan->ctrl.runl + 0x008) & 0xffff0000;
|
||||
|
||||
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, true, &chan->mthd);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, true, &chan->inst);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nvkm_kmap(chan->inst);
|
||||
nvkm_wo32(chan->inst, 0x010, 0x0000face);
|
||||
nvkm_wo32(chan->inst, 0x030, 0x7ffff902);
|
||||
nvkm_wo32(chan->inst, 0x048, lower_32_bits(args->offset));
|
||||
nvkm_wo32(chan->inst, 0x04c, upper_32_bits(args->offset) |
|
||||
(order_base_2(args->length / 8) << 16));
|
||||
nvkm_wo32(chan->inst, 0x084, 0x20400000);
|
||||
nvkm_wo32(chan->inst, 0x094, 0x30000001);
|
||||
nvkm_wo32(chan->inst, 0x0ac, 0x00020000);
|
||||
nvkm_wo32(chan->inst, 0x0e4, 0x00000000);
|
||||
nvkm_wo32(chan->inst, 0x0e8, 0);
|
||||
nvkm_wo32(chan->inst, 0x0f4, 0x00001000);
|
||||
nvkm_wo32(chan->inst, 0x0f8, 0x10003080);
|
||||
nvkm_mo32(chan->inst, 0x218, 0x00000000, 0x00000000);
|
||||
nvkm_wo32(chan->inst, 0x220, lower_32_bits(nvkm_memory_bar2(chan->mthd)));
|
||||
nvkm_wo32(chan->inst, 0x224, upper_32_bits(nvkm_memory_bar2(chan->mthd)));
|
||||
nvkm_done(chan->inst);
|
||||
|
||||
userd = nvkm_umem_search(oclass->client, args->huserd);
|
||||
if (IS_ERR(userd))
|
||||
return PTR_ERR(userd);
|
||||
|
||||
ret = nvkm_memory_kmap(userd, &chan->user);
|
||||
nvkm_memory_unref(&userd);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, true, &chan->runl);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nvkm_kmap(chan->runl);
|
||||
nvkm_wo32(chan->runl, 0x00, 0x80030001);
|
||||
nvkm_wo32(chan->runl, 0x04, 1);
|
||||
nvkm_wo32(chan->runl, 0x08, 0);
|
||||
nvkm_wo32(chan->runl, 0x0c, 0x00000000);
|
||||
nvkm_wo32(chan->runl, 0x10, lower_32_bits(nvkm_memory_addr(chan->user)));
|
||||
nvkm_wo32(chan->runl, 0x14, upper_32_bits(nvkm_memory_addr(chan->user)));
|
||||
nvkm_wo32(chan->runl, 0x18, lower_32_bits(nvkm_memory_addr(chan->inst)));
|
||||
nvkm_wo32(chan->runl, 0x1c, upper_32_bits(nvkm_memory_addr(chan->inst)));
|
||||
nvkm_done(chan->runl);
|
||||
|
||||
ret = nvkm_vmm_join(vmm, chan->inst);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
chan->vmm = nvkm_vmm_ref(vmm);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct nvkm_device_oclass
|
||||
ga102_chan_oclass = {
|
||||
.ctor = ga102_chan_new,
|
||||
};
|
||||
|
||||
static int
|
||||
ga102_fifo_sclass(struct nvkm_oclass *oclass, int index, const struct nvkm_device_oclass **class)
|
||||
{
|
||||
if (index == 0) {
|
||||
oclass->base = (struct nvkm_sclass) { 0, 0, AMPERE_CHANNEL_GPFIFO_B };
|
||||
*class = &ga102_chan_oclass;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int
|
||||
ga102_fifo_info(struct nvkm_engine *engine, u64 mthd, u64 *data)
|
||||
{
|
||||
switch (mthd) {
|
||||
case NV_DEVICE_HOST_CHANNELS: *data = 1; return 0;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static void *
|
||||
ga102_fifo_dtor(struct nvkm_engine *engine)
|
||||
{
|
||||
return ga102_fifo(engine);
|
||||
}
|
||||
|
||||
static const struct nvkm_engine_func
|
||||
static const struct nvkm_fifo_func
|
||||
ga102_fifo = {
|
||||
.dtor = ga102_fifo_dtor,
|
||||
.info = ga102_fifo_info,
|
||||
.base.sclass = ga102_fifo_sclass,
|
||||
.runl_ctor = ga100_fifo_runl_ctor,
|
||||
.mmu_fault = &tu102_fifo_mmu_fault,
|
||||
.nonstall_ctor = ga100_fifo_nonstall_ctor,
|
||||
.nonstall = &ga100_fifo_nonstall,
|
||||
.runl = &ga100_runl,
|
||||
.runq = &ga100_runq,
|
||||
.engn = &ga100_engn,
|
||||
.engn_ce = &ga100_engn_ce,
|
||||
.cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &ga100_cgrp, .force = true },
|
||||
.chan = {{ 0, 0, AMPERE_CHANNEL_GPFIFO_B }, &ga100_chan },
|
||||
};
|
||||
|
||||
int
|
||||
ga102_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
|
||||
struct nvkm_fifo **pfifo)
|
||||
{
|
||||
struct ga102_fifo *fifo;
|
||||
|
||||
if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
|
||||
return -ENOMEM;
|
||||
|
||||
nvkm_engine_ctor(&ga102_fifo, device, type, inst, true, &fifo->base.engine);
|
||||
*pfifo = &fifo->base;
|
||||
return 0;
|
||||
return nvkm_fifo_new_(&ga102_fifo, device, type, inst, pfifo);
|
||||
}
|
||||
|
||||
@ -37,6 +37,7 @@ struct nvkm_fifo_func {
|
||||
void (*pause)(struct nvkm_fifo *, unsigned long *);
|
||||
void (*start)(struct nvkm_fifo *, unsigned long *);
|
||||
|
||||
int (*nonstall_ctor)(struct nvkm_fifo *);
|
||||
const struct nvkm_event_func *nonstall;
|
||||
|
||||
const struct nvkm_runl_func *runl;
|
||||
@ -191,6 +192,16 @@ extern const struct nvkm_chan_func_ramfc gv100_chan_ramfc;
|
||||
void tu102_fifo_intr_ctxsw_timeout_info(struct nvkm_engn *, u32 info);
|
||||
extern const struct nvkm_fifo_func_mmu_fault tu102_fifo_mmu_fault;
|
||||
|
||||
int ga100_fifo_runl_ctor(struct nvkm_fifo *);
|
||||
int ga100_fifo_nonstall_ctor(struct nvkm_fifo *);
|
||||
extern const struct nvkm_event_func ga100_fifo_nonstall;
|
||||
extern const struct nvkm_runl_func ga100_runl;
|
||||
extern const struct nvkm_runq_func ga100_runq;
|
||||
extern const struct nvkm_engn_func ga100_engn;
|
||||
extern const struct nvkm_engn_func ga100_engn_ce;
|
||||
extern const struct nvkm_cgrp_func ga100_cgrp;
|
||||
extern const struct nvkm_chan_func ga100_chan;
|
||||
|
||||
int nvkm_uchan_new(struct nvkm_fifo *, struct nvkm_cgrp *, const struct nvkm_oclass *,
|
||||
void *argv, u32 argc, struct nvkm_object **);
|
||||
int nvkm_ucgrp_new(struct nvkm_fifo *, const struct nvkm_oclass *, void *argv, u32 argc,
|
||||
|
||||
@ -308,6 +308,9 @@ nvkm_runl_block(struct nvkm_runl *runl)
|
||||
void
|
||||
nvkm_runl_fini(struct nvkm_runl *runl)
|
||||
{
|
||||
if (runl->func->fini)
|
||||
runl->func->fini(runl);
|
||||
|
||||
flush_work(&runl->work);
|
||||
}
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#ifndef __NVKM_RUNL_H__
|
||||
#define __NVKM_RUNL_H__
|
||||
#include <core/os.h>
|
||||
#include <core/intr.h>
|
||||
struct nvkm_cctx;
|
||||
struct nvkm_cgrp;
|
||||
struct nvkm_chan;
|
||||
@ -36,6 +36,8 @@ struct nvkm_engn {
|
||||
|
||||
struct nvkm_runl {
|
||||
const struct nvkm_runl_func {
|
||||
void (*init)(struct nvkm_runl *);
|
||||
void (*fini)(struct nvkm_runl *);
|
||||
int runqs;
|
||||
u8 size;
|
||||
int (*update)(struct nvkm_runl *);
|
||||
@ -53,6 +55,8 @@ struct nvkm_runl {
|
||||
struct nvkm_fifo *fifo;
|
||||
int id;
|
||||
u32 addr;
|
||||
u32 chan;
|
||||
u16 doorbell;
|
||||
|
||||
struct nvkm_chid *cgid;
|
||||
#define NVKM_CHAN_EVENT_ERRORED BIT(0)
|
||||
@ -63,6 +67,8 @@ struct nvkm_runl {
|
||||
struct nvkm_runq *runq[2];
|
||||
int runq_nr;
|
||||
|
||||
struct nvkm_inth inth;
|
||||
|
||||
struct list_head cgrps;
|
||||
int cgrp_nr;
|
||||
int chan_nr;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user