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clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4

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R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220425064201.459633-5-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Yoshihiro Shimoda 2022-04-25 15:41:58 +09:00 committed by Geert Uytterhoeven
parent 5d33481f54
commit 7f906eaa95
4 changed files with 24 additions and 16 deletions
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12
drivers/clk/renesas/r8a779a0-cpg-mssr.c
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@ -244,7 +244,7 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
/*
* MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
* 14 13 (MHz) 21 31
* --------------------------------------------------------
* ----------------------------------------------------------------
* 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16
* 0 1 20 x 1 x106 x180 x106 x120 x160 /19
* 1 0 Prohibited setting
@ -253,11 +253,11 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
{ 1, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 16, },
{ 1, 106, 1, 0, 0, 0, 0, 160, 1, 0, 0, 19, },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 32, },
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
{ 1, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 16, },
{ 1, 106, 1, 0, 0, 0, 0, 120, 1, 160, 1, 0, 0, 19, },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 32, },
};

20
drivers/clk/renesas/r8a779f0-cpg-mssr.c
View File

@ -143,23 +143,23 @@ static const unsigned int r8a779f0_crit_mod_clks[] __initconst = {
* CPG Clock Data
*/
/*
* MD EXTAL PLL1 PLL2 PLL3 PLL5 PLL6 OSC
* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
* 14 13 (MHz)
* ----------------------------------------------------------------
* 0 0 16 / 1 x200 x150 x200 x200 x134 /15
* 0 1 20 / 1 x160 x120 x160 x160 x106 /19
* ------------------------------------------------------------------------
* 0 0 16 / 1 x200 x150 x200 n/a x200 x134 /15
* 0 1 20 / 1 x160 x120 x160 n/a x160 x106 /19
* 1 0 Prohibited setting
* 1 1 40 / 2 x160 x120 x160 x160 x106 /38
* 1 1 40 / 2 x160 x120 x160 n/a x160 x106 /38
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
{ 1, 200, 1, 150, 1, 200, 1, 200, 1, 134, 1, 15, },
{ 1, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 19, },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 38, },
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
{ 1, 200, 1, 150, 1, 200, 1, 0, 0, 200, 1, 134, 1, 15, },
{ 1, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 19, },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 38, },
};
static int __init r8a779f0_cpg_mssr_init(struct device *dev)

5
drivers/clk/renesas/rcar-gen4-cpg.c
View File

@ -215,6 +215,11 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
div = cpg_pll_config->pll3_div;
break;
case CLK_TYPE_GEN4_PLL4:
mult = cpg_pll_config->pll4_mult;
div = cpg_pll_config->pll4_div;
break;
case CLK_TYPE_GEN4_PLL5:
mult = cpg_pll_config->pll5_mult;
div = cpg_pll_config->pll5_div;

3
drivers/clk/renesas/rcar-gen4-cpg.h
View File

@ -16,6 +16,7 @@ enum rcar_gen4_clk_types {
CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
CLK_TYPE_GEN4_PLL3,
CLK_TYPE_GEN4_PLL5,
CLK_TYPE_GEN4_PLL4,
CLK_TYPE_GEN4_PLL6,
CLK_TYPE_GEN4_SDSRC,
CLK_TYPE_GEN4_SDH,
@ -56,6 +57,8 @@ struct rcar_gen4_cpg_pll_config {
u8 pll2_div;
u8 pll3_mult;
u8 pll3_div;
u8 pll4_mult;
u8 pll4_div;
u8 pll5_mult;
u8 pll5_div;
u8 pll6_mult;