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MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option

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Use a new config option to enable R4600 V1 index I-cacheop workaround
and remove define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Thomas Bogendoerfer
2020-08-24 18:32:43 +02:00
parent 8c2ede45ed
commit 802b83627f
15 changed files with 12 additions and 24 deletions
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1
arch/mips/include/asm/mach-rm/war.h
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@ -12,7 +12,6 @@
* The RM200C seems to have been shipped only with V2.0 R4600s
*/
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 1
#define BCM1250_M3_WAR 0