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drm/amd/powerplay: fix pre-check condition for setting clock range

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This fix will handle some MP1 FW issue like as mclk dpm table in renoir has a reverse
dpm clock layout and a zero frequency dpm level as following case.

cat pp_dpm_mclk
0: 1200Mhz
1: 1200Mhz
2: 800Mhz
3: 0Mhz

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
This commit is contained in:
Prike Liang 2020-03-02 09:36:15 +08:00 committed by Alex Deucher
parent a0275dfc82
commit 80381d40c9
2 changed files with 1 additions and 4 deletions
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2
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
View File

@ -222,7 +222,7 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
{
int ret = 0;
if (min <= 0 && max <= 0)
if (min < 0 && max < 0)
return -EINVAL;
if (!smu_clk_dpm_is_enabled(smu, clk_type))

3
drivers/gpu/drm/amd/powerplay/smu_v12_0.c
View File

@ -458,9 +458,6 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_
{
int ret = 0;
if (max < min)
return -EINVAL;
switch (clk_type) {
case SMU_GFXCLK:
case SMU_SCLK: