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ath9k: Enable extended synch for AR9485 to fix L0s recovery issue

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Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Vasanthakumar Thiagarajan 2010-12-06 04:27:42 -08:00 committed by John W. Linville
parent 7f1c7a6ac5
commit 8060e169e0
5 changed files with 23 additions and 0 deletions
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1
drivers/net/wireless/ath/ath.h
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@ -131,6 +131,7 @@ struct ath_bus_ops {
void (*read_cachesize)(struct ath_common *common, int *csz); void (*read_cachesize)(struct ath_common *common, int *csz);
bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
void (*bt_coex_prep)(struct ath_common *common); void (*bt_coex_prep)(struct ath_common *common);
void (*extn_synch_en)(struct ath_common *common);
}; };
struct ath_common { struct ath_common {

5
drivers/net/wireless/ath/ath9k/hw.c
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@ -1971,6 +1971,11 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
if (AR_SREV_9485_10(ah)) {
pCap->pcie_lcr_extsync_en = true;
pCap->pcie_lcr_offset = 0x80;
}
return 0; return 0;
} }

2
drivers/net/wireless/ath/ath9k/hw.h
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@ -209,6 +209,8 @@ struct ath9k_hw_capabilities {
u8 rx_status_len; u8 rx_status_len;
u8 tx_desc_len; u8 tx_desc_len;
u8 txs_len; u8 txs_len;
u16 pcie_lcr_offset;
bool pcie_lcr_extsync_en;
}; };
struct ath9k_ops_config { struct ath9k_ops_config {

3
drivers/net/wireless/ath/ath9k/main.c
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@ -1179,6 +1179,9 @@ static int ath9k_start(struct ieee80211_hw *hw)
pm_qos_update_request(&sc->pm_qos_req, 55); pm_qos_update_request(&sc->pm_qos_req, 55);
if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
common->bus_ops->extn_synch_en(common);
mutex_unlock: mutex_unlock:
mutex_unlock(&sc->mutex); mutex_unlock(&sc->mutex);

12
drivers/net/wireless/ath/ath9k/pci.c
View File

@ -103,11 +103,23 @@ static void ath_pci_bt_coex_prep(struct ath_common *common)
pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm); pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
} }
static void ath_pci_extn_synch_enable(struct ath_common *common)
{
struct ath_softc *sc = (struct ath_softc *) common->priv;
struct pci_dev *pdev = to_pci_dev(sc->dev);
u8 lnkctl;
pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
lnkctl |= PCI_EXP_LNKCTL_ES;
pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
}
static const struct ath_bus_ops ath_pci_bus_ops = { static const struct ath_bus_ops ath_pci_bus_ops = {
.ath_bus_type = ATH_PCI, .ath_bus_type = ATH_PCI,
.read_cachesize = ath_pci_read_cachesize, .read_cachesize = ath_pci_read_cachesize,
.eeprom_read = ath_pci_eeprom_read, .eeprom_read = ath_pci_eeprom_read,
.bt_coex_prep = ath_pci_bt_coex_prep, .bt_coex_prep = ath_pci_bt_coex_prep,
.extn_synch_en = ath_pci_extn_synch_enable,
}; };
static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)