sfc: Remove falcon references
Siena was using functions from the Falcon architecture. These start with the efx_farch prefix. Now that both of these are in separate modules the references are no longer used in the sfc.ko module. Signed-off-by: Martin Habets <habetsm.xilinx@gmail.com> Acked-by: Edward Cree <ecree.xilinx@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Martin Habets
David S. Miller
parent
be92377208
commit
806521bc48
File diff suppressed because it is too large
Load Diff
@ -10,7 +10,6 @@
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#include "net_driver.h"
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#include "nic.h"
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#include "io.h"
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#include "farch_regs.h"
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#include "mcdi_pcol.h"
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/**************************************************************************
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@ -237,7 +237,7 @@ struct efx_tx_buffer {
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* Normally this will equal @write_count, but as option descriptors
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* don't produce completion events, they won't update this.
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* Filled in iff @efx->type->option_descriptors; only used for PIO.
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* Thus, this is written and used on EF10, and neither on farch.
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* Thus, this is only written and used on EF10.
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* @old_read_count: The value of read_count when last checked.
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* This is here for performance reasons. The xmit path will
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* only get the up-to-date value of read_count if this
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@ -1288,8 +1288,7 @@ struct efx_udp_tunnel {
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* @set_wol: Push WoL configuration to the NIC
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* @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
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* @get_fec_stats: Get standard FEC statistics.
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* @test_chip: Test registers. May use efx_farch_test_registers(), and is
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* expected to reset the NIC.
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* @test_chip: Test registers. This is expected to reset the NIC.
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* @test_nvram: Test validity of NVRAM contents
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* @mcdi_request: Send an MCDI request with the given header and SDU.
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* The SDU length may be any value from 0 up to the protocol-
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@ -17,7 +17,6 @@
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#include "efx.h"
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#include "nic.h"
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#include "ef10_regs.h"
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#include "farch_regs.h"
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#include "io.h"
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#include "workarounds.h"
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#include "mcdi_pcol.h"
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@ -172,10 +171,6 @@ void efx_nic_fini_interrupt(struct efx_nic *efx)
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/* Register dump */
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#define REGISTER_REVISION_FA 1
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#define REGISTER_REVISION_FB 2
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#define REGISTER_REVISION_FC 3
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#define REGISTER_REVISION_FZ 3 /* last Falcon arch revision */
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#define REGISTER_REVISION_ED 4
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#define REGISTER_REVISION_EZ 4 /* latest EF10 revision */
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@ -189,117 +184,9 @@ struct efx_nic_reg {
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REGISTER_REVISION_ ## arch ## min_rev, \
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REGISTER_REVISION_ ## arch ## max_rev \
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}
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#define REGISTER_AA(name) REGISTER(name, F, A, A)
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#define REGISTER_AB(name) REGISTER(name, F, A, B)
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#define REGISTER_AZ(name) REGISTER(name, F, A, Z)
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#define REGISTER_BB(name) REGISTER(name, F, B, B)
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#define REGISTER_BZ(name) REGISTER(name, F, B, Z)
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#define REGISTER_CZ(name) REGISTER(name, F, C, Z)
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#define REGISTER_DZ(name) REGISTER(name, E, D, Z)
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static const struct efx_nic_reg efx_nic_regs[] = {
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REGISTER_AZ(ADR_REGION),
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REGISTER_AZ(INT_EN_KER),
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REGISTER_BZ(INT_EN_CHAR),
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REGISTER_AZ(INT_ADR_KER),
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REGISTER_BZ(INT_ADR_CHAR),
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/* INT_ACK_KER is WO */
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/* INT_ISR0 is RC */
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REGISTER_AZ(HW_INIT),
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REGISTER_CZ(USR_EV_CFG),
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REGISTER_AB(EE_SPI_HCMD),
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REGISTER_AB(EE_SPI_HADR),
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REGISTER_AB(EE_SPI_HDATA),
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REGISTER_AB(EE_BASE_PAGE),
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REGISTER_AB(EE_VPD_CFG0),
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/* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
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/* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
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/* PCIE_CORE_INDIRECT is indirect */
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REGISTER_AB(NIC_STAT),
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REGISTER_AB(GPIO_CTL),
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REGISTER_AB(GLB_CTL),
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/* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
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REGISTER_BZ(DP_CTRL),
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REGISTER_AZ(MEM_STAT),
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REGISTER_AZ(CS_DEBUG),
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REGISTER_AZ(ALTERA_BUILD),
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REGISTER_AZ(CSR_SPARE),
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REGISTER_AB(PCIE_SD_CTL0123),
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REGISTER_AB(PCIE_SD_CTL45),
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REGISTER_AB(PCIE_PCS_CTL_STAT),
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/* DEBUG_DATA_OUT is not used */
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/* DRV_EV is WO */
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REGISTER_AZ(EVQ_CTL),
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REGISTER_AZ(EVQ_CNT1),
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REGISTER_AZ(EVQ_CNT2),
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REGISTER_AZ(BUF_TBL_CFG),
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REGISTER_AZ(SRM_RX_DC_CFG),
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REGISTER_AZ(SRM_TX_DC_CFG),
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REGISTER_AZ(SRM_CFG),
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/* BUF_TBL_UPD is WO */
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REGISTER_AZ(SRM_UPD_EVQ),
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REGISTER_AZ(SRAM_PARITY),
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REGISTER_AZ(RX_CFG),
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REGISTER_BZ(RX_FILTER_CTL),
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/* RX_FLUSH_DESCQ is WO */
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REGISTER_AZ(RX_DC_CFG),
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REGISTER_AZ(RX_DC_PF_WM),
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REGISTER_BZ(RX_RSS_TKEY),
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/* RX_NODESC_DROP is RC */
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REGISTER_AA(RX_SELF_RST),
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/* RX_DEBUG, RX_PUSH_DROP are not used */
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REGISTER_CZ(RX_RSS_IPV6_REG1),
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REGISTER_CZ(RX_RSS_IPV6_REG2),
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REGISTER_CZ(RX_RSS_IPV6_REG3),
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/* TX_FLUSH_DESCQ is WO */
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REGISTER_AZ(TX_DC_CFG),
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REGISTER_AA(TX_CHKSM_CFG),
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REGISTER_AZ(TX_CFG),
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/* TX_PUSH_DROP is not used */
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REGISTER_AZ(TX_RESERVED),
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REGISTER_BZ(TX_PACE),
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/* TX_PACE_DROP_QID is RC */
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REGISTER_BB(TX_VLAN),
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REGISTER_BZ(TX_IPFIL_PORTEN),
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REGISTER_AB(MD_TXD),
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REGISTER_AB(MD_RXD),
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REGISTER_AB(MD_CS),
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REGISTER_AB(MD_PHY_ADR),
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REGISTER_AB(MD_ID),
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/* MD_STAT is RC */
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REGISTER_AB(MAC_STAT_DMA),
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REGISTER_AB(MAC_CTRL),
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REGISTER_BB(GEN_MODE),
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REGISTER_AB(MAC_MC_HASH_REG0),
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REGISTER_AB(MAC_MC_HASH_REG1),
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REGISTER_AB(GM_CFG1),
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REGISTER_AB(GM_CFG2),
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/* GM_IPG and GM_HD are not used */
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REGISTER_AB(GM_MAX_FLEN),
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/* GM_TEST is not used */
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REGISTER_AB(GM_ADR1),
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REGISTER_AB(GM_ADR2),
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REGISTER_AB(GMF_CFG0),
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REGISTER_AB(GMF_CFG1),
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REGISTER_AB(GMF_CFG2),
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REGISTER_AB(GMF_CFG3),
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REGISTER_AB(GMF_CFG4),
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REGISTER_AB(GMF_CFG5),
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REGISTER_BB(TX_SRC_MAC_CTL),
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REGISTER_AB(XM_ADR_LO),
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REGISTER_AB(XM_ADR_HI),
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REGISTER_AB(XM_GLB_CFG),
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REGISTER_AB(XM_TX_CFG),
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REGISTER_AB(XM_RX_CFG),
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REGISTER_AB(XM_MGT_INT_MASK),
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REGISTER_AB(XM_FC),
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REGISTER_AB(XM_PAUSE_TIME),
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REGISTER_AB(XM_TX_PARAM),
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REGISTER_AB(XM_RX_PARAM),
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/* XM_MGT_INT_MSK (note no 'A') is RC */
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REGISTER_AB(XX_PWR_RST),
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REGISTER_AB(XX_SD_CTL),
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REGISTER_AB(XX_TXDRV_CTL),
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/* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
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/* XX_CORE_STAT is partly RC */
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REGISTER_DZ(BIU_HW_REV_ID),
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@ -325,49 +212,9 @@ struct efx_nic_reg_table {
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arch, min_rev, max_rev, \
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arch ## R_ ## min_rev ## max_rev ## _ ## name ## _STEP, \
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arch ## R_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
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#define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, F, A, A)
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#define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, F, A, Z)
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#define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, F, B, B)
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#define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, F, B, Z)
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#define REGISTER_TABLE_BB_CZ(name) \
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REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, B, B, \
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FR_BZ_ ## name ## _STEP, \
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FR_BB_ ## name ## _ROWS), \
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REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, C, Z, \
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FR_BZ_ ## name ## _STEP, \
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FR_CZ_ ## name ## _ROWS)
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#define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, F, C, Z)
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#define REGISTER_TABLE_DZ(name) REGISTER_TABLE(name, E, D, Z)
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static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
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/* DRIVER is not used */
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/* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
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REGISTER_TABLE_BB(TX_IPFIL_TBL),
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REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
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REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
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REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
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REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
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REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
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REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
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REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
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/* We can't reasonably read all of the buffer table (up to 8MB!).
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* However this driver will only use a few entries. Reading
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* 1K entries allows for some expansion of queue count and
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* size before we need to change the version. */
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REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
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F, A, A, 8, 1024),
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REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
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F, B, Z, 8, 1024),
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REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
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REGISTER_TABLE_BB_CZ(TIMER_TBL),
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REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
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REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
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/* TX_FILTER_TBL0 is huge and not used by this driver */
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REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
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REGISTER_TABLE_CZ(MC_TREG_SMEM),
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/* MSIX_PBA_TABLE is not mapped */
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/* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
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REGISTER_TABLE_BZ(RX_FILTER_TBL0),
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REGISTER_TABLE_DZ(BIU_MC_SFT_STATUS),
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};
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@ -11,8 +11,6 @@
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#include "nic_common.h"
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#include "efx.h"
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u32 efx_farch_fpga_ver(struct efx_nic *efx);
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enum {
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PHY_TYPE_NONE = 0,
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PHY_TYPE_TXC43128 = 1,
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@ -304,89 +302,8 @@ int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
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extern const struct efx_nic_type efx_hunt_a0_nic_type;
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extern const struct efx_nic_type efx_hunt_a0_vf_nic_type;
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int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
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/* Falcon/Siena queue operations */
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int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
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void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
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void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
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void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
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void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
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unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue,
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dma_addr_t dma_addr, unsigned int len);
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int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
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void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
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void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
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void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
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void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
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void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
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int efx_farch_ev_probe(struct efx_channel *channel);
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int efx_farch_ev_init(struct efx_channel *channel);
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void efx_farch_ev_fini(struct efx_channel *channel);
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void efx_farch_ev_remove(struct efx_channel *channel);
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int efx_farch_ev_process(struct efx_channel *channel, int quota);
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void efx_farch_ev_read_ack(struct efx_channel *channel);
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void efx_farch_ev_test_generate(struct efx_channel *channel);
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/* Falcon/Siena filter operations */
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int efx_farch_filter_table_probe(struct efx_nic *efx);
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void efx_farch_filter_table_restore(struct efx_nic *efx);
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void efx_farch_filter_table_remove(struct efx_nic *efx);
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void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
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s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec,
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bool replace);
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int efx_farch_filter_remove_safe(struct efx_nic *efx,
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enum efx_filter_priority priority,
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u32 filter_id);
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int efx_farch_filter_get_safe(struct efx_nic *efx,
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enum efx_filter_priority priority, u32 filter_id,
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struct efx_filter_spec *);
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int efx_farch_filter_clear_rx(struct efx_nic *efx,
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enum efx_filter_priority priority);
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u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
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enum efx_filter_priority priority);
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u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
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s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
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enum efx_filter_priority priority, u32 *buf,
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u32 size);
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#ifdef CONFIG_RFS_ACCEL
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bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
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unsigned int index);
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#endif
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void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
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/* Falcon/Siena interrupts */
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void efx_farch_irq_enable_master(struct efx_nic *efx);
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int efx_farch_irq_test_generate(struct efx_nic *efx);
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void efx_farch_irq_disable_master(struct efx_nic *efx);
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irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
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irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
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irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
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/* Global Resources */
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void siena_prepare_flush(struct efx_nic *efx);
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int efx_farch_fini_dmaq(struct efx_nic *efx);
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void efx_farch_finish_flr(struct efx_nic *efx);
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void siena_finish_flush(struct efx_nic *efx);
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void falcon_start_nic_stats(struct efx_nic *efx);
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void falcon_stop_nic_stats(struct efx_nic *efx);
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int falcon_reset_xaui(struct efx_nic *efx);
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void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
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void efx_farch_init_common(struct efx_nic *efx);
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void efx_farch_rx_push_indir_table(struct efx_nic *efx);
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void efx_farch_rx_pull_indir_table(struct efx_nic *efx);
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/* Tests */
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struct efx_farch_register_test {
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unsigned address;
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efx_oword_t mask;
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};
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int efx_farch_test_registers(struct efx_nic *efx,
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const struct efx_farch_register_test *regs,
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size_t n_regs);
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void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
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efx_qword_t *event);
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#endif /* EFX_NIC_H */
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@ -43,7 +43,6 @@
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#include "mcdi.h"
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#include "mcdi_pcol.h"
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#include "io.h"
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#include "farch_regs.h"
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#include "tx.h"
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#include "nic.h" /* indirectly includes ptp.h */
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#include "efx_channels.h"
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