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ASoC: ssm2602: Add support for CLKDIV2

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The SSM260x chips have an internal MCLK /2 divider (bit D7 in register
R8). Add logic that allows for more MCLK values using this divider.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Link: https://lore.kernel.org/r/20230414140203.707729-7-pan@semihalf.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Paweł Anikiel 2023-04-14 16:02:00 +02:00 committed by Mark Brown
parent fc0b096c92
commit 8076c586bb
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 12 additions and 3 deletions
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15
sound/soc/codecs/ssm2602.c
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@ -280,9 +280,12 @@ static inline int ssm2602_get_coeff(int mclk, int rate)
int i;
for (i = 0; i < ARRAY_SIZE(ssm2602_coeff_table); i++) {
if (ssm2602_coeff_table[i].rate == rate &&
ssm2602_coeff_table[i].mclk == mclk)
return ssm2602_coeff_table[i].srate;
if (ssm2602_coeff_table[i].rate == rate) {
if (ssm2602_coeff_table[i].mclk == mclk)
return ssm2602_coeff_table[i].srate;
if (ssm2602_coeff_table[i].mclk == mclk / 2)
return ssm2602_coeff_table[i].srate | SRATE_CORECLK_DIV2;
}
}
return -EINVAL;
}
@ -365,18 +368,24 @@ static int ssm2602_set_dai_sysclk(struct snd_soc_dai *codec_dai,
switch (freq) {
case 12288000:
case 18432000:
case 24576000:
case 36864000:
ssm2602->sysclk_constraints = &ssm2602_constraints_12288000;
break;
case 11289600:
case 16934400:
case 22579200:
case 33868800:
ssm2602->sysclk_constraints = &ssm2602_constraints_11289600;
break;
case 12000000:
case 24000000:
ssm2602->sysclk_constraints = NULL;
break;
default:
return -EINVAL;
}
ssm2602->sysclk = freq;
} else {
unsigned int mask;