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cxgb4: collect SGE PF/VF queue map

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For T6, collect info on queue mapping to corresponding PF/VF in SGE.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Rahul Lakkireddy 2018-05-18 19:12:53 +05:30 committed by David S. Miller
parent a3302baa2c
commit 80a95a80d3
3 changed files with 65 additions and 2 deletions
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17
drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
View File

@ -62,6 +62,18 @@ struct cudbg_hw_sched {
u32 map;
};
#define SGE_QBASE_DATA_REG_NUM 4
struct sge_qbase_reg_field {
u32 reg_addr;
u32 reg_data[SGE_QBASE_DATA_REG_NUM];
/* Max supported PFs */
u32 pf_data_value[PCIE_FW_MASTER_M + 1][SGE_QBASE_DATA_REG_NUM];
/* Max supported VFs */
u32 vf_data_value[T6_VF_M + 1][SGE_QBASE_DATA_REG_NUM];
u32 vfcount; /* Actual number of max vfs in current configuration */
};
struct ireg_field {
u32 ireg_addr;
u32 ireg_data;
@ -357,6 +369,11 @@ static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = {
{0x10cc, 0x10d4, 0x0, 16},
};
static const u32 t6_sge_qbase_index_array[] = {
/* 1 addr reg SGE_QBASE_INDEX and 4 data reg SGE_QBASE_MAP[0-3] */
0x1250, 0x1240, 0x1244, 0x1248, 0x124c,
};
static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = {
{0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
{0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */

47
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
View File

@ -1339,16 +1339,39 @@ int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,
return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
}
static void cudbg_read_sge_qbase_indirect_reg(struct adapter *padap,
struct sge_qbase_reg_field *qbase,
u32 func, bool is_pf)
{
u32 *buff, i;
if (is_pf) {
buff = qbase->pf_data_value[func];
} else {
buff = qbase->vf_data_value[func];
/* In SGE_QBASE_INDEX,
* Entries 0->7 are PF0->7, Entries 8->263 are VFID0->256.
*/
func += 8;
}
t4_write_reg(padap, qbase->reg_addr, func);
for (i = 0; i < SGE_QBASE_DATA_REG_NUM; i++, buff++)
*buff = t4_read_reg(padap, qbase->reg_data[i]);
}
int cudbg_collect_sge_indirect(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
{
struct adapter *padap = pdbg_init->adap;
struct cudbg_buffer temp_buff = { 0 };
struct sge_qbase_reg_field *sge_qbase;
struct ireg_buf *ch_sge_dbg;
int i, rc;
rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(*ch_sge_dbg) * 2,
rc = cudbg_get_buff(pdbg_init, dbg_buff,
sizeof(*ch_sge_dbg) * 2 + sizeof(*sge_qbase),
&temp_buff);
if (rc)
return rc;
@ -1370,6 +1393,28 @@ int cudbg_collect_sge_indirect(struct cudbg_init *pdbg_init,
sge_pio->ireg_local_offset);
ch_sge_dbg++;
}
if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) {
sge_qbase = (struct sge_qbase_reg_field *)ch_sge_dbg;
/* 1 addr reg SGE_QBASE_INDEX and 4 data reg
* SGE_QBASE_MAP[0-3]
*/
sge_qbase->reg_addr = t6_sge_qbase_index_array[0];
for (i = 0; i < SGE_QBASE_DATA_REG_NUM; i++)
sge_qbase->reg_data[i] =
t6_sge_qbase_index_array[i + 1];
for (i = 0; i <= PCIE_FW_MASTER_M; i++)
cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase,
i, true);
for (i = 0; i < padap->params.arch.vfcount; i++)
cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase,
i, false);
sge_qbase->vfcount = padap->params.arch.vfcount;
}
return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
}

3
drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
View File

@ -214,7 +214,8 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
len = sizeof(struct ireg_buf) * n;
break;
case CUDBG_SGE_INDIRECT:
len = sizeof(struct ireg_buf) * 2;
len = sizeof(struct ireg_buf) * 2 +
sizeof(struct sge_qbase_reg_field);
break;
case CUDBG_ULPRX_LA:
len = sizeof(struct cudbg_ulprx_la);