cxgb4: collect SGE PF/VF queue map
For T6, collect info on queue mapping to corresponding PF/VF in SGE. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -62,6 +62,18 @@ struct cudbg_hw_sched {
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u32 map;
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};
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#define SGE_QBASE_DATA_REG_NUM 4
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struct sge_qbase_reg_field {
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u32 reg_addr;
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u32 reg_data[SGE_QBASE_DATA_REG_NUM];
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/* Max supported PFs */
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u32 pf_data_value[PCIE_FW_MASTER_M + 1][SGE_QBASE_DATA_REG_NUM];
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/* Max supported VFs */
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u32 vf_data_value[T6_VF_M + 1][SGE_QBASE_DATA_REG_NUM];
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u32 vfcount; /* Actual number of max vfs in current configuration */
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};
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struct ireg_field {
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u32 ireg_addr;
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u32 ireg_data;
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@ -357,6 +369,11 @@ static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = {
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{0x10cc, 0x10d4, 0x0, 16},
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};
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static const u32 t6_sge_qbase_index_array[] = {
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/* 1 addr reg SGE_QBASE_INDEX and 4 data reg SGE_QBASE_MAP[0-3] */
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0x1250, 0x1240, 0x1244, 0x1248, 0x124c,
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};
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static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = {
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{0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
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{0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */
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@ -1339,16 +1339,39 @@ int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,
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return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
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}
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static void cudbg_read_sge_qbase_indirect_reg(struct adapter *padap,
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struct sge_qbase_reg_field *qbase,
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u32 func, bool is_pf)
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{
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u32 *buff, i;
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if (is_pf) {
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buff = qbase->pf_data_value[func];
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} else {
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buff = qbase->vf_data_value[func];
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/* In SGE_QBASE_INDEX,
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* Entries 0->7 are PF0->7, Entries 8->263 are VFID0->256.
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*/
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func += 8;
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}
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t4_write_reg(padap, qbase->reg_addr, func);
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for (i = 0; i < SGE_QBASE_DATA_REG_NUM; i++, buff++)
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*buff = t4_read_reg(padap, qbase->reg_data[i]);
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}
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int cudbg_collect_sge_indirect(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err)
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{
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struct adapter *padap = pdbg_init->adap;
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struct cudbg_buffer temp_buff = { 0 };
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struct sge_qbase_reg_field *sge_qbase;
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struct ireg_buf *ch_sge_dbg;
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int i, rc;
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rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(*ch_sge_dbg) * 2,
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rc = cudbg_get_buff(pdbg_init, dbg_buff,
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sizeof(*ch_sge_dbg) * 2 + sizeof(*sge_qbase),
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&temp_buff);
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if (rc)
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return rc;
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@ -1370,6 +1393,28 @@ int cudbg_collect_sge_indirect(struct cudbg_init *pdbg_init,
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sge_pio->ireg_local_offset);
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ch_sge_dbg++;
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}
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if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) {
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sge_qbase = (struct sge_qbase_reg_field *)ch_sge_dbg;
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/* 1 addr reg SGE_QBASE_INDEX and 4 data reg
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* SGE_QBASE_MAP[0-3]
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*/
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sge_qbase->reg_addr = t6_sge_qbase_index_array[0];
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for (i = 0; i < SGE_QBASE_DATA_REG_NUM; i++)
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sge_qbase->reg_data[i] =
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t6_sge_qbase_index_array[i + 1];
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for (i = 0; i <= PCIE_FW_MASTER_M; i++)
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cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase,
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i, true);
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for (i = 0; i < padap->params.arch.vfcount; i++)
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cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase,
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i, false);
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sge_qbase->vfcount = padap->params.arch.vfcount;
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}
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return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
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}
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@ -214,7 +214,8 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
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len = sizeof(struct ireg_buf) * n;
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break;
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case CUDBG_SGE_INDIRECT:
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len = sizeof(struct ireg_buf) * 2;
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len = sizeof(struct ireg_buf) * 2 +
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sizeof(struct sge_qbase_reg_field);
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break;
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case CUDBG_ULPRX_LA:
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len = sizeof(struct cudbg_ulprx_la);
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