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drm/amdgpu: add apu sequence in the imu v11

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APU required to issue the enable GFX IMU message after IMU reset.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Huang Rui 2022-05-18 22:05:03 +08:00 committed by Alex Deucher
parent 7101ab97e3
commit 80d46fff37
2 changed files with 9 additions and 4 deletions
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6
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
View File

@ -6292,7 +6292,11 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)
{
adev->gfx.imu.mode = DEBUG_MODE;
if (adev->flags & AMD_IS_APU)
adev->gfx.imu.mode = MISSION_MODE;
else
adev->gfx.imu.mode = DEBUG_MODE;
adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
}

7
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
View File

@ -24,6 +24,7 @@
#include <linux/firmware.h>
#include "amdgpu.h"
#include "amdgpu_imu.h"
#include "amdgpu_dpm.h"
#include "gc/gc_11_0_0_offset.h"
#include "gc/gc_11_0_0_sh_mask.h"
@ -165,10 +166,10 @@ static int imu_v11_0_start(struct amdgpu_device *adev)
imu_reg_val &= 0xfffffffe;
WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
if (adev->gfx.imu.mode == DEBUG_MODE)
return imu_v11_0_wait_for_reset_status(adev);
if (adev->flags & AMD_IS_APU)
amdgpu_dpm_set_gfx_power_up_by_imu(adev);
return 0;
return imu_v11_0_wait_for_reset_status(adev);
}
static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] =