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arm64: dts: mt7622: specify the L2 cache topology

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On an MT7622 system, the kernel complains of not being able to detect the cache
hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in
order to fix this.

Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
Link: https://lore.kernel.org/r/20220428225755.785153-1-rsalvaterra@gmail.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Rui Salvaterra 2022-04-28 23:57:55 +01:00 committed by Matthias Brugger
parent 7d029cc240
commit 80dd27b6c6
1 changed files with 7 additions and 0 deletions
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7
arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@ -80,6 +80,7 @@
enable-method = "psci";
clock-frequency = <1300000000>;
cci-control-port = <&cci_control2>;
next-level-cache = <&L2>;
};
cpu1: cpu@1 {
@ -94,6 +95,12 @@
enable-method = "psci";
clock-frequency = <1300000000>;
cci-control-port = <&cci_control2>;
next-level-cache = <&L2>;
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};