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drm/amdgpu/vcn2.5: fix DPG mode power off issue on instance 1

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Support pause_state for multiple instance, and it will fix vcn2.5 DPG mode
power off issue on instance 1.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
James Zhu
2020-02-05 09:20:22 -05:00
committed by Alex Deucher
parent 4a6f8f01ef
commit 80ff3e10c8
4 changed files with 15 additions and 14 deletions
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3
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
View File

@@ -179,6 +179,7 @@ struct amdgpu_vcn_inst {
struct amdgpu_irq_src irq; struct amdgpu_irq_src irq;
struct amdgpu_vcn_reg external; struct amdgpu_vcn_reg external;
struct amdgpu_bo *dpg_sram_bo; struct amdgpu_bo *dpg_sram_bo;
struct dpg_pause_state pause_state;
void *dpg_sram_cpu_addr; void *dpg_sram_cpu_addr;
uint64_t dpg_sram_gpu_addr; uint64_t dpg_sram_gpu_addr;
uint32_t *dpg_sram_curr_addr; uint32_t *dpg_sram_curr_addr;
@@ -190,8 +191,6 @@ struct amdgpu_vcn {
const struct firmware *fw; /* VCN firmware */ const struct firmware *fw; /* VCN firmware */
unsigned num_enc_rings; unsigned num_enc_rings;
enum amd_powergating_state cur_state; enum amd_powergating_state cur_state;
struct dpg_pause_state pause_state;
bool indirect_sram; bool indirect_sram;
uint8_t num_vcn_inst; uint8_t num_vcn_inst;

14
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
View File

@@ -1207,9 +1207,10 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
struct amdgpu_ring *ring; struct amdgpu_ring *ring;
/* pause/unpause if state is changed */ /* pause/unpause if state is changed */
if (adev->vcn.pause_state.fw_based != new_state->fw_based) { if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, adev->vcn.inst[inst_idx].pause_state.fw_based,
adev->vcn.inst[inst_idx].pause_state.jpeg,
new_state->fw_based, new_state->jpeg); new_state->fw_based, new_state->jpeg);
reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
@@ -1258,13 +1259,14 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
} }
adev->vcn.pause_state.fw_based = new_state->fw_based; adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
} }
/* pause/unpause if state is changed */ /* pause/unpause if state is changed */
if (adev->vcn.pause_state.jpeg != new_state->jpeg) { if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {
DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, adev->vcn.inst[inst_idx].pause_state.fw_based,
adev->vcn.inst[inst_idx].pause_state.jpeg,
new_state->fw_based, new_state->jpeg); new_state->fw_based, new_state->jpeg);
reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
@@ -1318,7 +1320,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
} }
adev->vcn.pause_state.jpeg = new_state->jpeg; adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;
} }
return 0; return 0;

6
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
View File

@@ -1137,9 +1137,9 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
int ret_code; int ret_code;
/* pause/unpause if state is changed */ /* pause/unpause if state is changed */
if (adev->vcn.pause_state.fw_based != new_state->fw_based) { if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
DRM_DEBUG("dpg pause state changed %d -> %d", DRM_DEBUG("dpg pause state changed %d -> %d",
adev->vcn.pause_state.fw_based, new_state->fw_based); adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
(~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
@@ -1185,7 +1185,7 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
} }
adev->vcn.pause_state.fw_based = new_state->fw_based; adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
} }
return 0; return 0;

6
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
View File

@@ -1367,9 +1367,9 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
int ret_code; int ret_code;
/* pause/unpause if state is changed */ /* pause/unpause if state is changed */
if (adev->vcn.pause_state.fw_based != new_state->fw_based) { if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
DRM_DEBUG("dpg pause state changed %d -> %d", DRM_DEBUG("dpg pause state changed %d -> %d",
adev->vcn.pause_state.fw_based, new_state->fw_based); adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
reg_data = RREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE) & reg_data = RREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE) &
(~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
@@ -1414,7 +1414,7 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
WREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE, reg_data); WREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE, reg_data);
} }
adev->vcn.pause_state.fw_based = new_state->fw_based; adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
} }
return 0; return 0;