phy dp83867: Make rgmii parameters optional
If you compile without OF_MDIO support in an RGMII configuration, we fail to configure the dp83867 phy today by writing garbage into its configuration registers. On the other hand if you do compile with OF_MDIO and the phy gets loaded via device tree, you have to have the properties set in the device tree, otherwise we fail to load the driver and don't even attach the generic phy driver to the interface anymore. To make things slightly more consistent, make the rgmii configuration properties optional and allow a user to omit them in their device tree. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -65,6 +65,7 @@ struct dp83867_private {
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int rx_id_delay;
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int tx_id_delay;
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int fifo_depth;
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int values_are_sane;
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};
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static int dp83867_ack_interrupt(struct phy_device *phydev)
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@ -113,15 +114,30 @@ static int dp83867_of_init(struct phy_device *phydev)
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ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
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&dp83867->rx_id_delay);
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if (ret)
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return ret;
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goto invalid_dt;
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ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
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&dp83867->tx_id_delay);
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if (ret)
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return ret;
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goto invalid_dt;
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return of_property_read_u32(of_node, "ti,fifo-depth",
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ret = of_property_read_u32(of_node, "ti,fifo-depth",
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&dp83867->fifo_depth);
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if (ret)
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goto invalid_dt;
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dp83867->values_are_sane = 1;
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return 0;
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invalid_dt:
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phydev_err(phydev, "missing properties in device tree");
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/*
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* We can still run with a broken dt by not using any of the optional
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* parameters, so just don't set dp83867->values_are_sane.
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*/
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return 0;
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}
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#else
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static int dp83867_of_init(struct phy_device *phydev)
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@ -150,6 +166,15 @@ static int dp83867_config_init(struct phy_device *phydev)
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dp83867 = (struct dp83867_private *)phydev->priv;
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}
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/*
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* With no or broken device tree, we don't have the values that we would
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* want to configure the phy with. In that case, cross our fingers and
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* assume that firmware did everything correctly for us or that we don't
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* need them.
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*/
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if (!dp83867->values_are_sane)
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return 0;
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if (phy_interface_is_rgmii(phydev)) {
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ret = phy_write(phydev, MII_DP83867_PHYCTRL,
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(dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
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