iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/i915/gt: nuke gen6_hw_id

Browse Source 
This is only used by GRAPHICS_VER == 6 and GRAPHICS_VER == 7. All other
recent platforms do not depend on this field, so it doesn't make much
sense to keep it generic like that. Instead, just do a mapping from
engine class to HW ID in the single place that is needed.

v2: use macros with the direct register address instead of calculating
from the legacy HW_ID (Matt Roper)

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723002551.3906535-1-lucas.demarchi@intel.com
This commit is contained in:
Lucas De Marchi 2021-07-22 17:25:51 -07:00
parent bfac1e2b6e
commit 816753c06f
3 changed files with 11 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/drm/i915/gt/intel_engine_cs.c
View File

@ -42,7 +42,6 @@
#define MAX_MMIO_BASES 3
struct engine_info {
u8 gen6_hw_id;
u8 class;
u8 instance;
/* mmio bases table *must* be sorted in reverse graphics_ver order */
@ -54,7 +53,6 @@ struct engine_info {
static const struct engine_info intel_engines[] = {
[RCS0] = {
.gen6_hw_id = RCS0_HW,
.class = RENDER_CLASS,
.instance = 0,
.mmio_bases = {
@ -62,7 +60,6 @@ static const struct engine_info intel_engines[] = {
},
},
[BCS0] = {
.gen6_hw_id = BCS0_HW,
.class = COPY_ENGINE_CLASS,
.instance = 0,
.mmio_bases = {
@ -70,7 +67,6 @@ static const struct engine_info intel_engines[] = {
},
},
[VCS0] = {
.gen6_hw_id = VCS0_HW,
.class = VIDEO_DECODE_CLASS,
.instance = 0,
.mmio_bases = {
@ -130,7 +126,6 @@ static const struct engine_info intel_engines[] = {
},
},
[VECS0] = {
.gen6_hw_id = VECS0_HW,
.class = VIDEO_ENHANCEMENT_CLASS,
.instance = 0,
.mmio_bases = {
@ -334,7 +329,6 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
engine->i915 = i915;
engine->gt = gt;
engine->uncore = gt->uncore;
engine->gen6_hw_id = info->gen6_hw_id;
guc_class = engine_class_to_guc_class(info->class);
engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);
engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);

10
drivers/gpu/drm/i915/gt/intel_engine_types.h
View File

@ -28,14 +28,7 @@
#include "intel_wakeref.h"
#include "intel_workarounds_types.h"
/* Legacy HW Engine ID */
#define RCS0_HW 0
#define VCS0_HW 1
#define BCS0_HW 2
#define VECS0_HW 3
/* Gen11+ HW Engine class + instance */
/* HW Engine class + instance */
#define RENDER_CLASS 0
#define VIDEO_DECODE_CLASS 1
#define VIDEO_ENHANCEMENT_CLASS 2
@ -274,7 +267,6 @@ struct intel_engine_cs {
intel_engine_mask_t mask;
u8 gen6_hw_id;
u8 class;
u8 instance;

11
drivers/gpu/drm/i915/i915_reg.h
View File

@ -2586,7 +2586,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define ARB_MODE_BWGTLB_DISABLE (1 << 9)
#define ARB_MODE_SWIZZLE_BDW (1 << 1)
#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->gen6_hw_id)
#define _RING_FAULT_REG_RCS 0x4094
#define _RING_FAULT_REG_VCS 0x4194
#define _RING_FAULT_REG_BCS 0x4294
#define _RING_FAULT_REG_VECS 0x4394
#define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \
_RING_FAULT_REG_RCS, \
_RING_FAULT_REG_VCS, \
_RING_FAULT_REG_VECS, \
_RING_FAULT_REG_BCS))
#define GEN8_RING_FAULT_REG _MMIO(0x4094)
#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)