drm/amd/display: Set new format info for converted metadata.
If we use DCC modifiers this can increase the number of planes from the initial 1 plane with metadata, so that we get a valid modifier from getfb2. Since the code didn't update the format_info getfb2 would only ever return 1 plane with a modifier for which userspace expects > 1. This moves the format lookup to amdgpu_display.c so we do not have issues when DC is not compiled. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Bas Nieuwenhuizen
Alex Deucher
parent
3505b2ff53
commit
816853f9dc
@ -534,6 +534,95 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
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return domain;
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}
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static const struct drm_format_info dcc_formats[] = {
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{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
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.cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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};
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static const struct drm_format_info dcc_retile_formats[] = {
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{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
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.cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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};
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static const struct drm_format_info *
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lookup_format_info(const struct drm_format_info formats[],
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int num_formats, u32 format)
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{
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int i;
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for (i = 0; i < num_formats; i++) {
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if (formats[i].format == format)
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return &formats[i];
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}
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return NULL;
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}
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const struct drm_format_info *
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amdgpu_lookup_format_info(u32 format, uint64_t modifier)
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{
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if (!IS_AMD_FMT_MOD(modifier))
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return NULL;
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if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
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return lookup_format_info(dcc_retile_formats,
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ARRAY_SIZE(dcc_retile_formats),
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format);
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if (AMD_FMT_MOD_GET(DCC, modifier))
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return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
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format);
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/* returning NULL will cause the default format structs to be used. */
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return NULL;
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}
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static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
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{
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struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
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@ -623,6 +712,7 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
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if (dcc_offset != 0) {
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bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
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bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
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const struct drm_format_info *format_info;
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/* Enable constant encode on RAVEN2 and later. */
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bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN ||
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@ -641,6 +731,13 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
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afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
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afb->base.pitches[1] = AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
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format_info = amdgpu_lookup_format_info(afb->base.format->format,
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modifier);
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if (!format_info)
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return -EINVAL;
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afb->base.format = format_info;
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}
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}
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@ -44,5 +44,7 @@ struct drm_framebuffer *
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amdgpu_display_user_framebuffer_create(struct drm_device *dev,
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struct drm_file *file_priv,
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const struct drm_mode_fb_cmd2 *mode_cmd);
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const struct drm_format_info *
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amdgpu_lookup_format_info(u32 format, uint64_t modifier);
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#endif
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@ -3847,96 +3847,10 @@ modifier_gfx9_swizzle_mode(uint64_t modifier)
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return AMD_FMT_MOD_GET(TILE, modifier);
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}
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static const struct drm_format_info dcc_formats[] = {
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{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
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.cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
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.cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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};
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static const struct drm_format_info dcc_retile_formats[] = {
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{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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{ .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
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.cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
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.has_alpha = true, },
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{ .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
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.cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
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};
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static const struct drm_format_info *
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lookup_format_info(const struct drm_format_info formats[],
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int num_formats, u32 format)
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{
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int i;
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for (i = 0; i < num_formats; i++) {
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if (formats[i].format == format)
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return &formats[i];
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}
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return NULL;
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}
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static const struct drm_format_info *
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amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
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{
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uint64_t modifier = cmd->modifier[0];
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if (!IS_AMD_FMT_MOD(modifier))
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return NULL;
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if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
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return lookup_format_info(dcc_retile_formats,
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ARRAY_SIZE(dcc_retile_formats),
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cmd->pixel_format);
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if (AMD_FMT_MOD_GET(DCC, modifier))
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return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
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cmd->pixel_format);
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/* returning NULL will cause the default format structs to be used. */
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return NULL;
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return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]);
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}
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static void
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