Renesas driver updates for v5.19 (take two)
- Initial support for the R-Car V4H and RZ/V2M SoCs, - Miscellaneous fixes and improvements. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYnThKAAKCRCKwlD9ZEnx cDtZAQDveNky2MIYx0nNb88JzK5PS1zo85KcU5g6ybf/QEnMdQEA7GYKKKi9q3rF 5Q1h6kUvIW6e8c7lcva2DI4D7ZUIoAk= =M1iB -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmJ1gDcACgkQmmx57+YA GNl8LhAAjqsrH2O/ufjr/7SK1hHpqGdPo08RwHOvHNLOX35si9l4sSswf5xpI0M5 NtpS1DaDH5X7z/VteRC2CYqRR5L2pKogmjpEVxPCQxgVGfeicg4ntw59O6vuBmml w1bZ5a9Ipd/8AU5mEOXCZlb+96I16T9wfetlerSYyYsmt8pCLYwQrXijoIwUhrS0 i8YxzfUD5MZ7RZd8mzxxGs8vKDmgMZMuoxzdRxpoLIfgaRNyqCboLoP1lvQhXLFY XHLJZOW1pHd41sx5f1cJv3wKwsBHBVxzXFNGGz2i60BaVjrBSbSpixM+C/LUddIl h+QhR9PLKk2iIbDuiD6x9G6fv20LA0Gz5BI57XiJcuPK/SIB8R4hISYpQ6GVAh1L ve2NPE6o4hJC7UhJRH6JFNyfaF6pmPK9VVvG9BOPvd8L6SKyyeWHiVgaOzCBgJKm 5ZPKPZ8KCC9Rky7secioIFb2eyGg73CKWVi+cZzSb9wVkPC7rZsTTbErWTAI4FEn slyJrA36bfQXk2kDaWIXdN55xXD+oZhkHtwVVX61Srp6DEnaUABocGJ+TtrrfdkE 9OlsQE9fivl6WPtTZJ11RivT3qnpiUFl/owaG+l3q01Ryvtm9GJAJuBDhl1qN9AM /5endo466iMqS9zlNol+2MjPplGek43XSBE//24/+7BSmzPwcNs= =P6fe -----END PGP SIGNATURE----- Merge tag 'renesas-drivers-for-v5.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers Renesas driver updates for v5.19 (take two) - Initial support for the R-Car V4H and RZ/V2M SoCs, - Miscellaneous fixes and improvements. * tag 'renesas-drivers-for-v5.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: R-Car V3U is R-Car Gen4 soc: renesas: rzn1: Select PM and PM_GENERIC_DOMAINS configs soc: renesas: Add RZ/V2M (R9A09G011) config option soc: renesas: rcar-rst: Add support for R-Car V4H soc: renesas: Identify R-Car V4H soc: renesas: r8a779g0-sysc: Add r8a779g0 support dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions dt-bindings: power: Add r8a779g0 SYSC power domain definitions Link: https://lore.kernel.org/r/cover.1651828613.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
819ed6f07d
drivers/soc/renesas
include/dt-bindings
@ -47,6 +47,8 @@ config ARCH_RZG2L
|
||||
|
||||
config ARCH_RZN1
|
||||
bool
|
||||
select PM
|
||||
select PM_GENERIC_DOMAINS
|
||||
select ARM_AMBA
|
||||
|
||||
if ARM && ARCH_RENESAS
|
||||
@ -268,6 +270,13 @@ config ARCH_R8A779A0
|
||||
help
|
||||
This enables support for the Renesas R-Car V3U SoC.
|
||||
|
||||
config ARCH_R8A779G0
|
||||
bool "ARM64 Platform support for R-Car V4H"
|
||||
select ARCH_RCAR_GEN3
|
||||
select SYSC_R8A779G0
|
||||
help
|
||||
This enables support for the Renesas R-Car V4H SoC.
|
||||
|
||||
config ARCH_R8A774C0
|
||||
bool "ARM64 Platform support for RZ/G2E"
|
||||
select ARCH_RCAR_GEN3
|
||||
@ -314,6 +323,13 @@ config ARCH_R9A07G054
|
||||
help
|
||||
This enables support for the Renesas RZ/V2L SoC variants.
|
||||
|
||||
config ARCH_R9A09G011
|
||||
bool "ARM64 Platform support for RZ/V2M"
|
||||
select PM
|
||||
select PM_GENERIC_DOMAINS
|
||||
help
|
||||
This enables support for the Renesas RZ/V2M SoC.
|
||||
|
||||
endif # ARM64
|
||||
|
||||
config RST_RCAR
|
||||
@ -385,6 +401,10 @@ config SYSC_R8A779A0
|
||||
bool "System Controller support for R-Car V3U" if COMPILE_TEST
|
||||
select SYSC_RCAR_GEN4
|
||||
|
||||
config SYSC_R8A779G0
|
||||
bool "System Controller support for R-Car V4H" if COMPILE_TEST
|
||||
select SYSC_RCAR_GEN4
|
||||
|
||||
config SYSC_RMOBILE
|
||||
bool "System Controller support for R-Mobile" if COMPILE_TEST
|
||||
|
||||
|
||||
@ -26,6 +26,7 @@ obj-$(CONFIG_SYSC_R8A77990) += r8a77990-sysc.o
|
||||
obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o
|
||||
obj-$(CONFIG_SYSC_R8A779A0) += r8a779a0-sysc.o
|
||||
obj-$(CONFIG_SYSC_R8A779F0) += r8a779f0-sysc.o
|
||||
obj-$(CONFIG_SYSC_R8A779G0) += r8a779g0-sysc.o
|
||||
ifdef CONFIG_SMP
|
||||
obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o
|
||||
endif
|
||||
|
||||
62
drivers/soc/renesas/r8a779g0-sysc.c
Normal file
62
drivers/soc/renesas/r8a779g0-sysc.c
Normal file
@ -0,0 +1,62 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Renesas R-Car V4H System Controller
|
||||
*
|
||||
* Copyright (C) 2022 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <linux/bits.h>
|
||||
#include <linux/clk/renesas.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <dt-bindings/power/r8a779g0-sysc.h>
|
||||
|
||||
#include "rcar-gen4-sysc.h"
|
||||
|
||||
static struct rcar_gen4_sysc_area r8a779g0_areas[] __initdata = {
|
||||
{ "always-on", R8A779G0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
|
||||
{ "a3e0", R8A779G0_PD_A3E0, R8A779G0_PD_ALWAYS_ON, PD_SCU },
|
||||
{ "a2e0d0", R8A779G0_PD_A2E0D0, R8A779G0_PD_A3E0, PD_SCU },
|
||||
{ "a2e0d1", R8A779G0_PD_A2E0D1, R8A779G0_PD_A3E0, PD_SCU },
|
||||
{ "a1e0d0c0", R8A779G0_PD_A1E0D0C0, R8A779G0_PD_A2E0D0, PD_CPU_NOCR },
|
||||
{ "a1e0d0c1", R8A779G0_PD_A1E0D0C1, R8A779G0_PD_A2E0D0, PD_CPU_NOCR },
|
||||
{ "a1e0d1c0", R8A779G0_PD_A1E0D1C0, R8A779G0_PD_A2E0D1, PD_CPU_NOCR },
|
||||
{ "a1e0d1c1", R8A779G0_PD_A1E0D1C1, R8A779G0_PD_A2E0D1, PD_CPU_NOCR },
|
||||
{ "a33dga", R8A779G0_PD_A33DGA, R8A779G0_PD_ALWAYS_ON },
|
||||
{ "a23dgb", R8A779G0_PD_A23DGB, R8A779G0_PD_A33DGA },
|
||||
{ "a3vip0", R8A779G0_PD_A3VIP0, R8A779G0_PD_ALWAYS_ON },
|
||||
{ "a3vip1", R8A779G0_PD_A3VIP1, R8A779G0_PD_ALWAYS_ON },
|
||||
{ "a3vip2", R8A779G0_PD_A3VIP2, R8A779G0_PD_ALWAYS_ON },
|
||||
{ "a3isp0", R8A779G0_PD_A3ISP0, R8A779G0_PD_ALWAYS_ON },
|
||||
{ "a3isp1", R8A779G0_PD_A3ISP1, R8A779G0_PD_ALWAYS_ON },
|
||||
{ "a3ir", R8A779G0_PD_A3IR, R8A779G0_PD_ALWAYS_ON },
|
||||
{ "a2cn0", R8A779G0_PD_A2CN0, R8A779G0_PD_A3IR },
|
||||
{ "a1cnn0", R8A779G0_PD_A1CNN0, R8A779G0_PD_A2CN0 },
|
||||
{ "a1dsp0", R8A779G0_PD_A1DSP0, R8A779G0_PD_A2CN0 },
|
||||
{ "a1dsp1", R8A779G0_PD_A1DSP1, R8A779G0_PD_A2CN0 },
|
||||
{ "a1dsp2", R8A779G0_PD_A1DSP2, R8A779G0_PD_A2CN0 },
|
||||
{ "a1dsp3", R8A779G0_PD_A1DSP3, R8A779G0_PD_A2CN0 },
|
||||
{ "a2imp01", R8A779G0_PD_A2IMP01, R8A779G0_PD_A3IR },
|
||||
{ "a2imp23", R8A779G0_PD_A2IMP23, R8A779G0_PD_A3IR },
|
||||
{ "a2psc", R8A779G0_PD_A2PSC, R8A779G0_PD_A3IR },
|
||||
{ "a2dma", R8A779G0_PD_A2DMA, R8A779G0_PD_A3IR },
|
||||
{ "a2cv0", R8A779G0_PD_A2CV0, R8A779G0_PD_A3IR },
|
||||
{ "a2cv1", R8A779G0_PD_A2CV1, R8A779G0_PD_A3IR },
|
||||
{ "a2cv2", R8A779G0_PD_A2CV2, R8A779G0_PD_A3IR },
|
||||
{ "a2cv3", R8A779G0_PD_A2CV3, R8A779G0_PD_A3IR },
|
||||
};
|
||||
|
||||
const struct rcar_gen4_sysc_info r8a779g0_sysc_info __initconst = {
|
||||
.areas = r8a779g0_areas,
|
||||
.num_areas = ARRAY_SIZE(r8a779g0_areas),
|
||||
};
|
||||
@ -281,6 +281,9 @@ static const struct of_device_id rcar_gen4_sysc_matches[] __initconst = {
|
||||
#endif
|
||||
#ifdef CONFIG_SYSC_R8A779F0
|
||||
{ .compatible = "renesas,r8a779f0-sysc", .data = &r8a779f0_sysc_info },
|
||||
#endif
|
||||
#ifdef CONFIG_SYSC_R8A779G0
|
||||
{ .compatible = "renesas,r8a779g0-sysc", .data = &r8a779g0_sysc_info },
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
@ -39,5 +39,6 @@ struct rcar_gen4_sysc_info {
|
||||
|
||||
extern const struct rcar_gen4_sysc_info r8a779a0_sysc_info;
|
||||
extern const struct rcar_gen4_sysc_info r8a779f0_sysc_info;
|
||||
extern const struct rcar_gen4_sysc_info r8a779g0_sysc_info;
|
||||
|
||||
#endif /* __SOC_RENESAS_RCAR_GEN4_SYSC_H__ */
|
||||
|
||||
@ -103,6 +103,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
|
||||
/* R-Car Gen4 */
|
||||
{ .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_gen4 },
|
||||
{ .compatible = "renesas,r8a779f0-rst", .data = &rcar_rst_gen4 },
|
||||
{ .compatible = "renesas,r8a779g0-rst", .data = &rcar_rst_gen4 },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
||||
@ -232,7 +232,7 @@ static const struct renesas_soc soc_rcar_d3 __initconst __maybe_unused = {
|
||||
};
|
||||
|
||||
static const struct renesas_soc soc_rcar_v3u __initconst __maybe_unused = {
|
||||
.family = &fam_rcar_gen3,
|
||||
.family = &fam_rcar_gen4,
|
||||
.id = 0x59,
|
||||
};
|
||||
|
||||
@ -241,6 +241,11 @@ static const struct renesas_soc soc_rcar_s4 __initconst __maybe_unused = {
|
||||
.id = 0x5a,
|
||||
};
|
||||
|
||||
static const struct renesas_soc soc_rcar_v4h __initconst __maybe_unused = {
|
||||
.family = &fam_rcar_gen4,
|
||||
.id = 0x5c,
|
||||
};
|
||||
|
||||
static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = {
|
||||
.family = &fam_shmobile,
|
||||
.id = 0x37,
|
||||
@ -349,6 +354,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
|
||||
#ifdef CONFIG_ARCH_R8A779F0
|
||||
{ .compatible = "renesas,r8a779f0", .data = &soc_rcar_s4 },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_R8A779G0
|
||||
{ .compatible = "renesas,r8a779g0", .data = &soc_rcar_v4h },
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_R9A07G043)
|
||||
{ .compatible = "renesas,r9a07g043", .data = &soc_rz_g2ul },
|
||||
#endif
|
||||
|
||||
90
include/dt-bindings/clock/r8a779g0-cpg-mssr.h
Normal file
90
include/dt-bindings/clock/r8a779g0-cpg-mssr.h
Normal file
@ -0,0 +1,90 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2022 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a779g0 CPG Core Clocks */
|
||||
|
||||
#define R8A779G0_CLK_ZX 0
|
||||
#define R8A779G0_CLK_ZS 1
|
||||
#define R8A779G0_CLK_ZT 2
|
||||
#define R8A779G0_CLK_ZTR 3
|
||||
#define R8A779G0_CLK_S0D2 4
|
||||
#define R8A779G0_CLK_S0D3 5
|
||||
#define R8A779G0_CLK_S0D4 6
|
||||
#define R8A779G0_CLK_S0D1_VIO 7
|
||||
#define R8A779G0_CLK_S0D2_VIO 8
|
||||
#define R8A779G0_CLK_S0D4_VIO 9
|
||||
#define R8A779G0_CLK_S0D8_VIO 10
|
||||
#define R8A779G0_CLK_S0D1_VC 11
|
||||
#define R8A779G0_CLK_S0D2_VC 12
|
||||
#define R8A779G0_CLK_S0D4_VC 13
|
||||
#define R8A779G0_CLK_S0D2_MM 14
|
||||
#define R8A779G0_CLK_S0D4_MM 15
|
||||
#define R8A779G0_CLK_S0D2_U3DG 16
|
||||
#define R8A779G0_CLK_S0D4_U3DG 17
|
||||
#define R8A779G0_CLK_S0D2_RT 18
|
||||
#define R8A779G0_CLK_S0D3_RT 19
|
||||
#define R8A779G0_CLK_S0D4_RT 20
|
||||
#define R8A779G0_CLK_S0D6_RT 21
|
||||
#define R8A779G0_CLK_S0D24_RT 22
|
||||
#define R8A779G0_CLK_S0D2_PER 23
|
||||
#define R8A779G0_CLK_S0D3_PER 24
|
||||
#define R8A779G0_CLK_S0D4_PER 25
|
||||
#define R8A779G0_CLK_S0D6_PER 26
|
||||
#define R8A779G0_CLK_S0D12_PER 27
|
||||
#define R8A779G0_CLK_S0D24_PER 28
|
||||
#define R8A779G0_CLK_S0D1_HSC 29
|
||||
#define R8A779G0_CLK_S0D2_HSC 30
|
||||
#define R8A779G0_CLK_S0D4_HSC 31
|
||||
#define R8A779G0_CLK_S0D2_CC 32
|
||||
#define R8A779G0_CLK_SVD1_IR 33
|
||||
#define R8A779G0_CLK_SVD2_IR 34
|
||||
#define R8A779G0_CLK_SVD1_VIP 35
|
||||
#define R8A779G0_CLK_SVD2_VIP 36
|
||||
#define R8A779G0_CLK_CL 37
|
||||
#define R8A779G0_CLK_CL16M 38
|
||||
#define R8A779G0_CLK_CL16M_MM 39
|
||||
#define R8A779G0_CLK_CL16M_RT 40
|
||||
#define R8A779G0_CLK_CL16M_PER 41
|
||||
#define R8A779G0_CLK_CL16M_HSC 42
|
||||
#define R8A779G0_CLK_Z0 43
|
||||
#define R8A779G0_CLK_ZB3 44
|
||||
#define R8A779G0_CLK_ZB3D2 45
|
||||
#define R8A779G0_CLK_ZB3D4 46
|
||||
#define R8A779G0_CLK_ZG 47
|
||||
#define R8A779G0_CLK_SD0H 48
|
||||
#define R8A779G0_CLK_SD0 49
|
||||
#define R8A779G0_CLK_RPC 50
|
||||
#define R8A779G0_CLK_RPCD2 51
|
||||
#define R8A779G0_CLK_MSO 52
|
||||
#define R8A779G0_CLK_CANFD 53
|
||||
#define R8A779G0_CLK_CSI 54
|
||||
#define R8A779G0_CLK_FRAY 55
|
||||
#define R8A779G0_CLK_IPC 56
|
||||
#define R8A779G0_CLK_SASYNCRT 57
|
||||
#define R8A779G0_CLK_SASYNCPERD1 58
|
||||
#define R8A779G0_CLK_SASYNCPERD2 59
|
||||
#define R8A779G0_CLK_SASYNCPERD4 60
|
||||
#define R8A779G0_CLK_VIOBUS 61
|
||||
#define R8A779G0_CLK_VIOBUSD2 62
|
||||
#define R8A779G0_CLK_VCBUS 63
|
||||
#define R8A779G0_CLK_VCBUSD2 64
|
||||
#define R8A779G0_CLK_DSIEXT 65
|
||||
#define R8A779G0_CLK_DSIREF 66
|
||||
#define R8A779G0_CLK_ADGH 67
|
||||
#define R8A779G0_CLK_OSC 68
|
||||
#define R8A779G0_CLK_ZR0 69
|
||||
#define R8A779G0_CLK_ZR1 70
|
||||
#define R8A779G0_CLK_ZR2 71
|
||||
#define R8A779G0_CLK_IMPA 72
|
||||
#define R8A779G0_CLK_IMPAD4 73
|
||||
#define R8A779G0_CLK_CPEX 74
|
||||
#define R8A779G0_CLK_CBFUSA 75
|
||||
#define R8A779G0_CLK_R 76
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */
|
||||
45
include/dt-bindings/power/r8a779g0-sysc.h
Normal file
45
include/dt-bindings/power/r8a779g0-sysc.h
Normal file
@ -0,0 +1,45 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2022 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the Power Domain Register Numbers (PDR)
|
||||
*/
|
||||
|
||||
#define R8A779G0_PD_A1E0D0C0 0
|
||||
#define R8A779G0_PD_A1E0D0C1 1
|
||||
#define R8A779G0_PD_A1E0D1C0 2
|
||||
#define R8A779G0_PD_A1E0D1C1 3
|
||||
#define R8A779G0_PD_A2E0D0 16
|
||||
#define R8A779G0_PD_A2E0D1 17
|
||||
#define R8A779G0_PD_A3E0 20
|
||||
#define R8A779G0_PD_A33DGA 24
|
||||
#define R8A779G0_PD_A23DGB 25
|
||||
#define R8A779G0_PD_A1DSP0 33
|
||||
#define R8A779G0_PD_A2IMP01 34
|
||||
#define R8A779G0_PD_A2PSC 35
|
||||
#define R8A779G0_PD_A2CV0 36
|
||||
#define R8A779G0_PD_A2CV1 37
|
||||
#define R8A779G0_PD_A1CNN0 41
|
||||
#define R8A779G0_PD_A2CN0 42
|
||||
#define R8A779G0_PD_A3IR 43
|
||||
#define R8A779G0_PD_A1DSP1 45
|
||||
#define R8A779G0_PD_A2IMP23 46
|
||||
#define R8A779G0_PD_A2DMA 47
|
||||
#define R8A779G0_PD_A2CV2 48
|
||||
#define R8A779G0_PD_A2CV3 49
|
||||
#define R8A779G0_PD_A1DSP2 53
|
||||
#define R8A779G0_PD_A1DSP3 54
|
||||
#define R8A779G0_PD_A3VIP0 56
|
||||
#define R8A779G0_PD_A3VIP1 57
|
||||
#define R8A779G0_PD_A3VIP2 58
|
||||
#define R8A779G0_PD_A3ISP0 60
|
||||
#define R8A779G0_PD_A3ISP1 61
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A779G0_PD_ALWAYS_ON 64
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/
|
||||
Loading…
x
Reference in New Issue
Block a user