drm/i915/dpio: Clean up bxt/glk PHY registers
Use REG_BIT() & co. for the bxt/glk PHY register definitons. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240412175818.29217-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä
parent
e78b8e8f0c
commit
8221a6229a
@ -295,9 +295,9 @@ void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
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intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val);
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val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch));
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val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
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val |= trans->entries[level].bxt.margin << MARGIN_000_SHIFT |
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trans->entries[level].bxt.scale << UNIQ_TRANS_SCALE_SHIFT;
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val &= ~(MARGIN_000_MASK | UNIQ_TRANS_SCALE_MASK);
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val |= MARGIN_000(trans->entries[level].bxt.margin) |
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UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale);
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intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val);
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val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch));
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@ -312,8 +312,8 @@ void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
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intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val);
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val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch));
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val &= ~DE_EMPHASIS;
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val |= trans->entries[level].bxt.deemphasis << DEEMPH_SHIFT;
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val &= ~DE_EMPHASIS_MASK;
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val |= DE_EMPHASIS(trans->entries[level].bxt.deemphasis);
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intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val);
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val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch));
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@ -353,7 +353,7 @@ static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
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{
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u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy));
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return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
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return REG_FIELD_GET(GRC_CODE_MASK, val);
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}
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static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
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@ -405,11 +405,11 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
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phy);
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/* Program PLL Rcomp code offset */
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intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy), IREF0RC_OFFSET_MASK,
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0xE4 << IREF0RC_OFFSET_SHIFT);
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intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy),
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IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xE4));
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intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy), IREF1RC_OFFSET_MASK,
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0xE4 << IREF1RC_OFFSET_SHIFT);
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intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy),
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IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xE4));
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/* Program power gating */
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intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW28(phy), 0,
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@ -432,9 +432,9 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
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val = bxt_get_grc(dev_priv, phy_info->rcomp_phy);
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dev_priv->display.state.bxt_phy_grc = val;
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grc_code = val << GRC_CODE_FAST_SHIFT |
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val << GRC_CODE_SLOW_SHIFT |
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val;
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grc_code = GRC_CODE_FAST(val) |
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GRC_CODE_SLOW(val) |
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GRC_CODE_NOM(val);
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intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);
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intel_de_rmw(dev_priv, BXT_PORT_REF_DW8(phy),
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0, GRC_DIS | GRC_RDY_OVRD);
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@ -530,16 +530,16 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
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/* PLL Rcomp code offset */
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ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
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IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
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"BXT_PORT_CL1CM_DW9(%d)", phy);
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IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xe4),
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"BXT_PORT_CL1CM_DW9(%d)", phy);
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ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
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IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
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"BXT_PORT_CL1CM_DW10(%d)", phy);
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IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xe4),
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"BXT_PORT_CL1CM_DW10(%d)", phy);
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/* Power gating */
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mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
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ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
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"BXT_PORT_CL1CM_DW28(%d)", phy);
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"BXT_PORT_CL1CM_DW28(%d)", phy);
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if (phy_info->dual_channel)
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ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
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@ -549,9 +549,9 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
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if (phy_info->rcomp_phy != -1) {
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u32 grc_code = dev_priv->display.state.bxt_phy_grc;
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grc_code = grc_code << GRC_CODE_FAST_SHIFT |
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grc_code << GRC_CODE_SLOW_SHIFT |
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grc_code;
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grc_code = GRC_CODE_FAST(grc_code) |
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GRC_CODE_SLOW(grc_code) |
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GRC_CODE_NOM(grc_code);
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mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
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GRC_CODE_NOM_MASK;
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ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
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@ -559,7 +559,7 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
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mask = GRC_DIS | GRC_RDY_OVRD;
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ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
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"BXT_PORT_REF_DW8(%d)", phy);
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"BXT_PORT_REF_DW8(%d)", phy);
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}
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return ok;
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@ -648,32 +648,32 @@
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/* BXT PHY common lane registers */
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#define _PORT_CL1CM_DW0_A 0x162000
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#define _PORT_CL1CM_DW0_BC 0x6C000
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#define PHY_POWER_GOOD (1 << 16)
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#define PHY_RESERVED (1 << 7)
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#define PHY_POWER_GOOD REG_BIT(16)
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#define PHY_RESERVED REG_BIT(7)
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#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
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#define _PORT_CL1CM_DW9_A 0x162024
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#define _PORT_CL1CM_DW9_BC 0x6C024
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#define IREF0RC_OFFSET_SHIFT 8
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#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
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#define IREF0RC_OFFSET_MASK REG_GENMASK(15, 8)
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#define IREF0RC_OFFSET(x) REG_FIELD_PREP(IREF0RC_OFFSET_MASK, (x))
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#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
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#define _PORT_CL1CM_DW10_A 0x162028
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#define _PORT_CL1CM_DW10_BC 0x6C028
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#define IREF1RC_OFFSET_SHIFT 8
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#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
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#define IREF1RC_OFFSET_MASK REG_GENMASK(15, 8)
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#define IREF1RC_OFFSET(x) REG_FIELD_PREP(IREF1RC_OFFSET_MASK, (x))
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#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
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#define _PORT_CL1CM_DW28_A 0x162070
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#define _PORT_CL1CM_DW28_BC 0x6C070
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#define OCL1_POWER_DOWN_EN (1 << 23)
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#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
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#define SUS_CLK_CONFIG 0x3
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#define OCL1_POWER_DOWN_EN REG_BIT(23)
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#define DW28_OLDO_DYN_PWR_DOWN_EN REG_BIT(22)
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#define SUS_CLK_CONFIG REG_GENMASK(1, 0)
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#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
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#define _PORT_CL1CM_DW30_A 0x162078
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#define _PORT_CL1CM_DW30_BC 0x6C078
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#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
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#define OCL2_LDOFUSE_PWR_DIS REG_BIT(6)
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#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
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/* The spec defines this only for BXT PHY0, but lets assume that this
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@ -682,29 +682,30 @@
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#define _PORT_CL2CM_DW6_A 0x162358
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#define _PORT_CL2CM_DW6_BC 0x6C358
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#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
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#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
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#define DW6_OLDO_DYN_PWR_DOWN_EN REG_BIT(28)
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/* BXT PHY Ref registers */
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#define _PORT_REF_DW3_A 0x16218C
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#define _PORT_REF_DW3_BC 0x6C18C
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#define GRC_DONE (1 << 22)
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#define GRC_DONE REG_BIT(22)
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#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
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#define _PORT_REF_DW6_A 0x162198
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#define _PORT_REF_DW6_BC 0x6C198
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#define GRC_CODE_SHIFT 24
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#define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
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#define GRC_CODE_FAST_SHIFT 16
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#define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
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#define GRC_CODE_SLOW_SHIFT 8
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#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
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#define GRC_CODE_NOM_MASK 0xFF
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#define GRC_CODE_MASK REG_GENMASK(31, 24)
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#define GRC_CODE(x) REG_FIELD_PREP(GRC_CODE_MASK, (x))
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#define GRC_CODE_FAST_MASK REG_GENMASK(23, 16)
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#define GRC_CODE_FAST(x) REG_FIELD_PREP(GRC_CODE_FAST_MASK, (x))
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#define GRC_CODE_SLOW_MASK REG_GENMASK(15, 8)
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#define GRC_CODE_SLOW(x) REG_FIELD_PREP(GRC_CODE_SLOW_MASK, (x))
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#define GRC_CODE_NOM_MASK REG_GENMASK(7, 0)
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#define GRC_CODE_NOM(x) REG_FIELD_PREP(GRC_CODE_NOM_MASK, (x))
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#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
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#define _PORT_REF_DW8_A 0x1621A0
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#define _PORT_REF_DW8_BC 0x6C1A0
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#define GRC_DIS (1 << 15)
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#define GRC_RDY_OVRD (1 << 1)
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#define GRC_DIS REG_BIT(15)
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#define GRC_RDY_OVRD REG_BIT(1)
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#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
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/* BXT PHY PCS registers */
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@ -721,8 +722,8 @@
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_PORT_PCS_DW10_GRP_B, \
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_PORT_PCS_DW10_GRP_C)
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#define TX2_SWING_CALC_INIT (1 << 31)
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#define TX1_SWING_CALC_INIT (1 << 30)
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#define TX2_SWING_CALC_INIT REG_BIT(31)
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#define TX1_SWING_CALC_INIT REG_BIT(30)
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#define _PORT_PCS_DW12_LN01_A 0x162430
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#define _PORT_PCS_DW12_LN01_B 0x6C430
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@ -733,8 +734,8 @@
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#define _PORT_PCS_DW12_GRP_A 0x162c30
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#define _PORT_PCS_DW12_GRP_B 0x6CC30
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#define _PORT_PCS_DW12_GRP_C 0x6CE30
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#define LANESTAGGER_STRAP_OVRD (1 << 6)
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#define LANE_STAGGER_MASK 0x1F
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#define LANESTAGGER_STRAP_OVRD REG_BIT(6)
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#define LANE_STAGGER_MASK REG_GENMASK(4, 0)
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#define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
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_PORT_PCS_DW12_LN01_B, \
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_PORT_PCS_DW12_LN01_C)
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@ -761,10 +762,10 @@
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#define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
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_PORT_TX_DW2_GRP_B, \
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_PORT_TX_DW2_GRP_C)
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#define MARGIN_000_SHIFT 16
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#define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
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#define UNIQ_TRANS_SCALE_SHIFT 8
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#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
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#define MARGIN_000_MASK REG_GENMASK(23, 16)
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#define MARGIN_000(x) REG_FIELD_PREP(MARGIN_000_MASK, (x))
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#define UNIQ_TRANS_SCALE_MASK REG_GENMASK(15, 8)
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#define UNIQ_TRANS_SCALE(x) REG_FIELD_PREP(UNIQ_TRANS_SCALE_MASK, (x))
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#define _PORT_TX_DW3_LN0_A 0x16250C
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#define _PORT_TX_DW3_LN0_B 0x6C50C
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@ -778,8 +779,8 @@
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#define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
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_PORT_TX_DW3_GRP_B, \
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_PORT_TX_DW3_GRP_C)
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#define SCALE_DCOMP_METHOD (1 << 26)
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#define UNIQUE_TRANGE_EN_METHOD (1 << 27)
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#define SCALE_DCOMP_METHOD REG_BIT(26)
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#define UNIQUE_TRANGE_EN_METHOD REG_BIT(27)
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#define _PORT_TX_DW4_LN0_A 0x162510
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#define _PORT_TX_DW4_LN0_B 0x6C510
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@ -793,8 +794,8 @@
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#define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
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_PORT_TX_DW4_GRP_B, \
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_PORT_TX_DW4_GRP_C)
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#define DEEMPH_SHIFT 24
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#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
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#define DE_EMPHASIS_MASK REG_GENMASK(31, 24)
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#define DE_EMPHASIS(x) REG_FIELD_PREP(DE_EMPHASIS_MASK, (x))
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#define _PORT_TX_DW5_LN0_A 0x162514
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#define _PORT_TX_DW5_LN0_B 0x6C514
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@ -808,14 +809,13 @@
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#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
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_PORT_TX_DW5_GRP_B, \
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_PORT_TX_DW5_GRP_C)
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#define DCC_DELAY_RANGE_1 (1 << 9)
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#define DCC_DELAY_RANGE_2 (1 << 8)
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#define DCC_DELAY_RANGE_1 REG_BIT(9)
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#define DCC_DELAY_RANGE_2 REG_BIT(8)
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#define _PORT_TX_DW14_LN0_A 0x162538
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#define _PORT_TX_DW14_LN0_B 0x6C538
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#define _PORT_TX_DW14_LN0_C 0x6C938
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#define LATENCY_OPTIM_SHIFT 30
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#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
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#define LATENCY_OPTIM REG_BIT(30)
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#define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
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_MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
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_PORT_TX_DW14_LN0_C) + \
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