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Merge master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfin-2.6

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* master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (30 commits)
  Blackfin serial driver: supporting BF548-EZKIT serial port
  Video Console: Blackfin doesnt support VGA console
  Blackfin arch: Add peripheral io API to gpio header file
  Blackfin arch: set up gpio interrupt IRQ_PJ9 for BF54x ATAPI PATA driver
  Blackfin arch: add missing CONFIG_LARGE_ALLOCS when upstream merging
  Blackfin arch: as pointed out by Robert P. J. Day, update the CPU_FREQ name to match current Kconfig
  Blackfin arch: extract the entry point from the linked kernel
  Blackfin arch: clean up some coding style issues
  Blackfin arch: combine the common code of free_initrd_mem and free_initmem
  Blackfin arch: Add Support for Peripheral PortMux and resouce allocation
  Blackfin arch: use PAGE_SIZE when doing aligns rather than hardcoded values
  Blackfin arch: fix bug set dma_address properly in dma_map_sg
  Blackfin arch: Disable CACHELINE_ALIGNED_L1 for BF54x by default
  Blackfin arch: Port the dm9000 driver to Blackfin by using the correct low-level io routines
  Blackfin arch: There is no CDPRIO Bit in the EBIU_AMGCTL Register of BF54x arch
  Blackfin arch: scrub dead code
  Blackfin arch: Fix Warning add some defines in BF54x header file
  Blackfin arch: add BF54x missing GPIO access functions
  Blackfin arch: Some memory and code optimizations - Fix SYS_IRQS
  Blackfin arch: Enable BF54x PIN/GPIO interrupts
  ...
This commit is contained in:
Linus Torvalds 2007-07-12 13:25:24 -07:00
commit 82afee684f
121 changed files with 9781 additions and 3918 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

155
Documentation/blackfin/kgdb.txt Normal file
View File

@ -0,0 +1,155 @@
A Simple Guide to Configure KGDB
Sonic Zhang <sonic.zhang@analog.com>
Aug. 24th 2006
This KGDB patch enables the kernel developer to do source level debugging on
the kernel for the Blackfin architecture. The debugging works over either the
ethernet interface or one of the uarts. Both software breakpoints and
hardware breakpoints are supported in this version.
http://docs.blackfin.uclinux.org/doku.php?id=kgdb
2 known issues:
1. This bug:
http://blackfin.uclinux.org/tracker/index.php?func=detail&aid=544&group_id=18&atid=145
The GDB client for Blackfin uClinux causes incorrect values of local
variables to be displayed when the user breaks the running of kernel in GDB.
2. Because of a hardware bug in Blackfin 533 v1.0.3:
05000067 - Watchpoints (Hardware Breakpoints) are not supported
Hardware breakpoints cannot be set properly.
Debug over Ethernet:
1. Compile and install the cross platform version of gdb for blackfin, which
can be found at $(BINROOT)/bfin-elf-gdb.
2. Apply this patch to the 2.6.x kernel. Select the menuconfig option under
"Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb".
With this selected, option "Full Symbolic/Source Debugging support" and
"Compile the kernel with frame pointers" are also selected.
3. Select option "KGDB: connect over (Ethernet)". Add "kgdboe=@target-IP/,@host-IP/" to
the option "Compiled-in Kernel Boot Parameter" under "Kernel hacking".
4. Connect minicom to the serial port and boot the kernel image.
5. Configure the IP "/> ifconfig eth0 target-IP"
6. Start GDB client "bfin-elf-gdb vmlinux".
7. Connect to the target "(gdb) target remote udp:target-IP:6443".
8. Set software breakpoint "(gdb) break sys_open".
9. Continue "(gdb) c".
10. Run ls in the target console "/> ls".
11. Breakpoint hits. "Breakpoint 1: sys_open(..."
12. Display local variables and function paramters.
(*) This operation gives wrong results, see known issue 1.
13. Single stepping "(gdb) si".
14. Remove breakpoint 1. "(gdb) del 1"
15. Set hardware breakpoint "(gdb) hbreak sys_open".
16. Continue "(gdb) c".
17. Run ls in the target console "/> ls".
18. Hardware breakpoint hits. "Breakpoint 1: sys_open(...".
(*) This hardware breakpoint will not be hit, see known issue 2.
19. Continue "(gdb) c".
20. Interrupt the target in GDB "Ctrl+C".
21. Detach from the target "(gdb) detach".
22. Exit GDB "(gdb) quit".
Debug over the UART:
1. Compile and install the cross platform version of gdb for blackfin, which
can be found at $(BINROOT)/bfin-elf-gdb.
2. Apply this patch to the 2.6.x kernel. Select the menuconfig option under
"Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb".
With this selected, option "Full Symbolic/Source Debugging support" and
"Compile the kernel with frame pointers" are also selected.
3. Select option "KGDB: connect over (UART)". Set "KGDB: UART port number" to be
a different one from the console. Don't forget to change the mode of
blackfin serial driver to PIO. Otherwise kgdb works incorrectly on UART.
4. If you want connect to kgdb when the kernel boots, enable
"KGDB: Wait for gdb connection early"
5. Compile kernel.
6. Connect minicom to the serial port of the console and boot the kernel image.
7. Start GDB client "bfin-elf-gdb vmlinux".
8. Set the baud rate in GDB "(gdb) set remotebaud 57600".
9. Connect to the target on the second serial port "(gdb) target remote /dev/ttyS1".
10. Set software breakpoint "(gdb) break sys_open".
11. Continue "(gdb) c".
12. Run ls in the target console "/> ls".
13. A breakpoint is hit. "Breakpoint 1: sys_open(..."
14. All other operations are the same as that in KGDB over Ethernet.
Debug over the same UART as console:
1. Compile and install the cross platform version of gdb for blackfin, which
can be found at $(BINROOT)/bfin-elf-gdb.
2. Apply this patch to the 2.6.x kernel. Select the menuconfig option under
"Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb".
With this selected, option "Full Symbolic/Source Debugging support" and
"Compile the kernel with frame pointers" are also selected.
3. Select option "KGDB: connect over UART". Set "KGDB: UART port number" to console.
Don't forget to change the mode of blackfin serial driver to PIO.
Otherwise kgdb works incorrectly on UART.
4. If you want connect to kgdb when the kernel boots, enable
"KGDB: Wait for gdb connection early"
5. Connect minicom to the serial port and boot the kernel image.
6. (Optional) Ask target to wait for gdb connection by entering Ctrl+A. In minicom, you should enter Ctrl+A+A.
7. Start GDB client "bfin-elf-gdb vmlinux".
8. Set the baud rate in GDB "(gdb) set remotebaud 57600".
9. Connect to the target "(gdb) target remote /dev/ttyS0".
10. Set software breakpoint "(gdb) break sys_open".
11. Continue "(gdb) c". Then enter Ctrl+C twice to stop GDB connection.
12. Run ls in the target console "/> ls". Dummy string can be seen on the console.
13. Then connect the gdb to target again. "(gdb) target remote /dev/ttyS0".
Now you will find a breakpoint is hit. "Breakpoint 1: sys_open(..."
14. All other operations are the same as that in KGDB over Ethernet. The only
difference is that after continue command in GDB, please stop GDB
connection by 2 "Ctrl+C"s and connect again after breakpoints are hit or
Ctrl+A is entered.

59
arch/blackfin/Kconfig
View File

@ -71,6 +71,7 @@ config GENERIC_CALIBRATE_DELAY
config IRQCHIP_DEMUX_GPIO
bool
depends on (BF53x || BF561 || BF54x)
default y
source "init/Kconfig"
@ -114,6 +115,26 @@ config BF537
help
BF537 Processor Support.
config BF542
bool "BF542"
help
BF542 Processor Support.
config BF544
bool "BF544"
help
BF544 Processor Support.
config BF548
bool "BF548"
help
BF548 Processor Support.
config BF549
bool "BF549"
help
BF549 Processor Support.
config BF561
bool "BF561"
help
@ -125,6 +146,11 @@ choice
prompt "Silicon Rev"
default BF_REV_0_2 if BF537
default BF_REV_0_3 if BF533
default BF_REV_0_0 if BF549
config BF_REV_0_0
bool "0.0"
depends on (BF549)
config BF_REV_0_2
bool "0.2"
@ -150,6 +176,16 @@ config BF_REV_NONE
endchoice
config BF53x
bool
depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
default y
config BF54x
bool
depends on (BF542 || BF544 || BF548 || BF549)
default y
config BFIN_DUAL_CORE
bool
depends on (BF561)
@ -198,6 +234,12 @@ config BFIN537_BLUETECHNIX_CM
help
CM-BF537 support for EVAL- and DEV-Board.
config BFIN548_EZKIT
bool "BF548-EZKIT"
depends on (BF548 || BF549)
help
BFIN548-EZKIT board Support.
config BFIN561_BLUETECHNIX_CM
bool "Bluetechnix CM-BF561"
depends on (BF561)
@ -265,6 +307,7 @@ config BFIN_SHARED_FLASH_ENET
source "arch/blackfin/mach-bf533/Kconfig"
source "arch/blackfin/mach-bf561/Kconfig"
source "arch/blackfin/mach-bf537/Kconfig"
source "arch/blackfin/mach-bf548/Kconfig"
menu "Board customizations"
@ -497,7 +540,8 @@ config IP_CHECKSUM_L1
config CACHELINE_ALIGNED_L1
bool "Locate cacheline_aligned data to L1 Data Memory"
default y
default y if !BF54x
default n if BF54x
depends on !BF531
help
If enabled cacheline_anligned data is linked
@ -541,9 +585,17 @@ endchoice
source "mm/Kconfig"
config LARGE_ALLOCS
bool "Allow allocating large blocks (> 1MB) of memory"
help
Allow the slab memory allocator to keep chains for very large
memory sizes - upto 32MB. You may need this if your system has
a lot of RAM, and you need to able to allocate very large
contiguous chunks. If unsure, say N.
config BFIN_DMA_5XX
bool "Enable DMA Support"
depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561)
depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561 || BF54x)
default y
help
DMA driver for BF5xx.
@ -686,6 +738,7 @@ config C_AMCKEN
config C_CDPRIO
bool "DMA has priority over core for ext. accesses"
depends on !BF54x
default n
config C_B0PEN
@ -839,7 +892,7 @@ endchoice
endmenu
if (BF537 || BF533)
if (BF537 || BF533 || BF54x)
menu "CPU Frequency scaling"

2
arch/blackfin/Makefile
View File

@ -24,6 +24,8 @@ machine-$(CONFIG_BF533) := bf533
machine-$(CONFIG_BF534) := bf537
machine-$(CONFIG_BF536) := bf537
machine-$(CONFIG_BF537) := bf537
machine-$(CONFIG_BF548) := bf548
machine-$(CONFIG_BF549) := bf548
machine-$(CONFIG_BF561) := bf561
MACHINE := $(machine-y)
export MACHINE

3
arch/blackfin/boot/Makefile
View File

@ -13,7 +13,8 @@ extra-y += vmlinux.bin vmlinux.gz
quiet_cmd_uimage = UIMAGE $@
cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \
-C gzip -a $(CONFIG_BOOT_LOAD) -e $(CONFIG_BOOT_LOAD) -n 'Linux-$(KERNELRELEASE)' \
-C gzip -n 'Linux-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \
-e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \
-d $< $@
$(obj)/vmlinux.bin: vmlinux FORCE

1100
arch/blackfin/configs/BF548-EZKIT_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

7
arch/blackfin/kernel/Makefile
View File

@ -6,9 +6,12 @@ extra-y := init_task.o vmlinux.lds
obj-y := \
entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
sys_bfin.o time.o traps.o irqchip.o dma-mapping.o bfin_gpio.o \
flat.o
sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o \
fixed_code.o cplbinit.o cacheinit.o
obj-$(CONFIG_BF53x) += bfin_gpio.o
obj-$(CONFIG_BF561) += bfin_gpio.o
obj-$(CONFIG_MODULES) += module.o
obj-$(CONFIG_BFIN_DMA_5XX) += bfin_dma_5xx.o
obj-$(CONFIG_DUAL_CORE_TEST_MODULE) += dualcore_test.o
obj-$(CONFIG_KGDB) += kgdb.o

7
arch/blackfin/kernel/asm-offsets.c
View File

@ -32,11 +32,10 @@
#include <linux/kernel_stat.h>
#include <linux/ptrace.h>
#include <linux/hardirq.h>
#include <asm/irq.h>
#include <asm/thread_info.h>
#include <linux/irq.h>
#include <linux/thread_info.h>
#define DEFINE(sym, val) \
asm volatile("\n->" #sym " %0 " #val : : "i" (val))
#define DEFINE(sym, val) asm volatile("\n->" #sym " %0 " #val : : "i" (val))
int main(void)
{

207
arch/blackfin/kernel/bfin_dma_5xx.c
View File

@ -34,6 +34,7 @@
#include <linux/kernel.h>
#include <linux/param.h>
#include <asm/blackfin.h>
#include <asm/dma.h>
#include <asm/cacheflush.h>
@ -45,67 +46,6 @@
***************************************************************************/
static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL];
#if defined (CONFIG_BF561)
static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
(struct dma_register *) DMA1_0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_1_NEXT_DESC_PTR,
(struct dma_register *) DMA1_2_NEXT_DESC_PTR,
(struct dma_register *) DMA1_3_NEXT_DESC_PTR,
(struct dma_register *) DMA1_4_NEXT_DESC_PTR,
(struct dma_register *) DMA1_5_NEXT_DESC_PTR,
(struct dma_register *) DMA1_6_NEXT_DESC_PTR,
(struct dma_register *) DMA1_7_NEXT_DESC_PTR,
(struct dma_register *) DMA1_8_NEXT_DESC_PTR,
(struct dma_register *) DMA1_9_NEXT_DESC_PTR,
(struct dma_register *) DMA1_10_NEXT_DESC_PTR,
(struct dma_register *) DMA1_11_NEXT_DESC_PTR,
(struct dma_register *) DMA2_0_NEXT_DESC_PTR,
(struct dma_register *) DMA2_1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_2_NEXT_DESC_PTR,
(struct dma_register *) DMA2_3_NEXT_DESC_PTR,
(struct dma_register *) DMA2_4_NEXT_DESC_PTR,
(struct dma_register *) DMA2_5_NEXT_DESC_PTR,
(struct dma_register *) DMA2_6_NEXT_DESC_PTR,
(struct dma_register *) DMA2_7_NEXT_DESC_PTR,
(struct dma_register *) DMA2_8_NEXT_DESC_PTR,
(struct dma_register *) DMA2_9_NEXT_DESC_PTR,
(struct dma_register *) DMA2_10_NEXT_DESC_PTR,
(struct dma_register *) DMA2_11_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
};
#else
static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
(struct dma_register *) DMA0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_NEXT_DESC_PTR,
(struct dma_register *) DMA3_NEXT_DESC_PTR,
(struct dma_register *) DMA4_NEXT_DESC_PTR,
(struct dma_register *) DMA5_NEXT_DESC_PTR,
(struct dma_register *) DMA6_NEXT_DESC_PTR,
(struct dma_register *) DMA7_NEXT_DESC_PTR,
#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536))
(struct dma_register *) DMA8_NEXT_DESC_PTR,
(struct dma_register *) DMA9_NEXT_DESC_PTR,
(struct dma_register *) DMA10_NEXT_DESC_PTR,
(struct dma_register *) DMA11_NEXT_DESC_PTR,
#endif
(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
};
#endif
/*------------------------------------------------------------------------------
* Set the Buffer Clear bit in the Configuration register of specific DMA
@ -138,149 +78,6 @@ static int __init blackfin_dma_init(void)
arch_initcall(blackfin_dma_init);
/*
* Form the channel find the irq number for that channel.
*/
#if !defined(CONFIG_BF561)
static int bf533_channel2irq(unsigned int channel)
{
int ret_irq = -1;
switch (channel) {
case CH_PPI:
ret_irq = IRQ_PPI;
break;
#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536))
case CH_EMAC_RX:
ret_irq = IRQ_MAC_RX;
break;
case CH_EMAC_TX:
ret_irq = IRQ_MAC_TX;
break;
case CH_UART1_RX:
ret_irq = IRQ_UART1_RX;
break;
case CH_UART1_TX:
ret_irq = IRQ_UART1_TX;
break;
#endif
case CH_SPORT0_RX:
ret_irq = IRQ_SPORT0_RX;
break;
case CH_SPORT0_TX:
ret_irq = IRQ_SPORT0_TX;
break;
case CH_SPORT1_RX:
ret_irq = IRQ_SPORT1_RX;
break;
case CH_SPORT1_TX:
ret_irq = IRQ_SPORT1_TX;
break;
case CH_SPI:
ret_irq = IRQ_SPI;
break;
case CH_UART_RX:
ret_irq = IRQ_UART_RX;
break;
case CH_UART_TX:
ret_irq = IRQ_UART_TX;
break;
case CH_MEM_STREAM0_SRC:
case CH_MEM_STREAM0_DEST:
ret_irq = IRQ_MEM_DMA0;
break;
case CH_MEM_STREAM1_SRC:
case CH_MEM_STREAM1_DEST:
ret_irq = IRQ_MEM_DMA1;
break;
}
return ret_irq;
}
# define channel2irq(channel) bf533_channel2irq(channel)
#else
static int bf561_channel2irq(unsigned int channel)
{
int ret_irq = -1;
switch (channel) {
case CH_PPI0:
ret_irq = IRQ_PPI0;
break;
case CH_PPI1:
ret_irq = IRQ_PPI1;
break;
case CH_SPORT0_RX:
ret_irq = IRQ_SPORT0_RX;
break;
case CH_SPORT0_TX:
ret_irq = IRQ_SPORT0_TX;
break;
case CH_SPORT1_RX:
ret_irq = IRQ_SPORT1_RX;
break;
case CH_SPORT1_TX:
ret_irq = IRQ_SPORT1_TX;
break;
case CH_SPI:
ret_irq = IRQ_SPI;
break;
case CH_UART_RX:
ret_irq = IRQ_UART_RX;
break;
case CH_UART_TX:
ret_irq = IRQ_UART_TX;
break;
case CH_MEM_STREAM0_SRC:
case CH_MEM_STREAM0_DEST:
ret_irq = IRQ_MEM_DMA0;
break;
case CH_MEM_STREAM1_SRC:
case CH_MEM_STREAM1_DEST:
ret_irq = IRQ_MEM_DMA1;
break;
case CH_MEM_STREAM2_SRC:
case CH_MEM_STREAM2_DEST:
ret_irq = IRQ_MEM_DMA2;
break;
case CH_MEM_STREAM3_SRC:
case CH_MEM_STREAM3_DEST:
ret_irq = IRQ_MEM_DMA3;
break;
case CH_IMEM_STREAM0_SRC:
case CH_IMEM_STREAM0_DEST:
ret_irq = IRQ_IMEM_DMA0;
break;
case CH_IMEM_STREAM1_SRC:
case CH_IMEM_STREAM1_DEST:
ret_irq = IRQ_IMEM_DMA1;
break;
}
return ret_irq;
}
# define channel2irq(channel) bf561_channel2irq(channel)
#endif
/*------------------------------------------------------------------------------
* Request the specific DMA channel from the system.
*-----------------------------------------------------------------------------*/
@ -748,7 +545,6 @@ void *dma_memcpy(void *dest, const void *src, size_t size)
addr = __dma_memcpy(dest+bulk, src+bulk, rest);
return addr;
}
EXPORT_SYMBOL(dma_memcpy);
void *safe_dma_memcpy(void *dest, const void *src, size_t size)
@ -761,7 +557,6 @@ EXPORT_SYMBOL(safe_dma_memcpy);
void dma_outsb(void __iomem *addr, const void *buf, unsigned short len)
{
unsigned long flags;
local_irq_save(flags);

3
arch/blackfin/kernel/bfin_gpio.c
View File

@ -522,7 +522,6 @@ u32 gpio_pm_setup(void)
return IWR_ENABLE_ALL;
}
void gpio_pm_restore(void)
{
u16 bank, mask, i;
@ -591,7 +590,6 @@ int gpio_request(unsigned short gpio, const char *label)
}
EXPORT_SYMBOL(gpio_request);
void gpio_free(unsigned short gpio)
{
unsigned long flags;
@ -616,7 +614,6 @@ void gpio_free(unsigned short gpio)
}
EXPORT_SYMBOL(gpio_free);
void gpio_direction_input(unsigned short gpio)
{
unsigned long flags;

5
arch/blackfin/kernel/bfin_ksyms.c
View File

@ -28,10 +28,11 @@
*/
#include <linux/module.h>
#include <asm/irq.h>
#include <linux/irq.h>
#include <linux/uaccess.h>
#include <asm/checksum.h>
#include <asm/cacheflush.h>
#include <asm/uaccess.h>
/* platform dependent support */

66
arch/blackfin/kernel/cacheinit.c Normal file
View File

@ -0,0 +1,66 @@
/*
* Copyright 2004-2007 Analog Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/cpu.h>
#include <asm/cacheflush.h>
#include <asm/blackfin.h>
#include <asm/cplbinit.h>
#if defined(CONFIG_BLKFIN_CACHE)
void bfin_icache_init(void)
{
unsigned long *table = icplb_table;
unsigned long ctrl;
int i;
for (i = 0; i < MAX_CPLBS; i++) {
unsigned long addr = *table++;
unsigned long data = *table++;
if (addr == (unsigned long)-1)
break;
bfin_write32(ICPLB_ADDR0 + i * 4, addr);
bfin_write32(ICPLB_DATA0 + i * 4, data);
}
ctrl = bfin_read_IMEM_CONTROL();
ctrl |= IMC | ENICPLB;
bfin_write_IMEM_CONTROL(ctrl);
}
#endif
#if defined(CONFIG_BLKFIN_DCACHE)
void bfin_dcache_init(void)
{
unsigned long *table = dcplb_table;
unsigned long ctrl;
int i;
for (i = 0; i < MAX_CPLBS; i++) {
unsigned long addr = *table++;
unsigned long data = *table++;
if (addr == (unsigned long)-1)
break;
bfin_write32(DCPLB_ADDR0 + i * 4, addr);
bfin_write32(DCPLB_DATA0 + i * 4, data);
}
ctrl = bfin_read_DMEM_CONTROL();
ctrl |= DMEM_CNTR;
bfin_write_DMEM_CONTROL(ctrl);
}
#endif

433
arch/blackfin/kernel/cplbinit.c Normal file
View File

@ -0,0 +1,433 @@
/*
* Blackfin CPLB initialization
*
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/module.h>
#include <asm/blackfin.h>
#include <asm/cplbinit.h>
u_long icplb_table[MAX_CPLBS+1];
u_long dcplb_table[MAX_CPLBS+1];
#ifdef CONFIG_CPLB_SWITCH_TAB_L1
u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
#ifdef CONFIG_CPLB_INFO
u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
#endif /* CONFIG_CPLB_INFO */
#else
u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
#ifdef CONFIG_CPLB_INFO
u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
#endif /* CONFIG_CPLB_INFO */
#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
struct s_cplb {
struct cplb_tab init_i;
struct cplb_tab init_d;
struct cplb_tab switch_i;
struct cplb_tab switch_d;
};
#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
static struct cplb_desc cplb_data[] = {
{
.start = 0,
.end = SIZE_1K,
.psize = SIZE_1K,
.attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
.i_conf = SDRAM_OOPS,
.d_conf = SDRAM_OOPS,
#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
.valid = 1,
#else
.valid = 0,
#endif
.name = "ZERO Pointer Saveguard",
},
{
.start = L1_CODE_START,
.end = L1_CODE_START + L1_CODE_LENGTH,
.psize = SIZE_4M,
.attr = INITIAL_T | SWITCH_T | I_CPLB,
.i_conf = L1_IMEMORY,
.d_conf = 0,
.valid = 1,
.name = "L1 I-Memory",
},
{
.start = L1_DATA_A_START,
.end = L1_DATA_B_START + L1_DATA_B_LENGTH,
.psize = SIZE_4M,
.attr = INITIAL_T | SWITCH_T | D_CPLB,
.i_conf = 0,
.d_conf = L1_DMEMORY,
#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
.valid = 1,
#else
.valid = 0,
#endif
.name = "L1 D-Memory",
},
{
.start = 0,
.end = 0, /* dynamic */
.psize = 0,
.attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
.i_conf = SDRAM_IGENERIC,
.d_conf = SDRAM_DGENERIC,
.valid = 1,
.name = "SDRAM Kernel",
},
{
.start = 0, /* dynamic */
.end = 0, /* dynamic */
.psize = 0,
.attr = INITIAL_T | SWITCH_T | D_CPLB,
.i_conf = SDRAM_IGENERIC,
.d_conf = SDRAM_DNON_CHBL,
.valid = 1,
.name = "SDRAM RAM MTD",
},
{
.start = 0, /* dynamic */
.end = 0, /* dynamic */
.psize = SIZE_1M,
.attr = INITIAL_T | SWITCH_T | D_CPLB,
.d_conf = SDRAM_DNON_CHBL,
.valid = 1,
.name = "SDRAM Uncached DMA ZONE",
},
{
.start = 0, /* dynamic */
.end = 0, /* dynamic */
.psize = 0,
.attr = SWITCH_T | D_CPLB,
.i_conf = 0, /* dynamic */
.d_conf = 0, /* dynamic */
.valid = 1,
.name = "SDRAM Reserved Memory",
},
{
.start = ASYNC_BANK0_BASE,
.end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
.psize = 0,
.attr = SWITCH_T | D_CPLB,
.d_conf = SDRAM_EBIU,
.valid = 1,
.name = "ASYNC Memory",
},
{
#if defined(CONFIG_BF561)
.start = L2_SRAM,
.end = L2_SRAM_END,
.psize = SIZE_1M,
.attr = SWITCH_T | D_CPLB,
.i_conf = L2_MEMORY,
.d_conf = L2_MEMORY,
.valid = 1,
#else
.valid = 0,
#endif
.name = "L2 Memory",
}
};
static u16 __init lock_kernel_check(u32 start, u32 end)
{
if ((start <= (u32) _stext && end >= (u32) _end)
|| (start >= (u32) _stext && end <= (u32) _end))
return IN_KERNEL;
return 0;
}
static unsigned short __init
fill_cplbtab(struct cplb_tab *table,
unsigned long start, unsigned long end,
unsigned long block_size, unsigned long cplb_data)
{
int i;
switch (block_size) {
case SIZE_4M:
i = 3;
break;
case SIZE_1M:
i = 2;
break;
case SIZE_4K:
i = 1;
break;
case SIZE_1K:
default:
i = 0;
break;
}
cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
while ((start < end) && (table->pos < table->size)) {
table->tab[table->pos++] = start;
if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
table->tab[table->pos++] =
cplb_data | CPLB_LOCK | CPLB_DIRTY;
else
table->tab[table->pos++] = cplb_data;
start += block_size;
}
return 0;
}
static unsigned short __init
close_cplbtab(struct cplb_tab *table)
{
while (table->pos < table->size) {
table->tab[table->pos++] = 0;
table->tab[table->pos++] = 0; /* !CPLB_VALID */
}
return 0;
}
/* helper function */
static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
{
if (cplb_data[i].psize) {
fill_cplbtab(t,
cplb_data[i].start,
cplb_data[i].end,
cplb_data[i].psize,
cplb_data[i].i_conf);
} else {
#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
if (i == SDRAM_KERN) {
fill_cplbtab(t,
cplb_data[i].start,
cplb_data[i].end,
SIZE_4M,
cplb_data[i].i_conf);
} else
#endif
{
fill_cplbtab(t,
cplb_data[i].start,
a_start,
SIZE_1M,
cplb_data[i].i_conf);
fill_cplbtab(t,
a_start,
a_end,
SIZE_4M,
cplb_data[i].i_conf);
fill_cplbtab(t, a_end,
cplb_data[i].end,
SIZE_1M,
cplb_data[i].i_conf);
}
}
}
static void __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
{
if (cplb_data[i].psize) {
fill_cplbtab(t,
cplb_data[i].start,
cplb_data[i].end,
cplb_data[i].psize,
cplb_data[i].d_conf);
} else {
fill_cplbtab(t,
cplb_data[i].start,
a_start, SIZE_1M,
cplb_data[i].d_conf);
fill_cplbtab(t, a_start,
a_end, SIZE_4M,
cplb_data[i].d_conf);
fill_cplbtab(t, a_end,
cplb_data[i].end,
SIZE_1M,
cplb_data[i].d_conf);
}
}
void __init generate_cpl_tables(void)
{
u16 i, j, process;
u32 a_start, a_end, as, ae, as_1m;
struct cplb_tab *t_i = NULL;
struct cplb_tab *t_d = NULL;
struct s_cplb cplb;
cplb.init_i.size = MAX_CPLBS;
cplb.init_d.size = MAX_CPLBS;
cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
cplb.init_i.pos = 0;
cplb.init_d.pos = 0;
cplb.switch_i.pos = 0;
cplb.switch_d.pos = 0;
cplb.init_i.tab = icplb_table;
cplb.init_d.tab = dcplb_table;
cplb.switch_i.tab = ipdt_table;
cplb.switch_d.tab = dpdt_table;
cplb_data[SDRAM_KERN].end = memory_end;
#ifdef CONFIG_MTD_UCLINUX
cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
# if defined(CONFIG_ROMFS_FS)
cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
/*
* The ROMFS_FS size is often not multiple of 1MB.
* This can cause multiple CPLB sets covering the same memory area.
* This will then cause multiple CPLB hit exceptions.
* Workaround: We ensure a contiguous memory area by extending the kernel
* memory section over the mtd section.
* For ROMFS_FS memory must be covered with ICPLBs anyways.
* So there is no difference between kernel and mtd memory setup.
*/
cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
cplb_data[SDRAM_RAM_MTD].valid = 0;
# endif
#else
cplb_data[SDRAM_RAM_MTD].valid = 0;
#endif
cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
cplb_data[SDRAM_DMAZ].end = _ramend;
cplb_data[RES_MEM].start = _ramend;
cplb_data[RES_MEM].end = physical_mem_end;
if (reserved_mem_dcache_on)
cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
else
cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
if (reserved_mem_icache_on)
cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
else
cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
for (i = ZERO_P; i <= L2_MEM; i++) {
if (!cplb_data[i].valid)
continue;
as_1m = cplb_data[i].start % SIZE_1M;
/* We need to make sure all sections are properly 1M aligned
* However between Kernel Memory and the Kernel mtd section, depending on the
* rootfs size, there can be overlapping memory areas.
*/
if (as_1m && i != L1I_MEM && i != L1D_MEM) {
#ifdef CONFIG_MTD_UCLINUX
if (i == SDRAM_RAM_MTD) {
if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
else
cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
} else
#endif
printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
cplb_data[i].name, cplb_data[i].start);
}
as = cplb_data[i].start % SIZE_4M;
ae = cplb_data[i].end % SIZE_4M;
if (as)
a_start = cplb_data[i].start + (SIZE_4M - (as));
else
a_start = cplb_data[i].start;
a_end = cplb_data[i].end - ae;
for (j = INITIAL_T; j <= SWITCH_T; j++) {
switch (j) {
case INITIAL_T:
if (cplb_data[i].attr & INITIAL_T) {
t_i = &cplb.init_i;
t_d = &cplb.init_d;
process = 1;
} else
process = 0;
break;
case SWITCH_T:
if (cplb_data[i].attr & SWITCH_T) {
t_i = &cplb.switch_i;
t_d = &cplb.switch_d;
process = 1;
} else
process = 0;
break;
default:
process = 0;
break;
}
if (!process)
continue;
if (cplb_data[i].attr & I_CPLB)
__fill_code_cplbtab(t_i, i, a_start, a_end);
if (cplb_data[i].attr & D_CPLB)
__fill_data_cplbtab(t_d, i, a_start, a_end);
}
}
/* close tables */
close_cplbtab(&cplb.init_i);
close_cplbtab(&cplb.init_d);
cplb.init_i.tab[cplb.init_i.pos] = -1;
cplb.init_d.tab[cplb.init_d.pos] = -1;
cplb.switch_i.tab[cplb.switch_i.pos] = -1;
cplb.switch_d.tab[cplb.switch_d.pos] = -1;
}
#endif

13
arch/blackfin/kernel/dma-mapping.c
View File

@ -34,8 +34,8 @@
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <asm/cacheflush.h>
#include <asm/io.h>
#include <asm/bfin-global.h>
static spinlock_t dma_page_lock;
@ -159,10 +159,13 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
BUG_ON(direction == DMA_NONE);
for (i = 0; i < nents; i++)
invalidate_dcache_range(sg_dma_address(&sg[i]),
sg_dma_address(&sg[i]) +
sg_dma_len(&sg[i]));
for (i = 0; i < nents; i++, sg++) {
sg->dma_address = page_address(sg->page) + sg->offset;
invalidate_dcache_range(sg_dma_address(sg),
sg_dma_address(sg) +
sg_dma_len(sg));
}
return nents;
}

4
arch/blackfin/kernel/dualcore_test.c
View File

@ -35,14 +35,14 @@ static int *testarg = (int*)0xfeb00000;
static int test_init(void)
{
*testarg = 1;
printk("Dual core test module inserted: set testarg = [%d]\n @ [%p]\n",
printk(KERN_INFO "Dual core test module inserted: set testarg = [%d]\n @ [%p]\n",
*testarg, testarg);
return 0;
}
static void test_exit(void)
{
printk("Dual core test module removed: testarg = [%d]\n", *testarg);
printk(KERN_INFO "Dual core test module removed: testarg = [%d]\n", *testarg);
}
module_init(test_init);

132
arch/blackfin/kernel/fixed_code.S Normal file
View File

@ -0,0 +1,132 @@
/*
* This file contains sequences of code that will be copied to a
* fixed location, defined in <asm/atomic_seq.h>. The interrupt
* handlers ensure that these sequences appear to be atomic when
* executed from userspace.
* These are aligned to 16 bytes, so that we have some space to replace
* these sequences with something else (e.g. kernel traps if we ever do
* BF561 SMP).
*/
#include <linux/linkage.h>
#include <linux/unistd.h>
#include <asm/entry.h>
.text
ENTRY(_fixed_code_start)
.align 16
ENTRY(_sigreturn_stub)
P0 = __NR_rt_sigreturn;
EXCPT 0;
/* Speculative execution paranoia. */
0: JUMP.S 0b;
ENDPROC (_sigreturn_stub)
.align 16
/*
* Atomic swap, 8 bit.
* Inputs: P0: memory address to use
* R1: value to store
* Output: R0: old contents of the memory address, zero extended.
*/
ENTRY(_atomic_xchg32)
R0 = [P0];
[P0] = R1;
rts;
ENDPROC (_atomic_xchg32)
.align 16
/*
* Compare and swap, 32 bit.
* Inputs: P0: memory address to use
* R1: compare value
* R2: new value to store
* The new value is stored if the contents of the memory
* address is equal to the compare value.
* Output: R0: old contents of the memory address.
*/
ENTRY(_atomic_cas32)
R0 = [P0];
CC = R0 == R1;
IF !CC JUMP 1f;
[P0] = R2;
1:
rts;
ENDPROC (_atomic_cas32)
.align 16
/*
* Atomic add, 32 bit.
* Inputs: P0: memory address to use
* R0: value to add
* Outputs: R0: new contents of the memory address.
* R1: previous contents of the memory address.
*/
ENTRY(_atomic_add32)
R1 = [P0];
R0 = R1 + R0;
[P0] = R0;
rts;
ENDPROC (_atomic_add32)
.align 16
/*
* Atomic sub, 32 bit.
* Inputs: P0: memory address to use
* R0: value to subtract
* Outputs: R0: new contents of the memory address.
* R1: previous contents of the memory address.
*/
ENTRY(_atomic_sub32)
R1 = [P0];
R0 = R1 - R0;
[P0] = R0;
rts;
ENDPROC (_atomic_sub32)
.align 16
/*
* Atomic ior, 32 bit.
* Inputs: P0: memory address to use
* R0: value to ior
* Outputs: R0: new contents of the memory address.
* R1: previous contents of the memory address.
*/
ENTRY(_atomic_ior32)
R1 = [P0];
R0 = R1 | R0;
[P0] = R0;
rts;
ENDPROC (_atomic_ior32)
.align 16
/*
* Atomic ior, 32 bit.
* Inputs: P0: memory address to use
* R0: value to ior
* Outputs: R0: new contents of the memory address.
* R1: previous contents of the memory address.
*/
ENTRY(_atomic_and32)
R1 = [P0];
R0 = R1 & R0;
[P0] = R0;
rts;
ENDPROC (_atomic_ior32)
.align 16
/*
* Atomic ior, 32 bit.
* Inputs: P0: memory address to use
* R0: value to ior
* Outputs: R0: new contents of the memory address.
* R1: previous contents of the memory address.
*/
ENTRY(_atomic_xor32)
R1 = [P0];
R0 = R1 ^ R0;
[P0] = R0;
rts;
ENDPROC (_atomic_ior32)
ENTRY(_fixed_code_end)

7
arch/blackfin/kernel/flat.c
View File

@ -50,9 +50,7 @@ unsigned long bfin_get_addr_from_rp(unsigned long *ptr,
break;
default:
pr_debug("BINFMT_FLAT: Unknown relocation type %x\n",
type);
pr_debug("BINFMT_FLAT: Unknown relocation type %x\n", type);
return 0;
}
@ -83,8 +81,7 @@ void bfin_put_addr_at_rp(unsigned long *ptr, unsigned long addr,
switch (type) {
case FLAT_BFIN_RELOC_TYPE_16_BIT:
put_unaligned(addr, usptr);
pr_debug("new value %x at %p", get_unaligned(usptr),
usptr);
pr_debug("new value %x at %p", get_unaligned(usptr), usptr);
break;
case FLAT_BFIN_RELOC_TYPE_16H_BIT:

421
arch/blackfin/kernel/kgdb.c Normal file
View File

@ -0,0 +1,421 @@
/*
* File: arch/blackfin/kernel/kgdb.c
* Based on:
* Author: Sonic Zhang
*
* Created:
* Description:
*
* Rev: $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $
*
* Modified:
* Copyright 2005-2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/ptrace.h> /* for linux pt_regs struct */
#include <linux/kgdb.h>
#include <linux/console.h>
#include <linux/init.h>
#include <linux/debugger.h>
#include <linux/errno.h>
#include <linux/irq.h>
#include <asm/system.h>
#include <asm/traps.h>
#include <asm/blackfin.h>
/* Put the error code here just in case the user cares. */
int gdb_bf533errcode;
/* Likewise, the vector number here (since GDB only gets the signal
number through the usual means, and that's not very specific). */
int gdb_bf533vector = -1;
#if KGDB_MAX_NO_CPUS != 8
#error change the definition of slavecpulocks
#endif
void regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
{
gdb_regs[BFIN_R0] = regs->r0;
gdb_regs[BFIN_R1] = regs->r1;
gdb_regs[BFIN_R2] = regs->r2;
gdb_regs[BFIN_R3] = regs->r3;
gdb_regs[BFIN_R4] = regs->r4;
gdb_regs[BFIN_R5] = regs->r5;
gdb_regs[BFIN_R6] = regs->r6;
gdb_regs[BFIN_R7] = regs->r7;
gdb_regs[BFIN_P0] = regs->p0;
gdb_regs[BFIN_P1] = regs->p1;
gdb_regs[BFIN_P2] = regs->p2;
gdb_regs[BFIN_P3] = regs->p3;
gdb_regs[BFIN_P4] = regs->p4;
gdb_regs[BFIN_P5] = regs->p5;
gdb_regs[BFIN_SP] = regs->reserved;
gdb_regs[BFIN_FP] = regs->fp;
gdb_regs[BFIN_I0] = regs->i0;
gdb_regs[BFIN_I1] = regs->i1;
gdb_regs[BFIN_I2] = regs->i2;
gdb_regs[BFIN_I3] = regs->i3;
gdb_regs[BFIN_M0] = regs->m0;
gdb_regs[BFIN_M1] = regs->m1;
gdb_regs[BFIN_M2] = regs->m2;
gdb_regs[BFIN_M3] = regs->m3;
gdb_regs[BFIN_B0] = regs->b0;
gdb_regs[BFIN_B1] = regs->b1;
gdb_regs[BFIN_B2] = regs->b2;
gdb_regs[BFIN_B3] = regs->b3;
gdb_regs[BFIN_L0] = regs->l0;
gdb_regs[BFIN_L1] = regs->l1;
gdb_regs[BFIN_L2] = regs->l2;
gdb_regs[BFIN_L3] = regs->l3;
gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
gdb_regs[BFIN_ASTAT] = regs->astat;
gdb_regs[BFIN_RETS] = regs->rets;
gdb_regs[BFIN_LC0] = regs->lc0;
gdb_regs[BFIN_LT0] = regs->lt0;
gdb_regs[BFIN_LB0] = regs->lb0;
gdb_regs[BFIN_LC1] = regs->lc1;
gdb_regs[BFIN_LT1] = regs->lt1;
gdb_regs[BFIN_LB1] = regs->lb1;
gdb_regs[BFIN_CYCLES] = 0;
gdb_regs[BFIN_CYCLES2] = 0;
gdb_regs[BFIN_USP] = regs->usp;
gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
gdb_regs[BFIN_SYSCFG] = regs->syscfg;
gdb_regs[BFIN_RETI] = regs->pc;
gdb_regs[BFIN_RETX] = regs->retx;
gdb_regs[BFIN_RETN] = regs->retn;
gdb_regs[BFIN_RETE] = regs->rete;
gdb_regs[BFIN_PC] = regs->pc;
gdb_regs[BFIN_CC] = 0;
gdb_regs[BFIN_EXTRA1] = 0;
gdb_regs[BFIN_EXTRA2] = 0;
gdb_regs[BFIN_EXTRA3] = 0;
gdb_regs[BFIN_IPEND] = regs->ipend;
}
/*
* Extracts ebp, esp and eip values understandable by gdb from the values
* saved by switch_to.
* thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
* prior to entering switch_to is 8 greater then the value that is saved.
* If switch_to changes, change following code appropriately.
*/
void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
{
gdb_regs[BFIN_SP] = p->thread.ksp;
gdb_regs[BFIN_PC] = p->thread.pc;
gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
}
void gdb_regs_to_regs(unsigned long *gdb_regs, struct pt_regs *regs)
{
regs->r0 = gdb_regs[BFIN_R0];
regs->r1 = gdb_regs[BFIN_R1];
regs->r2 = gdb_regs[BFIN_R2];
regs->r3 = gdb_regs[BFIN_R3];
regs->r4 = gdb_regs[BFIN_R4];
regs->r5 = gdb_regs[BFIN_R5];
regs->r6 = gdb_regs[BFIN_R6];
regs->r7 = gdb_regs[BFIN_R7];
regs->p0 = gdb_regs[BFIN_P0];
regs->p1 = gdb_regs[BFIN_P1];
regs->p2 = gdb_regs[BFIN_P2];
regs->p3 = gdb_regs[BFIN_P3];
regs->p4 = gdb_regs[BFIN_P4];
regs->p5 = gdb_regs[BFIN_P5];
regs->fp = gdb_regs[BFIN_FP];
regs->i0 = gdb_regs[BFIN_I0];
regs->i1 = gdb_regs[BFIN_I1];
regs->i2 = gdb_regs[BFIN_I2];
regs->i3 = gdb_regs[BFIN_I3];
regs->m0 = gdb_regs[BFIN_M0];
regs->m1 = gdb_regs[BFIN_M1];
regs->m2 = gdb_regs[BFIN_M2];
regs->m3 = gdb_regs[BFIN_M3];
regs->b0 = gdb_regs[BFIN_B0];
regs->b1 = gdb_regs[BFIN_B1];
regs->b2 = gdb_regs[BFIN_B2];
regs->b3 = gdb_regs[BFIN_B3];
regs->l0 = gdb_regs[BFIN_L0];
regs->l1 = gdb_regs[BFIN_L1];
regs->l2 = gdb_regs[BFIN_L2];
regs->l3 = gdb_regs[BFIN_L3];
regs->a0x = gdb_regs[BFIN_A0_DOT_X];
regs->a0w = gdb_regs[BFIN_A0_DOT_W];
regs->a1x = gdb_regs[BFIN_A1_DOT_X];
regs->a1w = gdb_regs[BFIN_A1_DOT_W];
regs->rets = gdb_regs[BFIN_RETS];
regs->lc0 = gdb_regs[BFIN_LC0];
regs->lt0 = gdb_regs[BFIN_LT0];
regs->lb0 = gdb_regs[BFIN_LB0];
regs->lc1 = gdb_regs[BFIN_LC1];
regs->lt1 = gdb_regs[BFIN_LT1];
regs->lb1 = gdb_regs[BFIN_LB1];
regs->usp = gdb_regs[BFIN_USP];
regs->syscfg = gdb_regs[BFIN_SYSCFG];
regs->retx = gdb_regs[BFIN_PC];
regs->retn = gdb_regs[BFIN_RETN];
regs->rete = gdb_regs[BFIN_RETE];
regs->pc = gdb_regs[BFIN_PC];
#if 0 /* can't change these */
regs->astat = gdb_regs[BFIN_ASTAT];
regs->seqstat = gdb_regs[BFIN_SEQSTAT];
regs->ipend = gdb_regs[BFIN_IPEND];
#endif
}
struct hw_breakpoint {
unsigned int occupied:1;
unsigned int skip:1;
unsigned int enabled:1;
unsigned int type:1;
unsigned int dataacc:2;
unsigned short count;
unsigned int addr;
} breakinfo[HW_BREAKPOINT_NUM];
int kgdb_arch_init(void)
{
kgdb_remove_all_hw_break();
return 0;
}
int kgdb_set_hw_break(unsigned long addr)
{
int breakno;
for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++)
if (!breakinfo[breakno].occupied) {
breakinfo[breakno].occupied = 1;
breakinfo[breakno].enabled = 1;
breakinfo[breakno].type = 1;
breakinfo[breakno].addr = addr;
return 0;
}
return -ENOSPC;
}
int kgdb_remove_hw_break(unsigned long addr)
{
int breakno;
for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++)
if (breakinfo[breakno].addr == addr)
memset(&(breakinfo[breakno]), 0, sizeof(struct hw_breakpoint));
return 0;
}
void kgdb_remove_all_hw_break(void)
{
memset(breakinfo, 0, sizeof(struct hw_breakpoint)*8);
}
/*
void kgdb_show_info(void)
{
printk(KERN_DEBUG "hwd: wpia0=0x%x, wpiacnt0=%d, wpiactl=0x%x, wpstat=0x%x\n",
bfin_read_WPIA0(), bfin_read_WPIACNT0(),
bfin_read_WPIACTL(), bfin_read_WPSTAT());
}
*/
void kgdb_correct_hw_break(void)
{
int breakno;
int correctit;
uint32_t wpdactl = bfin_read_WPDACTL();
correctit = 0;
for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++) {
if (breakinfo[breakno].type == 1) {
switch (breakno) {
case 0:
if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN0)) {
correctit = 1;
wpdactl &= ~(WPIREN01|EMUSW0);
wpdactl |= WPIAEN0|WPICNTEN0;
bfin_write_WPIA0(breakinfo[breakno].addr);
bfin_write_WPIACNT0(breakinfo[breakno].skip);
} else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN0)) {
correctit = 1;
wpdactl &= ~WPIAEN0;
}
break;
case 1:
if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN1)) {
correctit = 1;
wpdactl &= ~(WPIREN01|EMUSW1);
wpdactl |= WPIAEN1|WPICNTEN1;
bfin_write_WPIA1(breakinfo[breakno].addr);
bfin_write_WPIACNT1(breakinfo[breakno].skip);
} else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN1)) {
correctit = 1;
wpdactl &= ~WPIAEN1;
}
break;
case 2:
if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN2)) {
correctit = 1;
wpdactl &= ~(WPIREN23|EMUSW2);
wpdactl |= WPIAEN2|WPICNTEN2;
bfin_write_WPIA2(breakinfo[breakno].addr);
bfin_write_WPIACNT2(breakinfo[breakno].skip);
} else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN2)) {
correctit = 1;
wpdactl &= ~WPIAEN2;
}
break;
case 3:
if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN3)) {
correctit = 1;
wpdactl &= ~(WPIREN23|EMUSW3);
wpdactl |= WPIAEN3|WPICNTEN3;
bfin_write_WPIA3(breakinfo[breakno].addr);
bfin_write_WPIACNT3(breakinfo[breakno].skip);
} else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN3)) {
correctit = 1;
wpdactl &= ~WPIAEN3;
}
break;
case 4:
if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN4)) {
correctit = 1;
wpdactl &= ~(WPIREN45|EMUSW4);
wpdactl |= WPIAEN4|WPICNTEN4;
bfin_write_WPIA4(breakinfo[breakno].addr);
bfin_write_WPIACNT4(breakinfo[breakno].skip);
} else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN4)) {
correctit = 1;
wpdactl &= ~WPIAEN4;
}
break;
case 5:
if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN5)) {
correctit = 1;
wpdactl &= ~(WPIREN45|EMUSW5);
wpdactl |= WPIAEN5|WPICNTEN5;
bfin_write_WPIA5(breakinfo[breakno].addr);
bfin_write_WPIACNT5(breakinfo[breakno].skip);
} else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN5)) {
correctit = 1;
wpdactl &= ~WPIAEN5;
}
break;
}
}
}
if (correctit) {
wpdactl &= ~WPAND;
wpdactl |= WPPWR;
/*printk("correct_hw_break: wpdactl=0x%x\n", wpdactl);*/
bfin_write_WPDACTL(wpdactl);
CSYNC();
/*kgdb_show_info();*/
}
}
void kgdb_disable_hw_debug(struct pt_regs *regs)
{
/* Disable hardware debugging while we are in kgdb */
bfin_write_WPIACTL(bfin_read_WPIACTL() & ~0x1);
CSYNC();
}
void kgdb_post_master_code(struct pt_regs *regs, int eVector, int err_code)
{
/* Master processor is completely in the debugger */
gdb_bf533vector = eVector;
gdb_bf533errcode = err_code;
}
int kgdb_arch_handle_exception(int exceptionVector, int signo,
int err_code, char *remcom_in_buffer,
char *remcom_out_buffer,
struct pt_regs *linux_regs)
{
long addr;
long breakno;
char *ptr;
int newPC;
int wp_status;
switch (remcom_in_buffer[0]) {
case 'c':
case 's':
if (kgdb_contthread && kgdb_contthread != current) {
strcpy(remcom_out_buffer, "E00");
break;
}
kgdb_contthread = NULL;
/* try to read optional parameter, pc unchanged if no parm */
ptr = &remcom_in_buffer[1];
if (kgdb_hex2long(&ptr, &addr)) {
linux_regs->retx = addr;
}
newPC = linux_regs->retx;
/* clear the trace bit */
linux_regs->syscfg &= 0xfffffffe;
/* set the trace bit if we're stepping */
if (remcom_in_buffer[0] == 's') {
linux_regs->syscfg |= 0x1;
debugger_step = 1;
}
wp_status = bfin_read_WPSTAT();
CSYNC();
if (exceptionVector == VEC_WATCH) {
for (breakno = 0; breakno < 6; ++breakno) {
if (wp_status & (1 << breakno)) {
breakinfo->skip = 1;
break;
}
}
}
kgdb_correct_hw_break();
bfin_write_WPSTAT(0);
return 0;
} /* switch */
return -1; /* this means that we do not want to exit from the handler */
}
struct kgdb_arch arch_kgdb_ops = {
.gdb_bpt_instr = {0xa1},
.flags = KGDB_HW_BREAKPOINT,
};

71
arch/blackfin/kernel/process.c
View File

@ -32,9 +32,10 @@
#include <linux/unistd.h>
#include <linux/user.h>
#include <linux/a.out.h>
#include <linux/uaccess.h>
#include <asm/blackfin.h>
#include <asm/uaccess.h>
#include <asm/fixed_code.h>
#define LED_ON 0
#define LED_OFF 1
@ -173,8 +174,8 @@ void show_regs(struct pt_regs *regs)
printk(KERN_NOTICE "R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
regs->r4, regs->r5, regs->r6, regs->r7);
if (!(regs->ipend))
printk("USP: %08lx\n", rdusp());
if (!regs->ipend)
printk(KERN_NOTICE "USP: %08lx\n", rdusp());
}
/* Fill in the fpu structure for a core dump. */
@ -350,6 +351,70 @@ unsigned long get_wchan(struct task_struct *p)
return 0;
}
void finish_atomic_sections (struct pt_regs *regs)
{
if (regs->pc < ATOMIC_SEQS_START || regs->pc >= ATOMIC_SEQS_END)
return;
switch (regs->pc) {
case ATOMIC_XCHG32 + 2:
put_user(regs->r1, (int *)regs->p0);
regs->pc += 2;
break;
case ATOMIC_CAS32 + 2:
case ATOMIC_CAS32 + 4:
if (regs->r0 == regs->r1)
put_user(regs->r2, (int *)regs->p0);
regs->pc = ATOMIC_CAS32 + 8;
break;
case ATOMIC_CAS32 + 6:
put_user(regs->r2, (int *)regs->p0);
regs->pc += 2;
break;
case ATOMIC_ADD32 + 2:
regs->r0 = regs->r1 + regs->r0;
/* fall through */
case ATOMIC_ADD32 + 4:
put_user(regs->r0, (int *)regs->p0);
regs->pc = ATOMIC_ADD32 + 6;
break;
case ATOMIC_SUB32 + 2:
regs->r0 = regs->r1 - regs->r0;
/* fall through */
case ATOMIC_SUB32 + 4:
put_user(regs->r0, (int *)regs->p0);
regs->pc = ATOMIC_SUB32 + 6;
break;
case ATOMIC_IOR32 + 2:
regs->r0 = regs->r1 | regs->r0;
/* fall through */
case ATOMIC_IOR32 + 4:
put_user(regs->r0, (int *)regs->p0);
regs->pc = ATOMIC_IOR32 + 6;
break;
case ATOMIC_AND32 + 2:
regs->r0 = regs->r1 & regs->r0;
/* fall through */
case ATOMIC_AND32 + 4:
put_user(regs->r0, (int *)regs->p0);
regs->pc = ATOMIC_AND32 + 6;
break;
case ATOMIC_XOR32 + 2:
regs->r0 = regs->r1 ^ regs->r0;
/* fall through */
case ATOMIC_XOR32 + 4:
put_user(regs->r0, (int *)regs->p0);
regs->pc = ATOMIC_XOR32 + 6;
break;
}
}
#if defined(CONFIG_ACCESS_CHECK)
int _access_ok(unsigned long addr, unsigned long size)
{

2
arch/blackfin/kernel/ptrace.c
View File

@ -36,8 +36,8 @@
#include <linux/ptrace.h>
#include <linux/user.h>
#include <linux/signal.h>
#include <linux/uaccess.h>
#include <asm/uaccess.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>

326
arch/blackfin/kernel/setup.c
View File

@ -42,6 +42,7 @@
#include <asm/cacheflush.h>
#include <asm/blackfin.h>
#include <asm/cplbinit.h>
#include <asm/fixed_code.h>
u16 _bfin_swrst;
@ -63,10 +64,6 @@ EXPORT_SYMBOL(mtd_size);
char __initdata command_line[COMMAND_LINE_SIZE];
#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
static void generate_cpl_tables(void);
#endif
void __init bf53x_cache_init(void)
{
#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
@ -197,6 +194,17 @@ void __init setup_arch(char **cmdline_p)
/* this give a chance to get printk() working before crash. */
#endif
printk(KERN_INFO "Hardware Trace ");
if (bfin_read_TBUFCTL() & 0x1 )
printk("Active ");
else
printk("Off ");
if (bfin_read_TBUFCTL() & 0x2)
printk("and Enabled\n");
else
printk("and Disabled\n");
#if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
/* we need to initialize the Flashrom device here since we might
* do things with flash early on in the boot
@ -388,11 +396,11 @@ void __init setup_arch(char **cmdline_p)
/* check the size of the l1 area */
l1_length = _etext_l1 - _stext_l1;
if (l1_length > L1_CODE_LENGTH)
panic("L1 memory overflow\n");
panic("L1 code memory overflow\n");
l1_length = _ebss_l1 - _sdata_l1;
if (l1_length > L1_DATA_A_LENGTH)
panic("L1 memory overflow\n");
panic("L1 data memory overflow\n");
#ifdef BF561_FAMILY
_bfin_swrst = bfin_read_SICA_SWRST();
@ -400,10 +408,28 @@ void __init setup_arch(char **cmdline_p)
_bfin_swrst = bfin_read_SWRST();
#endif
bf53x_cache_init();
/* Copy atomic sequences to their fixed location, and sanity check that
these locations are the ones that we advertise to userspace. */
memcpy((void *)FIXED_CODE_START, &fixed_code_start,
FIXED_CODE_END - FIXED_CODE_START);
BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
!= SIGRETURN_STUB - FIXED_CODE_START);
BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
!= ATOMIC_XCHG32 - FIXED_CODE_START);
BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
!= ATOMIC_CAS32 - FIXED_CODE_START);
BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
!= ATOMIC_ADD32 - FIXED_CODE_START);
BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
!= ATOMIC_SUB32 - FIXED_CODE_START);
BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
!= ATOMIC_IOR32 - FIXED_CODE_START);
BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
!= ATOMIC_AND32 - FIXED_CODE_START);
BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
!= ATOMIC_XOR32 - FIXED_CODE_START);
printk(KERN_INFO "Hardware Trace Enabled\n");
bfin_write_TBUFCTL(0x03);
bf53x_cache_init();
}
static int __init topology_init(void)
@ -421,286 +447,6 @@ static int __init topology_init(void)
subsys_initcall(topology_init);
#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
static u16 __init lock_kernel_check(u32 start, u32 end)
{
if ((start <= (u32) _stext && end >= (u32) _end)
|| (start >= (u32) _stext && end <= (u32) _end))
return IN_KERNEL;
return 0;
}
static unsigned short __init
fill_cplbtab(struct cplb_tab *table,
unsigned long start, unsigned long end,
unsigned long block_size, unsigned long cplb_data)
{
int i;
switch (block_size) {
case SIZE_4M:
i = 3;
break;
case SIZE_1M:
i = 2;
break;
case SIZE_4K:
i = 1;
break;
case SIZE_1K:
default:
i = 0;
break;
}
cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
while ((start < end) && (table->pos < table->size)) {
table->tab[table->pos++] = start;
if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
table->tab[table->pos++] =
cplb_data | CPLB_LOCK | CPLB_DIRTY;
else
table->tab[table->pos++] = cplb_data;
start += block_size;
}
return 0;
}
static unsigned short __init
close_cplbtab(struct cplb_tab *table)
{
while (table->pos < table->size) {
table->tab[table->pos++] = 0;
table->tab[table->pos++] = 0; /* !CPLB_VALID */
}
return 0;
}
/* helper function */
static void __fill_code_cplbtab(struct cplb_tab *t, int i,
u32 a_start, u32 a_end)
{
if (cplb_data[i].psize) {
fill_cplbtab(t,
cplb_data[i].start,
cplb_data[i].end,
cplb_data[i].psize,
cplb_data[i].i_conf);
} else {
#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
if (i == SDRAM_KERN) {
fill_cplbtab(t,
cplb_data[i].start,
cplb_data[i].end,
SIZE_4M,
cplb_data[i].i_conf);
} else {
#endif
fill_cplbtab(t,
cplb_data[i].start,
a_start,
SIZE_1M,
cplb_data[i].i_conf);
fill_cplbtab(t,
a_start,
a_end,
SIZE_4M,
cplb_data[i].i_conf);
fill_cplbtab(t, a_end,
cplb_data[i].end,
SIZE_1M,
cplb_data[i].i_conf);
}
}
}
static void __fill_data_cplbtab(struct cplb_tab *t, int i,
u32 a_start, u32 a_end)
{
if (cplb_data[i].psize) {
fill_cplbtab(t,
cplb_data[i].start,
cplb_data[i].end,
cplb_data[i].psize,
cplb_data[i].d_conf);
} else {
fill_cplbtab(t,
cplb_data[i].start,
a_start, SIZE_1M,
cplb_data[i].d_conf);
fill_cplbtab(t, a_start,
a_end, SIZE_4M,
cplb_data[i].d_conf);
fill_cplbtab(t, a_end,
cplb_data[i].end,
SIZE_1M,
cplb_data[i].d_conf);
}
}
static void __init generate_cpl_tables(void)
{
u16 i, j, process;
u32 a_start, a_end, as, ae, as_1m;
struct cplb_tab *t_i = NULL;
struct cplb_tab *t_d = NULL;
struct s_cplb cplb;
cplb.init_i.size = MAX_CPLBS;
cplb.init_d.size = MAX_CPLBS;
cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
cplb.init_i.pos = 0;
cplb.init_d.pos = 0;
cplb.switch_i.pos = 0;
cplb.switch_d.pos = 0;
cplb.init_i.tab = icplb_table;
cplb.init_d.tab = dcplb_table;
cplb.switch_i.tab = ipdt_table;
cplb.switch_d.tab = dpdt_table;
cplb_data[SDRAM_KERN].end = memory_end;
#ifdef CONFIG_MTD_UCLINUX
cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
# if defined(CONFIG_ROMFS_FS)
cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
/*
* The ROMFS_FS size is often not multiple of 1MB.
* This can cause multiple CPLB sets covering the same memory area.
* This will then cause multiple CPLB hit exceptions.
* Workaround: We ensure a contiguous memory area by extending the kernel
* memory section over the mtd section.
* For ROMFS_FS memory must be covered with ICPLBs anyways.
* So there is no difference between kernel and mtd memory setup.
*/
cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
cplb_data[SDRAM_RAM_MTD].valid = 0;
# endif
#else
cplb_data[SDRAM_RAM_MTD].valid = 0;
#endif
cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
cplb_data[SDRAM_DMAZ].end = _ramend;
cplb_data[RES_MEM].start = _ramend;
cplb_data[RES_MEM].end = physical_mem_end;
if (reserved_mem_dcache_on)
cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
else
cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
if (reserved_mem_icache_on)
cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
else
cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
for (i = ZERO_P; i <= L2_MEM; i++) {
if (!cplb_data[i].valid)
continue;
as_1m = cplb_data[i].start % SIZE_1M;
/*
* We need to make sure all sections are properly 1M aligned
* However between Kernel Memory and the Kernel mtd section,
* depending on the rootfs size, there can be overlapping
* memory areas.
*/
if (as_1m && i != L1I_MEM && i != L1D_MEM) {
#ifdef CONFIG_MTD_UCLINUX
if (i == SDRAM_RAM_MTD) {
if ((cplb_data[SDRAM_KERN].end + 1) >
cplb_data[SDRAM_RAM_MTD].start)
cplb_data[SDRAM_RAM_MTD].start =
(cplb_data[i].start &
(-2*SIZE_1M)) + SIZE_1M;
else
cplb_data[SDRAM_RAM_MTD].start =
(cplb_data[i].start &
(-2*SIZE_1M));
} else
#endif
printk(KERN_WARNING
"Unaligned Start of %s at 0x%X\n",
cplb_data[i].name, cplb_data[i].start);
}
as = cplb_data[i].start % SIZE_4M;
ae = cplb_data[i].end % SIZE_4M;
if (as)
a_start = cplb_data[i].start + (SIZE_4M - (as));
else
a_start = cplb_data[i].start;
a_end = cplb_data[i].end - ae;
for (j = INITIAL_T; j <= SWITCH_T; j++) {
switch (j) {
case INITIAL_T:
if (cplb_data[i].attr & INITIAL_T) {
t_i = &cplb.init_i;
t_d = &cplb.init_d;
process = 1;
} else
process = 0;
break;
case SWITCH_T:
if (cplb_data[i].attr & SWITCH_T) {
t_i = &cplb.switch_i;
t_d = &cplb.switch_d;
process = 1;
} else
process = 0;
break;
default:
process = 0;
break;
}
if (!process)
continue;
if (cplb_data[i].attr & I_CPLB)
__fill_code_cplbtab(t_i, i, a_start, a_end);
if (cplb_data[i].attr & D_CPLB)
__fill_data_cplbtab(t_d, i, a_start, a_end);
}
}
/* close tables */
close_cplbtab(&cplb.init_i);
close_cplbtab(&cplb.init_d);
cplb.init_i.tab[cplb.init_i.pos] = -1;
cplb.init_d.tab[cplb.init_d.pos] = -1;
cplb.switch_i.tab[cplb.switch_i.pos] = -1;
cplb.switch_d.tab[cplb.switch_d.pos] = -1;
}
#endif
static u_long get_vco(void)
{
u_long msel;
@ -730,7 +476,6 @@ u_long get_cclk(void)
return get_vco() / ssel;
return get_vco() >> csel;
}
EXPORT_SYMBOL(get_cclk);
/* Get the System clock */
@ -749,7 +494,6 @@ u_long get_sclk(void)
return get_vco() / ssel;
}
EXPORT_SYMBOL(get_sclk);
/*

2
arch/blackfin/kernel/signal.c
View File

@ -34,8 +34,8 @@
#include <linux/personality.h>
#include <linux/binfmts.h>
#include <linux/freezer.h>
#include <linux/uaccess.h>
#include <asm/uaccess.h>
#include <asm/cacheflush.h>
#include <asm/ucontext.h>

6
arch/blackfin/kernel/sys_bfin.c
View File

@ -37,12 +37,12 @@
#include <linux/syscalls.h>
#include <linux/mman.h>
#include <linux/file.h>
#include <linux/uaccess.h>
#include <linux/ipc.h>
#include <linux/unistd.h>
#include <asm/cacheflush.h>
#include <asm/uaccess.h>
#include <asm/ipc.h>
#include <asm/dma.h>
#include <asm/unistd.h>
/*
* sys_pipe() is the normal C calling standard for creating

4
arch/blackfin/kernel/time.c
View File

@ -87,7 +87,7 @@ void __init init_leds(void)
static inline void do_leds(void)
{
static unsigned int count = 50;
static int flag = 0;
static int flag;
unsigned short tmp = 0;
if (--count == 0) {
@ -200,7 +200,7 @@ irqreturn_t timer_interrupt(int irq, void *dummy)__attribute__((l1_text));
irqreturn_t timer_interrupt(int irq, void *dummy)
{
/* last time the cmos clock got updated */
static long last_rtc_update = 0;
static long last_rtc_update;
write_seqlock(&xtime_lock);

30
arch/blackfin/kernel/traps.c
View File

@ -27,15 +27,15 @@
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <asm/uaccess.h>
#include <asm/traps.h>
#include <asm/cacheflush.h>
#include <asm/blackfin.h>
#include <asm/uaccess.h>
#include <asm/irq_handler.h>
#include <linux/uaccess.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/kallsyms.h>
#include <asm/traps.h>
#include <asm/cacheflush.h>
#include <asm/blackfin.h>
#include <asm/irq_handler.h>
#include <asm/trace.h>
#ifdef CONFIG_KGDB
# include <linux/debugger.h>
@ -131,16 +131,6 @@ static int printk_address(unsigned long address)
return printk("[<0x%p>]", (void *)address);
}
#define trace_buffer_save(x) \
do { \
(x) = bfin_read_TBUFCTL(); \
bfin_write_TBUFCTL((x) & ~TBUFEN); \
} while (0)
#define trace_buffer_restore(x) \
do { \
bfin_write_TBUFCTL((x)); \
} while (0)
asmlinkage void trap_c(struct pt_regs *fp)
{
int j, sig = 0;
@ -203,15 +193,14 @@ asmlinkage void trap_c(struct pt_regs *fp)
#else
/* 0x02 - User Defined, Caught by default */
#endif
/* 0x03 - Atomic test and set */
/* 0x03 - User Defined, userspace stack overflow */
case VEC_EXCPT03:
info.si_code = SEGV_STACKFLOW;
sig = SIGSEGV;
printk(KERN_EMERG EXC_0x03);
CHK_DEBUGGER_TRAP();
break;
/* 0x04 - spinlock - handled by _ex_spinlock,
getting here is an error */
/* 0x04 - User Defined, Caught by default */
/* 0x05 - User Defined, Caught by default */
/* 0x06 - User Defined, Caught by default */
/* 0x07 - User Defined, Caught by default */
@ -567,8 +556,7 @@ void dump_bfin_regs(struct pt_regs *fp, void *retaddr)
) {
int i = ((unsigned int)retaddr & 0xFFFFFFF0) - 32;
unsigned short x = 0;
for (; i < ((unsigned int)retaddr & 0xFFFFFFF0 ) + 32 ;
i += 2) {
for (; i < ((unsigned int)retaddr & 0xFFFFFFF0) + 32; i += 2) {
if (!(i & 0xF))
printk(KERN_EMERG "\n" KERN_EMERG
"0x%08x: ", i);

12
arch/blackfin/kernel/vmlinux.lds.S
View File

@ -31,6 +31,7 @@
#include <asm-generic/vmlinux.lds.h>
#include <asm/mem_map.h>
#include <asm/page.h>
OUTPUT_FORMAT("elf32-bfin")
ENTRY(__start)
@ -63,8 +64,8 @@ SECTIONS
.data :
{
. = ALIGN(PAGE_SIZE);
__sdata = .;
. = ALIGN(0x2000);
*(.data.init_task)
DATA_DATA
CONSTRUCTORS
@ -72,14 +73,14 @@ SECTIONS
. = ALIGN(32);
*(.data.cacheline_aligned)
. = ALIGN(0x2000);
. = ALIGN(PAGE_SIZE);
__edata = .;
}
. = ALIGN(PAGE_SIZE);
___init_begin = .;
.init :
{
. = ALIGN(4096);
__sinittext = .;
*(.init.text)
__einittext = .;
@ -152,9 +153,10 @@ SECTIONS
__ebss_b_l1 = .;
}
___init_end = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1);
. = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1);
___init_end = ALIGN(PAGE_SIZE);
.bss LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1) :
.bss ___init_end :
{
. = ALIGN(4);
___bss_start = .;

1
arch/blackfin/lib/strcmp.c
View File

@ -8,4 +8,3 @@ int strcmp(const char *dest, const char *src)
{
return __inline_strcmp(dest, src);
}

1
arch/blackfin/lib/strcpy.c
View File

@ -8,4 +8,3 @@ char *strcpy(char *dest, const char *src)
{
return __inline_strcpy(dest, src);
}

1
arch/blackfin/lib/strncmp.c
View File

@ -8,4 +8,3 @@ int strncmp(const char *cs, const char *ct, size_t count)
{
return __inline_strncmp(cs, ct, count);
}

1
arch/blackfin/lib/strncpy.c
View File

@ -8,4 +8,3 @@ char *strncpy(char *dest, const char *src, size_t n)
{
return __inline_strncpy(dest, src, n);
}

4
arch/blackfin/mach-bf533/Makefile
View File

@ -4,6 +4,6 @@
extra-y := head.o
obj-y := ints-priority.o
obj-y := ints-priority.o dma.o
obj-$(CONFIG_CPU_FREQ_BF533) += cpu.o
obj-$(CONFIG_CPU_FREQ) += cpu.o

2
arch/blackfin/mach-bf533/boards/cm_bf533.c
View File

@ -34,7 +34,7 @@
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/usb_isp1362.h>
#include <asm/irq.h>
#include <linux/irq.h>
#include <asm/bfin5xx_spi.h>
/*

2
arch/blackfin/mach-bf533/boards/ezkit.c
View File

@ -35,7 +35,7 @@
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/usb_isp1362.h>
#include <asm/irq.h>
#include <linux/irq.h>
#include <asm/bfin5xx_spi.h>
/*

2
arch/blackfin/mach-bf533/boards/generic_board.c
View File

@ -30,7 +30,7 @@
#include <linux/device.h>
#include <linux/platform_device.h>
#include <asm/irq.h>
#include <linux/irq.h>
/*
* Name the Board for the /proc/cpuinfo

2
arch/blackfin/mach-bf533/boards/stamp.c
View File

@ -37,7 +37,7 @@
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
#include <linux/usb_isp1362.h>
#endif
#include <asm/irq.h>
#include <linux/irq.h>
#include <asm/bfin5xx_spi.h>
/*

3
arch/blackfin/mach-bf533/cpu.c
View File

@ -79,8 +79,7 @@ static int bf533_target(struct cpufreq_policy *policy,
int i;
struct cpufreq_freqs freqs;
if (cpufreq_frequency_table_target
(policy, bf533_freq_table, target_freq, relation, &index))
if (cpufreq_frequency_table_target(policy, bf533_freq_table, target_freq, relation, &index))
return -EINVAL;
cclk_mhz = bf533_freq_table[index].frequency;
vco_mhz = bf533_freq_table[index].index;

95
arch/blackfin/mach-bf533/dma.c Normal file
View File

@ -0,0 +1,95 @@
/*
* File: arch/blackfin/mach-bf533/dma.c
* Based on:
* Author:
*
* Created:
* Description: This file contains the simple DMA Implementation for Blackfin
*
* Modified:
* Copyright 2004-2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <asm/blackfin.h>
#include <asm/dma.h>
struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
(struct dma_register *) DMA0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_NEXT_DESC_PTR,
(struct dma_register *) DMA3_NEXT_DESC_PTR,
(struct dma_register *) DMA4_NEXT_DESC_PTR,
(struct dma_register *) DMA5_NEXT_DESC_PTR,
(struct dma_register *) DMA6_NEXT_DESC_PTR,
(struct dma_register *) DMA7_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
};
int channel2irq(unsigned int channel)
{
int ret_irq = -1;
switch (channel) {
case CH_PPI:
ret_irq = IRQ_PPI;
break;
case CH_SPORT0_RX:
ret_irq = IRQ_SPORT0_RX;
break;
case CH_SPORT0_TX:
ret_irq = IRQ_SPORT0_TX;
break;
case CH_SPORT1_RX:
ret_irq = IRQ_SPORT1_RX;
break;
case CH_SPORT1_TX:
ret_irq = IRQ_SPORT1_TX;
break;
case CH_SPI:
ret_irq = IRQ_SPI;
break;
case CH_UART_RX:
ret_irq = IRQ_UART_RX;
break;
case CH_UART_TX:
ret_irq = IRQ_UART_TX;
break;
case CH_MEM_STREAM0_SRC:
case CH_MEM_STREAM0_DEST:
ret_irq = IRQ_MEM_DMA0;
break;
case CH_MEM_STREAM1_SRC:
case CH_MEM_STREAM1_DEST:
ret_irq = IRQ_MEM_DMA1;
break;
}
return ret_irq;
}

5
arch/blackfin/mach-bf533/head.S
View File

@ -30,6 +30,7 @@
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/blackfin.h>
#include <asm/trace.h>
#if CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach/mem_init.h>
#endif
@ -96,6 +97,10 @@ ENTRY(__start)
M2 = r0;
M3 = r0;
trace_buffer_start(p0,r0);
P0 = R1;
R0 = R1;
#if CONFIG_DEBUG_KERNEL_START
/*

2
arch/blackfin/mach-bf533/ints-priority.c
View File

@ -28,8 +28,8 @@
*/
#include <linux/module.h>
#include <linux/irq.h>
#include <asm/blackfin.h>
#include <asm/irq.h>
void program_IAR(void)
{

2
arch/blackfin/mach-bf537/Makefile
View File

@ -4,6 +4,6 @@
extra-y := head.o
obj-y := ints-priority.o
obj-y := ints-priority.o dma.o
obj-$(CONFIG_CPU_FREQ) += cpu.o

2
arch/blackfin/mach-bf537/boards/cm_bf537.c
View File

@ -35,7 +35,7 @@
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/usb_isp1362.h>
#include <asm/irq.h>
#include <linux/irq.h>
#include <asm/bfin5xx_spi.h>
/*

3
arch/blackfin/mach-bf537/boards/eth_mac.c
View File

@ -20,8 +20,7 @@
#include <linux/module.h>
#include <asm/blackfin.h>
#if defined(CONFIG_GENERIC_BOARD) \
|| defined(CONFIG_BFIN537_STAMP)
#if defined(CONFIG_GENERIC_BOARD) || defined(CONFIG_BFIN537_STAMP)
/*
* Currently the MAC address is saved in Flash by U-Boot

4
arch/blackfin/mach-bf537/boards/generic_board.c
View File

@ -35,9 +35,9 @@
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/usb_isp1362.h>
#include <asm/irq.h>
#include <asm/bfin5xx_spi.h>
#include <linux/irq.h>
#include <linux/usb_sl811.h>
#include <asm/bfin5xx_spi.h>
/*
* Name the Board for the /proc/cpuinfo

30
arch/blackfin/mach-bf537/boards/pnav10.c
View File

@ -37,7 +37,7 @@
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
#include <linux/usb_isp1362.h>
#endif
#include <asm/irq.h>
#include <linux/irq.h>
#include <asm/bfin5xx_spi.h>
#include <linux/usb_sl811.h>
@ -294,16 +294,6 @@ static struct bfin5xx_spi_chip spi_mmc_chip_info = {
};
#endif
#if defined(CONFIG_PBX)
static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
.ctl_reg = 0x4, /* send zero */
.enable_dma = 0,
.bits_per_word = 8,
.cs_change_per_word = 1,
};
#endif
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
.cs_change_per_word = 1,
@ -392,24 +382,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.mode = SPI_MODE_3,
},
#endif
#if defined(CONFIG_PBX)
{
.modalias = "fxs-spi",
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
.bus_num = 1,
.chip_select = 3,
.controller_data= &spi_si3xxx_chip_info,
.mode = SPI_MODE_3,
},
{
.modalias = "fxo-spi",
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
.bus_num = 1,
.chip_select = 2,
.controller_data= &spi_si3xxx_chip_info,
.mode = SPI_MODE_3,
},
#endif
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
{
.modalias = "ad7877",

31
arch/blackfin/mach-bf537/boards/stamp.c
View File

@ -37,12 +37,10 @@
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
#include <linux/usb_isp1362.h>
#endif
#include <asm/irq.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <asm/bfin5xx_spi.h>
#include <linux/usb_sl811.h>
#include <asm/bfin5xx_spi.h>
#include <linux/spi/ad7877.h>
/*
@ -159,6 +157,28 @@ static struct platform_device smc91x_device = {
};
#endif
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
static struct resource dm9000_resources[] = {
[0] = {
.start = 0x203FB800,
.end = 0x203FB800 + 8,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_PF9,
.end = IRQ_PF9,
.flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
},
};
static struct platform_device dm9000_device = {
.name = "dm9000",
.id = -1,
.num_resources = ARRAY_SIZE(dm9000_resources),
.resource = dm9000_resources,
};
#endif
#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
static struct resource sl811_hcd_resources[] = {
{
@ -361,7 +381,6 @@ static struct bfin5xx_spi_chip ad5304_chip_info = {
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
// .cs_change_per_word = 1,
.enable_dma = 0,
.bits_per_word = 16,
};
@ -571,6 +590,10 @@ static struct platform_device *stamp_devices[] __initdata = {
&smc91x_device,
#endif
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
&dm9000_device,
#endif
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
&bfin_mac_device,
#endif

115
arch/blackfin/mach-bf537/dma.c Normal file
View File

@ -0,0 +1,115 @@
/*
* File: arch/blackfin/mach-bf537/dma.c
* Based on:
* Author:
*
* Created:
* Description: This file contains the simple DMA Implementation for Blackfin
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <asm/blackfin.h>
#include <asm/dma.h>
struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
(struct dma_register *) DMA0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_NEXT_DESC_PTR,
(struct dma_register *) DMA3_NEXT_DESC_PTR,
(struct dma_register *) DMA4_NEXT_DESC_PTR,
(struct dma_register *) DMA5_NEXT_DESC_PTR,
(struct dma_register *) DMA6_NEXT_DESC_PTR,
(struct dma_register *) DMA7_NEXT_DESC_PTR,
(struct dma_register *) DMA8_NEXT_DESC_PTR,
(struct dma_register *) DMA9_NEXT_DESC_PTR,
(struct dma_register *) DMA10_NEXT_DESC_PTR,
(struct dma_register *) DMA11_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
};
int channel2irq(unsigned int channel)
{
int ret_irq = -1;
switch (channel) {
case CH_PPI:
ret_irq = IRQ_PPI;
break;
case CH_EMAC_RX:
ret_irq = IRQ_MAC_RX;
break;
case CH_EMAC_TX:
ret_irq = IRQ_MAC_TX;
break;
case CH_UART1_RX:
ret_irq = IRQ_UART1_RX;
break;
case CH_UART1_TX:
ret_irq = IRQ_UART1_TX;
break;
case CH_SPORT0_RX:
ret_irq = IRQ_SPORT0_RX;
break;
case CH_SPORT0_TX:
ret_irq = IRQ_SPORT0_TX;
break;
case CH_SPORT1_RX:
ret_irq = IRQ_SPORT1_RX;
break;
case CH_SPORT1_TX:
ret_irq = IRQ_SPORT1_TX;
break;
case CH_SPI:
ret_irq = IRQ_SPI;
break;
case CH_UART_RX:
ret_irq = IRQ_UART_RX;
break;
case CH_UART_TX:
ret_irq = IRQ_UART_TX;
break;
case CH_MEM_STREAM0_SRC:
case CH_MEM_STREAM0_DEST:
ret_irq = IRQ_MEM_DMA0;
break;
case CH_MEM_STREAM1_SRC:
case CH_MEM_STREAM1_DEST:
ret_irq = IRQ_MEM_DMA1;
break;
}
return ret_irq;
}

6
arch/blackfin/mach-bf537/head.S
View File

@ -30,6 +30,8 @@
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/blackfin.h>
#include <asm/trace.h>
#if CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach/mem_init.h>
#endif
@ -93,6 +95,10 @@ ENTRY(__start)
M2 = r0;
M3 = r0;
trace_buffer_start(p0,r0);
P0 = R1;
R0 = R1;
/* Turn off the icache */
p0.l = (IMEM_CONTROL & 0xFFFF);
p0.h = (IMEM_CONTROL >> 16);

2
arch/blackfin/mach-bf537/ints-priority.c
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@ -28,8 +28,8 @@
*/
#include <linux/module.h>
#include <linux/irq.h>
#include <asm/blackfin.h>
#include <asm/irq.h>
void program_IAR(void)
{

316
arch/blackfin/mach-bf548/Kconfig Normal file
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if (BF54x)
menu "BF548 Specific Configuration"
comment "Interrupt Priority Assignment"
menu "Priority"
config IRQ_PLL_WAKEUP
int "IRQ_PLL_WAKEUP"
default 7
config IRQ_DMAC0_ERR
int "IRQ_DMAC0_ERR"
default 7
config IRQ_EPPI0_ERR
int "IRQ_EPPI0_ERR"
default 7
config IRQ_SPORT0_ERR
int "IRQ_SPORT0_ERR"
default 7
config IRQ_SPORT1_ERR
int "IRQ_SPORT1_ERR"
default 7
config IRQ_SPI0_ERR
int "IRQ_SPI0_ERR"
default 7
config IRQ_UART0_ERR
int "IRQ_UART0_ERR"
default 7
config IRQ_RTC
int "IRQ_RTC"
default 8
config IRQ_EPPI0
int "IRQ_EPPI0"
default 8
config IRQ_SPORT0_RX
int "IRQ_SPORT0_RX"
default 9
config IRQ_SPORT0_TX
int "IRQ_SPORT0_TX"
default 9
config IRQ_SPORT1_RX
int "IRQ_SPORT1_RX"
default 9
config IRQ_SPORT1_TX
int "IRQ_SPORT1_TX"
default 9
config IRQ_SPI0
int "IRQ_SPI0"
default 10
config IRQ_UART0_RX
int "IRQ_UART0_RX"
default 10
config IRQ_UART0_TX
int "IRQ_UART0_TX"
default 10
config IRQ_TIMER8
int "IRQ_TIMER8"
default 11
config IRQ_TIMER9
int "IRQ_TIMER9"
default 11
config IRQ_TIMER10
int "IRQ_TIMER10"
default 11
config IRQ_PINT0
int "IRQ_PINT0"
default 12
config IRQ_PINT1
int "IRQ_PINT0"
default 12
config IRQ_MDMAS0
int "IRQ_MDMAS0"
default 13
config IRQ_MDMAS1
int "IRQ_DMDMAS1"
default 13
config IRQ_WATCHDOG
int "IRQ_WATCHDOG"
default 13
config IRQ_DMAC1_ERR
int "IRQ_DMAC1_ERR"
default 7
config IRQ_SPORT2_ERR
int "IRQ_SPORT2_ERR"
default 7
config IRQ_SPORT3_ERR
int "IRQ_SPORT3_ERR"
default 7
config IRQ_MXVR_DATA
int "IRQ MXVR Data"
default 7
config IRQ_SPI1_ERR
int "IRQ_SPI1_ERR"
default 7
config IRQ_SPI2_ERR
int "IRQ_SPI2_ERR"
default 7
config IRQ_UART1_ERR
int "IRQ_UART1_ERR"
default 7
config IRQ_UART2_ERR
int "IRQ_UART2_ERR"
default 7
config IRQ_CAN0_ERR
int "IRQ_CAN0_ERR"
default 7
config IRQ_SPORT2_RX
int "IRQ_SPORT2_RX"
default 9
config IRQ_SPORT2_TX
int "IRQ_SPORT2_TX"
default 9
config IRQ_SPORT3_RX
int "IRQ_SPORT3_RX"
default 9
config IRQ_SPORT3_TX
int "IRQ_SPORT3_TX"
default 9
config IRQ_EPPI1
int "IRQ_EPPI1"
default 9
config IRQ_EPPI2
int "IRQ_EPPI2"
default 9
config IRQ_SPI1
int "IRQ_SPI1"
default 10
config IRQ_SPI2
int "IRQ_SPI2"
default 10
config IRQ_UART1_RX
int "IRQ_UART1_RX"
default 10
config IRQ_UART1_TX
int "IRQ_UART1_TX"
default 10
config IRQ_ATAPI_RX
int "IRQ_ATAPI_RX"
default 10
config IRQ_ATAPI_TX
int "IRQ_ATAPI_TX"
default 10
config IRQ_TWI0
int "IRQ_TWI0"
default 11
config IRQ_TWI1
int "IRQ_TWI1"
default 11
config IRQ_CAN0_RX
int "IRQ_CAN_RX"
default 11
config IRQ_CAN0_TX
int "IRQ_CAN_TX"
default 11
config IRQ_MDMAS2
int "IRQ_MDMAS2"
default 13
config IRQ_MDMAS3
int "IRQ_DMMAS3"
default 13
config IRQ_MXVR_ERR
int "IRQ_MXVR_ERR"
default 11
config IRQ_MXVR_MSG
int "IRQ_MXVR_MSG"
default 11
config IRQ_MXVR_PKT
int "IRQ_MXVR_PKT"
default 11
config IRQ_EPPI1_ERR
int "IRQ_EPPI1_ERR"
default 7
config IRQ_EPPI2_ERR
int "IRQ_EPPI2_ERR"
default 7
config IRQ_UART3_ERR
int "IRQ_UART3_ERR"
default 7
config IRQ_HOST_ERR
int "IRQ_HOST_ERR"
default 7
config IRQ_PIXC_ERR
int "IRQ_PIXC_ERR"
default 7
config IRQ_NFC_ERR
int "IRQ_NFC_ERR"
default 7
config IRQ_ATAPI_ERR
int "IRQ_ATAPI_ERR"
default 7
config IRQ_CAN1_ERR
int "IRQ_CAN1_ERR"
default 7
config IRQ_HS_DMA_ERR
int "IRQ Handshake DMA Status"
default 7
config IRQ_PIXC_IN0
int "IRQ PIXC IN0"
default 8
config IRQ_PIXC_IN1
int "IRQ PIXC IN1"
default 8
config IRQ_PIXC_OUT
int "IRQ PIXC OUT"
default 8
config IRQ_SDH
int "IRQ SDH"
default 8
config IRQ_CNT
int "IRQ CNT"
default 8
config IRQ_KEY
int "IRQ KEY"
default 8
config IRQ_CAN1_RX
int "IRQ CAN1 RX"
default 11
config IRQ_CAN1_TX
int "IRQ_CAN1_TX"
default 11
config IRQ_SDH_MASK0
int "IRQ_SDH_MASK0"
default 11
config IRQ_SDH_MASK1
int "IRQ_SDH_MASK1"
default 11
config IRQ_USB_INT0
int "IRQ USB INT0"
default 11
config IRQ_USB_INT1
int "IRQ USB INT1"
default 11
config IRQ_USB_INT2
int "IRQ USB INT2"
default 11
config IRQ_USB_DMA
int "IRQ USB DMA"
default 11
config IRQ_OTPSEC
int "IRQ OPTSEC"
default 11
config IRQ_TIMER0
int "IRQ_TIMER0"
default 11
config IRQ_TIMER1
int "IRQ_TIMER1"
default 11
config IRQ_TIMER2
int "IRQ_TIMER2"
default 11
config IRQ_TIMER3
int "IRQ_TIMER3"
default 11
config IRQ_TIMER4
int "IRQ_TIMER4"
default 11
config IRQ_TIMER5
int "IRQ_TIMER5"
default 11
config IRQ_TIMER6
int "IRQ_TIMER6"
default 11
config IRQ_TIMER7
int "IRQ_TIMER7"
default 11
config IRQ_PINT2
int "IRQ_PIN2"
default 11
config IRQ_PINT3
int "IRQ_PIN3"
default 11
help
Enter the priority numbers between 7-13 ONLY. Others are Reserved.
This applies to all the above. It is not recommended to assign the
highest priority number 7 to UART or any other device.
endmenu
comment "Pin Interrupt to Port Assignment"
menu "Assignment"
config PINTx_REASSIGN
bool "Reprogram PINT Assignment"
default n
help
The interrupt assignment registers controls the pin-to-interrupt
assignment in a byte-wide manner. Each option allows you to select
a set of pins (High/Low Byte) of an specific Port being mapped
to one of the four PIN Interrupts IRQ_PINTx.
You shouldn't change any of these unless you know exactly what you're doing.
Please consult the Blackfin BF54x Processor Hardware Reference Manual.
config PINT0_ASSIGN
hex "PINT0_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
config PINT1_ASSIGN
hex "PINT1_ASSIGN"
depends on PINTx_REASSIGN
default 0x01010000
config PINT2_ASSIGN
hex "PINT2_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
config PINT3_ASSIGN
hex "PINT3_ASSIGN"
depends on PINTx_REASSIGN
default 0x02020303
endmenu
endmenu
endif

9
arch/blackfin/mach-bf548/Makefile Normal file
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@ -0,0 +1,9 @@
#
# arch/blackfin/mach-bf537/Makefile
#
extra-y := head.o
obj-y := ints-priority.o dma.o gpio.o
obj-$(CONFIG_CPU_FREQ) += cpu.o

5
arch/blackfin/mach-bf548/boards/Makefile Normal file
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@ -0,0 +1,5 @@
#
# arch/blackfin/mach-bf548/boards/Makefile
#
obj-$(CONFIG_BFIN548_EZKIT) += ezkit.o led.o

114
arch/blackfin/mach-bf548/boards/ezkit.c Normal file
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@ -0,0 +1,114 @@
/*
* File: arch/blackfin/mach-bf548/boards/ezkit.c
* Based on: arch/blackfin/mach-bf537/boards/ezkit.c
* Author: Aidan Williams <aidan@nicta.com.au>
*
* Created:
* Description:
*
* Modified:
* Copyright 2005 National ICT Australia (NICTA)
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/irq.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <asm/bfin5xx_spi.h>
/*
* Name the Board for the /proc/cpuinfo
*/
char *bfin_board_name = "ADSP-BF548-EZKIT";
/*
* Driver needs to know address, irq and flag pin.
*/
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
static struct platform_device rtc_device = {
.name = "rtc-bfin",
.id = -1,
};
#endif
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
static struct resource bfin_uart_resources[] = {
#ifdef CONFIG_SERIAL_BFIN_UART0
{
.start = 0xFFC00400,
.end = 0xFFC004FF,
.flags = IORESOURCE_MEM,
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
{
.start = 0xFFC02000,
.end = 0xFFC020FF,
.flags = IORESOURCE_MEM,
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART2
{
.start = 0xFFC02100,
.end = 0xFFC021FF,
.flags = IORESOURCE_MEM,
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART3
{
.start = 0xFFC03100,
.end = 0xFFC031FF,
},
#endif
};
static struct platform_device bfin_uart_device = {
.name = "bfin-uart",
.id = 1,
.num_resources = ARRAY_SIZE(bfin_uart_resources),
.resource = bfin_uart_resources,
};
#endif
static struct platform_device *ezkit_devices[] __initdata = {
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
&rtc_device,
#endif
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
&bfin_uart_device,
#endif
};
static int __init stamp_init(void)
{
printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
return 0;
}
arch_initcall(stamp_init);

172
arch/blackfin/mach-bf548/boards/led.S Normal file
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@ -0,0 +1,172 @@
/****************************************************
* LED1 ---- PG6 LED2 ---- PG7 *
* LED3 ---- PG8 LED4 ---- PG9 *
* LED5 ---- PG10 LED6 ---- PG11 *
****************************************************/
#include <linux/linkage.h>
#include <asm/blackfin.h>
/* All functions in this file save the registers they uses.
So there is no need to save any registers before calling them. */
.text;
/* Initialize LEDs. */
ENTRY(_led_init)
LINK 0;
[--SP] = P0;
[--SP] = R0;
[--SP] = R1;
[--SP] = R2;
R1 = (PG6|PG7|PG8|PG9|PG10|PG11)(Z);
R2 = ~R1;
P0.H = hi(PORTG_FER);
P0.L = lo(PORTG_FER);
R0 = W[P0](Z);
SSYNC;
R0 = R0 & R2;
W[P0] = R0.L;
SSYNC;
P0.H = hi(PORTG_DIR_SET);
P0.L = lo(PORTG_DIR_SET);
W[P0] = R1.L;
SSYNC;
P0.H = hi(PORTG_INEN);
P0.L = lo(PORTG_INEN);
R0 = W[P0](Z);
SSYNC;
R0 = R0 & R2;
W[P0] = R0.L;
SSYNC;
R2 = [SP++];
R1 = [SP++];
R0 = [SP++];
P0 = [SP++];
RTS;
.size _led_init, .-_led_init
/* Set one LED on. Leave other LEDs unchanged.
It expects the LED number passed through R0. */
ENTRY(_led_on)
LINK 0;
[--SP] = P0;
[--SP] = R1;
CALL _led_init;
R1 = 1;
R0 += 5;
R1 <<= R0;
P0.H = hi(PORTG_SET);
P0.L = lo(PORTG_SET);
W[P0] = R1.L;
SSYNC;
R1 = [SP++];
P0 = [SP++];
UNLINK;
RTS;
.size _led_on, .-_led_on
/* Set one LED off. Leave other LEDs unchanged. */
ENTRY(_led_off)
LINK 0;
[--SP] = P0;
[--SP] = R1;
CALL _led_init;
R1 = 1;
R0 += 5;
R1 <<= R0;
P0.H = hi(PORTG_CLEAR);
P0.L = lo(PORTG_CLEAR);
W[P0] = R1.L;
SSYNC;
R1 = [SP++];
P0 = [SP++];
UNLINK;
RTS;
.size _led_off, .-_led_off
/* Toggle one LED. Leave other LEDs unchanged. */
ENTRY(_led_toggle)
LINK 0;
[--SP] = P0;
[--SP] = R1;
CALL _led_init;
R1 = 1;
R0 += 5;
R1 <<= R0;
P0.H = hi(PORTG);
P0.L = lo(PORTG);
R0 = W[P0](Z);
SSYNC;
R0 = R0 ^ R1;
W[P0] = R0.L;
SSYNC;
R1 = [SP++];
P0 = [SP++];
UNLINK;
RTS;
.size _led_toggle, .-_led_toggle
/* Display the number using LEDs in binary format. */
ENTRY(_led_disp_num)
LINK 0;
[--SP] = P0;
[--SP] = R1;
[--SP] = R2;
CALL _led_init;
R1 = 0x3f(X);
R0 = R0 & R1;
R2 = 6(X);
R0 <<= R2;
R1 <<= R2;
P0.H = hi(PORTG);
P0.L = lo(PORTG);
R2 = W[P0](Z);
SSYNC;
R1 = ~R1;
R2 = R2 & R1;
R2 = R2 | R0;
W[P0] = R2.L;
SSYNC;
R2 = [SP++];
R1 = [SP++];
P0 = [SP++];
UNLINK;
RTS;
.size _led_disp_num, .-_led_disp_num
/* Toggle the number using LEDs in binary format. */
ENTRY(_led_toggle_num)
LINK 0;
[--SP] = P0;
[--SP] = R1;
[--SP] = R2;
CALL _led_init;
R1 = 0x3f(X);
R0 = R0 & R1;
R1 = 6(X);
R0 <<= R1;
P0.H = hi(PORTG);
P0.L = lo(PORTG);
R1 = W[P0](Z);
SSYNC;
R1 = R1 ^ R0;
W[P0] = R1.L;
SSYNC;
R2 = [SP++];
R1 = [SP++];
P0 = [SP++];
UNLINK;
RTS;
.size _led_toggle_num, .-_led_toggle_num

159
arch/blackfin/mach-bf548/cpu.c Normal file
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@ -0,0 +1,159 @@
/*
* File: arch/blackfin/mach-bf548/cpu.c
* Based on:
* Author:
*
* Created:
* Description: clock scaling for the bf54x
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <asm/dpmc.h>
#include <linux/fs.h>
#include <asm/bfin-global.h>
/* CONFIG_CLKIN_HZ=25000000 */
#define VCO5 (CONFIG_CLKIN_HZ*45)
#define VCO4 (CONFIG_CLKIN_HZ*36)
#define VCO3 (CONFIG_CLKIN_HZ*27)
#define VCO2 (CONFIG_CLKIN_HZ*18)
#define VCO1 (CONFIG_CLKIN_HZ*9)
#define VCO(x) VCO##x
#define MFREQ(x) {VCO(x),VCO(x)/4},{VCO(x),VCO(x)/2},{VCO(x),VCO(x)}
/* frequency */
static struct cpufreq_frequency_table bf548_freq_table[] = {
MFREQ(1),
MFREQ(3),
{VCO4, VCO4 / 2}, {VCO4, VCO4},
MFREQ(5),
{0, CPUFREQ_TABLE_END},
};
/*
* dpmc_fops->ioctl()
* static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
*/
static int bf548_getfreq(unsigned int cpu)
{
unsigned long cclk_mhz;
/* The driver only support single cpu */
if (cpu == 0)
dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz);
else
cclk_mhz = -1;
return cclk_mhz;
}
static int bf548_target(struct cpufreq_policy *policy,
unsigned int target_freq, unsigned int relation)
{
unsigned long cclk_mhz;
unsigned long vco_mhz;
unsigned long flags;
unsigned int index;
struct cpufreq_freqs freqs;
if (cpufreq_frequency_table_target(policy, bf548_freq_table, target_freq, relation, &index))
return -EINVAL;
cclk_mhz = bf548_freq_table[index].frequency;
vco_mhz = bf548_freq_table[index].index;
dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz);
freqs.old = bf548_getfreq(0);
freqs.new = cclk_mhz;
freqs.cpu = 0;
pr_debug("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n",
cclk_mhz, vco_mhz, index, target_freq, freqs.old);
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
local_irq_save(flags);
dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz);
local_irq_restore(flags);
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
vco_mhz = get_vco();
cclk_mhz = get_cclk();
return 0;
}
/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
* this platform, anyway.
*/
static int bf548_verify_speed(struct cpufreq_policy *policy)
{
return cpufreq_frequency_table_verify(policy, &bf548_freq_table);
}
static int __init __bf548_cpu_init(struct cpufreq_policy *policy)
{
if (policy->cpu != 0)
return -EINVAL;
policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
/*Now ,only support one cpu */
policy->cur = bf548_getfreq(0);
cpufreq_frequency_table_get_attr(bf548_freq_table, policy->cpu);
return cpufreq_frequency_table_cpuinfo(policy, bf548_freq_table);
}
static struct freq_attr *bf548_freq_attr[] = {
&cpufreq_freq_attr_scaling_available_freqs,
NULL,
};
static struct cpufreq_driver bf548_driver = {
.verify = bf548_verify_speed,
.target = bf548_target,
.get = bf548_getfreq,
.init = __bf548_cpu_init,
.name = "bf548",
.owner = THIS_MODULE,
.attr = bf548_freq_attr,
};
static int __init bf548_cpu_init(void)
{
return cpufreq_register_driver(&bf548_driver);
}
static void __exit bf548_cpu_exit(void)
{
cpufreq_unregister_driver(&bf548_driver);
}
MODULE_AUTHOR("Mickael Kang");
MODULE_DESCRIPTION("cpufreq driver for BF548 CPU");
MODULE_LICENSE("GPL");
module_init(bf548_cpu_init);
module_exit(bf548_cpu_exit);

156
arch/blackfin/mach-bf548/dma.c Normal file
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/*
* File: arch/blackfin/mach-bf561/dma.c
* Based on:
* Author:
*
* Created:
* Description: This file contains the simple DMA Implementation for Blackfin
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <asm/blackfin.h>
#include <asm/dma.h>
struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
(struct dma_register *) DMA0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_NEXT_DESC_PTR,
(struct dma_register *) DMA3_NEXT_DESC_PTR,
(struct dma_register *) DMA4_NEXT_DESC_PTR,
(struct dma_register *) DMA5_NEXT_DESC_PTR,
(struct dma_register *) DMA6_NEXT_DESC_PTR,
(struct dma_register *) DMA7_NEXT_DESC_PTR,
(struct dma_register *) DMA8_NEXT_DESC_PTR,
(struct dma_register *) DMA9_NEXT_DESC_PTR,
(struct dma_register *) DMA10_NEXT_DESC_PTR,
(struct dma_register *) DMA11_NEXT_DESC_PTR,
(struct dma_register *) DMA12_NEXT_DESC_PTR,
(struct dma_register *) DMA13_NEXT_DESC_PTR,
(struct dma_register *) DMA14_NEXT_DESC_PTR,
(struct dma_register *) DMA15_NEXT_DESC_PTR,
(struct dma_register *) DMA16_NEXT_DESC_PTR,
(struct dma_register *) DMA17_NEXT_DESC_PTR,
(struct dma_register *) DMA18_NEXT_DESC_PTR,
(struct dma_register *) DMA19_NEXT_DESC_PTR,
(struct dma_register *) DMA20_NEXT_DESC_PTR,
(struct dma_register *) DMA21_NEXT_DESC_PTR,
(struct dma_register *) DMA22_NEXT_DESC_PTR,
(struct dma_register *) DMA23_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
};
int channel2irq(unsigned int channel)
{
int ret_irq = -1;
switch (channel) {
case CH_SPORT0_RX:
ret_irq = IRQ_SPORT0_RX;
break;
case CH_SPORT0_TX:
ret_irq = IRQ_SPORT0_TX;
break;
case CH_SPORT1_RX:
ret_irq = IRQ_SPORT1_RX;
break;
case CH_SPORT1_TX:
ret_irq = IRQ_SPORT1_TX;
case CH_SPI0:
ret_irq = IRQ_SPI0;
break;
case CH_SPI1:
ret_irq = IRQ_SPI1;
break;
case CH_UART0_RX:
ret_irq = IRQ_UART_RX;
break;
case CH_UART0_TX:
ret_irq = IRQ_UART_TX;
break;
case CH_UART1_RX:
ret_irq = IRQ_UART_RX;
break;
case CH_UART1_TX:
ret_irq = IRQ_UART_TX;
break;
case CH_EPPI0:
ret_irq = IRQ_EPPI0;
break;
case CH_EPPI1:
ret_irq = IRQ_EPPI1;
break;
case CH_EPPI2:
ret_irq = IRQ_EPPI2;
break;
case CH_PIXC_IMAGE:
ret_irq = IRQ_PIXC_IN0;
break;
case CH_PIXC_OVERLAY:
ret_irq = IRQ_PIXC_IN1;
break;
case CH_PIXC_OUTPUT:
ret_irq = IRQ_PIXC_OUT;
break;
case CH_SPORT2_RX:
ret_irq = IRQ_SPORT2_RX;
break;
case CH_SPORT2_TX:
ret_irq = IRQ_SPORT2_TX;
break;
case CH_SPORT3_RX:
ret_irq = IRQ_SPORT3_RX;
break;
case CH_SPORT3_TX:
ret_irq = IRQ_SPORT3_TX;
break;
case CH_SDH:
ret_irq = IRQ_SDH;
break;
case CH_SPI2:
ret_irq = IRQ_SPI2;
break;
case CH_MEM_STREAM0_SRC:
case CH_MEM_STREAM0_DEST:
ret_irq = IRQ_MDMAS0;
break;
case CH_MEM_STREAM1_SRC:
case CH_MEM_STREAM1_DEST:
ret_irq = IRQ_MDMAS1;
break;
case CH_MEM_STREAM2_SRC:
case CH_MEM_STREAM2_DEST:
ret_irq = IRQ_MDMAS2;
break;
case CH_MEM_STREAM3_SRC:
case CH_MEM_STREAM3_DEST:
ret_irq = IRQ_MDMAS3;
break;
}
return ret_irq;
}

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arch/blackfin/mach-bf548/gpio.c Normal file
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/*
* File: arch/blackfin/mach-bf548/gpio.c
* Based on:
* Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
*
* Created:
* Description: GPIO Abstraction Layer
*
* Modified:
* Copyright 2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/module.h>
#include <linux/err.h>
#include <asm/blackfin.h>
#include <asm/gpio.h>
#include <asm/portmux.h>
#include <linux/irq.h>
static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
(struct gpio_port_t *)PORTA_FER,
(struct gpio_port_t *)PORTB_FER,
(struct gpio_port_t *)PORTC_FER,
(struct gpio_port_t *)PORTD_FER,
(struct gpio_port_t *)PORTE_FER,
(struct gpio_port_t *)PORTF_FER,
(struct gpio_port_t *)PORTG_FER,
(struct gpio_port_t *)PORTH_FER,
(struct gpio_port_t *)PORTI_FER,
(struct gpio_port_t *)PORTJ_FER,
};
static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
static unsigned short reserved_peri_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
inline int check_gpio(unsigned short gpio)
{
if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
|| gpio == GPIO_PH14 || gpio == GPIO_PH15
|| gpio == GPIO_PJ14 || gpio == GPIO_PJ15
|| gpio > MAX_BLACKFIN_GPIOS)
return -EINVAL;
return 0;
}
inline void portmux_setup(unsigned short portno, unsigned short function)
{
u32 pmux;
pmux = gpio_array[gpio_bank(portno)]->port_mux;
pmux &= ~(0x3 << (2 * gpio_sub_n(portno)));
pmux |= (function & 0x3) << (2 * gpio_sub_n(portno));
gpio_array[gpio_bank(portno)]->port_mux = pmux;
}
inline u16 get_portmux(unsigned short portno)
{
u32 pmux;
pmux = gpio_array[gpio_bank(portno)]->port_mux;
return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
}
static void port_setup(unsigned short gpio, unsigned short usage)
{
if (usage == GPIO_USAGE) {
if (gpio_array[gpio_bank(gpio)]->port_fer & gpio_bit(gpio))
printk(KERN_WARNING
"bfin-gpio: Possible Conflict with Peripheral "
"usage and GPIO %d detected!\n", gpio);
gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
} else
gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
SSYNC();
}
static int __init bfin_gpio_init(void)
{
printk(KERN_INFO "Blackfin GPIO Controller\n");
return 0;
}
arch_initcall(bfin_gpio_init);
int peripheral_request(unsigned short per, const char *label)
{
unsigned long flags;
unsigned short ident = P_IDENT(per);
if (!(per & P_DEFINED))
return -ENODEV;
if (check_gpio(ident) < 0)
return -EINVAL;
local_irq_save(flags);
if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
printk(KERN_ERR
"%s: Peripheral %d is already reserved as GPIO!\n",
__FUNCTION__, per);
dump_stack();
local_irq_restore(flags);
return -EBUSY;
}
if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
u16 funct = get_portmux(ident);
if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
printk(KERN_ERR
"%s: Peripheral %d is already reserved!\n",
__FUNCTION__, per);
dump_stack();
local_irq_restore(flags);
return -EBUSY;
}
}
reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
portmux_setup(ident, P_FUNCT2MUX(per));
port_setup(ident, PERIPHERAL_USAGE);
local_irq_restore(flags);
return 0;
}
EXPORT_SYMBOL(peripheral_request);
int peripheral_request_list(unsigned short per[], const char *label)
{
u16 cnt;
int ret;
for (cnt = 0; per[cnt] != 0; cnt++) {
ret = peripheral_request(per[cnt], label);
if (ret < 0)
return ret;
}
return 0;
}
EXPORT_SYMBOL(peripheral_request_list);
void peripheral_free(unsigned short per)
{
unsigned long flags;
unsigned short ident = P_IDENT(per);
if (!(per & P_DEFINED))
return;
if (check_gpio(ident) < 0)
return;
local_irq_save(flags);
if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
printk(KERN_ERR "bfin-gpio: Peripheral %d wasn't reserved!\n", per);
dump_stack();
local_irq_restore(flags);
return;
}
if (!(per & P_MAYSHARE)) {
port_setup(ident, GPIO_USAGE);
}
reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
local_irq_restore(flags);
}
EXPORT_SYMBOL(peripheral_free);
void peripheral_free_list(unsigned short per[])
{
u16 cnt;
for (cnt = 0; per[cnt] != 0; cnt++) {
peripheral_free(per[cnt]);
}
}
EXPORT_SYMBOL(peripheral_free_list);
/***********************************************************
*
* FUNCTIONS: Blackfin GPIO Driver
*
* INPUTS/OUTPUTS:
* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
*
*
* DESCRIPTION: Blackfin GPIO Driver API
*
* CAUTION:
*************************************************************
* MODIFICATION HISTORY :
**************************************************************/
int gpio_request(unsigned short gpio, const char *label)
{
unsigned long flags;
if (check_gpio(gpio) < 0)
return -EINVAL;
local_irq_save(flags);
if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved!\n", gpio);
dump_stack();
local_irq_restore(flags);
return -EBUSY;
}
if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
printk(KERN_ERR
"bfin-gpio: GPIO %d is already reserved as Peripheral!\n", gpio);
dump_stack();
local_irq_restore(flags);
return -EBUSY;
}
reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
local_irq_restore(flags);
port_setup(gpio, GPIO_USAGE);
return 0;
}
EXPORT_SYMBOL(gpio_request);
void gpio_free(unsigned short gpio)
{
unsigned long flags;
if (check_gpio(gpio) < 0)
return;
local_irq_save(flags);
if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio);
dump_stack();
local_irq_restore(flags);
return;
}
reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
local_irq_restore(flags);
}
EXPORT_SYMBOL(gpio_free);
void gpio_direction_input(unsigned short gpio)
{
unsigned long flags;
BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
local_irq_save(flags);
gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
local_irq_restore(flags);
}
EXPORT_SYMBOL(gpio_direction_input);
void gpio_direction_output(unsigned short gpio)
{
unsigned long flags;
BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
local_irq_save(flags);
gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
local_irq_restore(flags);
}
EXPORT_SYMBOL(gpio_direction_output);
void gpio_set_value(unsigned short gpio, unsigned short arg)
{
if (arg)
gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
else
gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
}
EXPORT_SYMBOL(gpio_set_value);
unsigned short gpio_get_value(unsigned short gpio)
{
return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
}
EXPORT_SYMBOL(gpio_get_value);

512
arch/blackfin/mach-bf548/head.S Normal file
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/*
* File: arch/blackfin/mach-bf548/head.S
* Based on: arch/blackfin/mach-bf537/head.S
* Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
*
* Created: 1998
* Description: Startup code for Blackfin BF548
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/linkage.h>
#include <asm/blackfin.h>
#include <asm/trace.h>
#if CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach/mem_init.h>
#endif
.global __rambase
.global __ramstart
.global __ramend
.extern ___bss_stop
.extern ___bss_start
.extern _bf53x_relocate_l1_mem
#define INITIAL_STACK 0xFFB01000
.text
ENTRY(__start)
ENTRY(__stext)
/* R0: argument of command line string, passed from uboot, save it */
R7 = R0;
/* Set the SYSCFG register */
R0 = 0x36;
SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
R0 = 0;
/* Clear Out All the data and pointer Registers*/
R1 = R0;
R2 = R0;
R3 = R0;
R4 = R0;
R5 = R0;
R6 = R0;
P0 = R0;
P1 = R0;
P2 = R0;
P3 = R0;
P4 = R0;
P5 = R0;
LC0 = r0;
LC1 = r0;
L0 = r0;
L1 = r0;
L2 = r0;
L3 = r0;
/* Clear Out All the DAG Registers*/
B0 = r0;
B1 = r0;
B2 = r0;
B3 = r0;
I0 = r0;
I1 = r0;
I2 = r0;
I3 = r0;
M0 = r0;
M1 = r0;
M2 = r0;
M3 = r0;
trace_buffer_start(p0,r0);
P0 = R1;
R0 = R1;
/* Turn off the icache */
p0.l = (IMEM_CONTROL & 0xFFFF);
p0.h = (IMEM_CONTROL >> 16);
R1 = [p0];
R0 = ~ENICPLB;
R0 = R0 & R1;
[p0] = R0;
SSYNC;
/* Turn off the dcache */
p0.l = (DMEM_CONTROL & 0xFFFF);
p0.h = (DMEM_CONTROL >> 16);
R1 = [p0];
R0 = ~ENDCPLB;
R0 = R0 & R1;
[p0] = R0;
SSYNC;
/* Initialize stack pointer */
SP.L = LO(INITIAL_STACK);
SP.H = HI(INITIAL_STACK);
FP = SP;
USP = SP;
/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
call _bf53x_relocate_l1_mem;
#if CONFIG_BFIN_KERNEL_CLOCK
call _start_dma_code;
#endif
/* Code for initializing Async memory banks */
p2.h = hi(EBIU_AMBCTL1);
p2.l = lo(EBIU_AMBCTL1);
r0.h = hi(AMBCTL1VAL);
r0.l = lo(AMBCTL1VAL);
[p2] = r0;
ssync;
p2.h = hi(EBIU_AMBCTL0);
p2.l = lo(EBIU_AMBCTL0);
r0.h = hi(AMBCTL0VAL);
r0.l = lo(AMBCTL0VAL);
[p2] = r0;
ssync;
p2.h = hi(EBIU_AMGCTL);
p2.l = lo(EBIU_AMGCTL);
r0 = AMGCTLVAL;
w[p2] = r0;
ssync;
/* This section keeps the processor in supervisor mode
* during kernel boot. Switches to user mode at end of boot.
* See page 3-9 of Hardware Reference manual for documentation.
*/
/* EVT15 = _real_start */
p0.l = lo(EVT15);
p0.h = hi(EVT15);
p1.l = _real_start;
p1.h = _real_start;
[p0] = p1;
csync;
p0.l = lo(IMASK);
p0.h = hi(IMASK);
p1.l = IMASK_IVG15;
p1.h = 0x0;
[p0] = p1;
csync;
raise 15;
p0.l = .LWAIT_HERE;
p0.h = .LWAIT_HERE;
reti = p0;
#if defined (ANOMALY_05000281)
nop;
nop;
nop;
#endif
rti;
.LWAIT_HERE:
jump .LWAIT_HERE;
ENTRY(_real_start)
[ -- sp ] = reti;
p0.l = lo(WDOG_CTL);
p0.h = hi(WDOG_CTL);
r0 = 0xAD6(z);
w[p0] = r0; /* watchdog off for now */
ssync;
/* Code update for BSS size == 0
* Zero out the bss region.
*/
p1.l = ___bss_start;
p1.h = ___bss_start;
p2.l = ___bss_stop;
p2.h = ___bss_stop;
r0 = 0;
p2 -= p1;
lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2;
.L_clear_bss:
B[p1++] = r0;
/* In case there is a NULL pointer reference
* Zero out region before stext
*/
p1.l = 0x0;
p1.h = 0x0;
r0.l = __stext;
r0.h = __stext;
r0 = r0 >> 1;
p2 = r0;
r0 = 0;
lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2;
.L_clear_zero:
W[p1++] = r0;
/* pass the uboot arguments to the global value command line */
R0 = R7;
call _cmdline_init;
p1.l = __rambase;
p1.h = __rambase;
r0.l = __sdata;
r0.h = __sdata;
[p1] = r0;
p1.l = __ramstart;
p1.h = __ramstart;
p3.l = ___bss_stop;
p3.h = ___bss_stop;
r1 = p3;
[p1] = r1;
/*
* load the current thread pointer and stack
*/
r1.l = _init_thread_union;
r1.h = _init_thread_union;
r2.l = 0x2000;
r2.h = 0x0000;
r1 = r1 + r2;
sp = r1;
usp = sp;
fp = sp;
call _start_kernel;
.L_exit:
jump.s .L_exit;
.section .l1.text
#if CONFIG_BFIN_KERNEL_CLOCK
ENTRY(_start_dma_code)
/* Enable PHY CLK buffer output */
p0.h = hi(VR_CTL);
p0.l = lo(VR_CTL);
r0.l = w[p0];
bitset(r0, 14);
w[p0] = r0.l;
ssync;
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
r0.l = 0x1;
r0.h = 0x0;
[p0] = r0;
SSYNC;
/*
* Set PLL_CTL
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
* - [7] = output delay (add 200ps of delay to mem signals)
* - [6] = input delay (add 200ps of input delay to mem signals)
* - [5] = PDWN : 1=All Clocks off
* - [3] = STOPCK : 1=Core Clock off
* - [1] = PLL_OFF : 1=Disable Power to PLL
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
* all other bits set to zero
*/
p0.h = hi(PLL_LOCKCNT);
p0.l = lo(PLL_LOCKCNT);
r0 = 0x300(Z);
w[p0] = r0.l;
ssync;
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITSET (R0, 24);
[P2] = R0;
SSYNC;
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
r0 = r0 << 9; /* Shift it over, */
r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
r0 = r1 | r0;
r1 = PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL); /* Load the address */
cli r2; /* Disable interrupts */
ssync;
w[p0] = r0.l; /* Set the value */
idle; /* Wait for the PLL to stablize */
sti r2; /* Enable interrupts */
.Lcheck_again:
p0.h = hi(PLL_STAT);
p0.l = lo(PLL_STAT);
R0 = W[P0](Z);
CC = BITTST(R0,5);
if ! CC jump .Lcheck_again;
/* Configure SCLK & CCLK Dividers */
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
p0.h = hi(PLL_DIV);
p0.l = lo(PLL_DIV);
w[p0] = r0.l;
ssync;
p0.l = lo(EBIU_SDRRC);
p0.h = hi(EBIU_SDRRC);
r0 = mem_SDRRC;
w[p0] = r0.l;
ssync;
p0.l = (EBIU_SDBCTL & 0xFFFF);
p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
r0 = mem_SDBCTL;
w[p0] = r0.l;
ssync;
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITCLR (R0, 24);
p0.h = hi(EBIU_SDSTAT);
p0.l = lo(EBIU_SDSTAT);
r2.l = w[p0];
cc = bittst(r2,3);
if !cc jump .Lskip;
NOP;
BITSET (R0, 23);
.Lskip:
[P2] = R0;
SSYNC;
R0.L = lo(mem_SDGCTL);
R0.H = hi(mem_SDGCTL);
R1 = [p2];
R1 = R1 | R0;
[P2] = R1;
SSYNC;
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
r0.l = lo(IWR_ENABLE_ALL);
r0.h = hi(IWR_ENABLE_ALL);
[p0] = r0;
SSYNC;
RTS;
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
ENTRY(_bfin_reset)
/* No more interrupts to be handled*/
CLI R6;
SSYNC;
#if defined(CONFIG_MTD_M25P80)
/*
* The following code fix the SPI flash reboot issue,
* /CS signal of the chip which is using PF10 return to GPIO mode
*/
p0.h = hi(PORTF_FER);
p0.l = lo(PORTF_FER);
r0.l = 0x0000;
w[p0] = r0.l;
SSYNC;
/* /CS return to high */
p0.h = hi(PORTFIO);
p0.l = lo(PORTFIO);
r0.l = 0xFFFF;
w[p0] = r0.l;
SSYNC;
/* Delay some time, This is necessary */
r1.h = 0;
r1.l = 0x400;
p1 = r1;
lsetup (_delay_lab1,_delay_lab1_end ) lc1 = p1;
_delay_lab1:
r0.h = 0;
r0.l = 0x8000;
p0 = r0;
lsetup (_delay_lab0,_delay_lab0_end ) lc0 = p0;
_delay_lab0:
nop;
_delay_lab0_end:
nop;
_delay_lab1_end:
nop;
#endif
/* Clear the bits 13-15 in SWRST if they werent cleared */
p0.h = hi(SWRST);
p0.l = lo(SWRST);
csync;
r0.l = w[p0];
/* Clear the IMASK register */
p0.h = hi(IMASK);
p0.l = lo(IMASK);
r0 = 0x0;
[p0] = r0;
/* Clear the ILAT register */
p0.h = hi(ILAT);
p0.l = lo(ILAT);
r0 = [p0];
[p0] = r0;
SSYNC;
/* Disable the WDOG TIMER */
p0.h = hi(WDOG_CTL);
p0.l = lo(WDOG_CTL);
r0.l = 0xAD6;
w[p0] = r0.l;
SSYNC;
/* Clear the sticky bit incase it is already set */
p0.h = hi(WDOG_CTL);
p0.l = lo(WDOG_CTL);
r0.l = 0x8AD6;
w[p0] = r0.l;
SSYNC;
/* Program the count value */
R0.l = 0x100;
R0.h = 0x0;
P0.h = hi(WDOG_CNT);
P0.l = lo(WDOG_CNT);
[P0] = R0;
SSYNC;
/* Program WDOG_STAT if necessary */
P0.h = hi(WDOG_CTL);
P0.l = lo(WDOG_CTL);
R0 = W[P0](Z);
CC = BITTST(R0,1);
if !CC JUMP .LWRITESTAT;
CC = BITTST(R0,2);
if !CC JUMP .LWRITESTAT;
JUMP .LSKIP_WRITE;
.LWRITESTAT:
/* When watch dog timer is enabled,
* a write to STAT will load the contents of CNT to STAT
*/
R0 = 0x0000(z);
P0.h = hi(WDOG_STAT);
P0.l = lo(WDOG_STAT)
[P0] = R0;
SSYNC;
.LSKIP_WRITE:
/* Enable the reset event */
P0.h = hi(WDOG_CTL);
P0.l = lo(WDOG_CTL);
R0 = W[P0](Z);
BITCLR(R0,1);
BITCLR(R0,2);
W[P0] = R0.L;
SSYNC;
NOP;
/* Enable the wdog counter */
R0 = W[P0](Z);
BITCLR(R0,4);
W[P0] = R0.L;
SSYNC;
IDLE;
RTS;
.data
/*
* Set up the usable of RAM stuff. Size of RAM is determined then
* an initial stack set up at the end.
*/
.align 4
__rambase:
.long 0
__ramstart:
.long 0
__ramend:
.long 0

137
arch/blackfin/mach-bf548/ints-priority.c Normal file
View File

@ -0,0 +1,137 @@
/*
* File: arch/blackfin/mach-bf537/ints-priority.c
* Based on: arch/blackfin/mach-bf533/ints-priority.c
* Author: Michael Hennerich
*
* Created:
* Description: Set up the interupt priorities
*
* Modified:
* Copyright 2004-2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/module.h>
#include <linux/irq.h>
#include <asm/blackfin.h>
void program_IAR(void)
{
/* Program the IAR0 Register with the configured priority */
bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
((CONFIG_IRQ_DMAC0_ERR - 7) << IRQ_DMAC0_ERR_POS) |
((CONFIG_IRQ_EPPI0_ERR - 7) << IRQ_EPPI0_ERR_POS) |
((CONFIG_IRQ_SPORT0_ERR - 7) << IRQ_SPORT0_ERR_POS) |
((CONFIG_IRQ_SPORT1_ERR - 7) << IRQ_SPORT1_ERR_POS) |
((CONFIG_IRQ_SPI0_ERR - 7) << IRQ_SPI0_ERR_POS) |
((CONFIG_IRQ_UART0_ERR - 7) << IRQ_UART0_ERR_POS) |
((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
bfin_write_SIC_IAR1(((CONFIG_IRQ_EPPI0 - 7) << IRQ_EPPI0_POS) |
((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
((CONFIG_IRQ_PINT0 - 7) << IRQ_PINT0_POS) |
((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCHDOG_POS));
bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |
((CONFIG_IRQ_SPORT3_ERR - 7) << IRQ_SPORT3_ERR_POS) |
((CONFIG_IRQ_MXVR_DATA - 7) << IRQ_MXVR_DATA_POS) |
((CONFIG_IRQ_SPI1_ERR - 7) << IRQ_SPI1_ERR_POS) |
((CONFIG_IRQ_SPI2_ERR - 7) << IRQ_SPI2_ERR_POS) |
((CONFIG_IRQ_UART1_ERR - 7) << IRQ_UART1_ERR_POS) |
((CONFIG_IRQ_UART2_ERR - 7) << IRQ_UART2_ERR_POS));
bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN0_ERR - 7) << IRQ_CAN0_ERR_POS) |
((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
((CONFIG_IRQ_EPPI1 - 7) << IRQ_EPPI1_POS) |
((CONFIG_IRQ_EPPI2 - 7) << IRQ_EPPI2_POS) |
((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
((CONFIG_IRQ_ATAPI_RX - 7) << IRQ_ATAPI_RX_POS) |
((CONFIG_IRQ_ATAPI_TX - 7) << IRQ_ATAPI_TX_POS) |
((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
((CONFIG_IRQ_CAN0_RX - 7) << IRQ_CAN0_RX_POS));
bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN0_TX - 7) << IRQ_CAN0_TX_POS) |
((CONFIG_IRQ_MDMAS2 - 7) << IRQ_MDMAS2_POS) |
((CONFIG_IRQ_MDMAS3 - 7) << IRQ_MDMAS3_POS) |
((CONFIG_IRQ_MXVR_ERR - 7) << IRQ_MXVR_ERR_POS) |
((CONFIG_IRQ_MXVR_MSG - 7) << IRQ_MXVR_MSG_POS) |
((CONFIG_IRQ_MXVR_PKT - 7) << IRQ_MXVR_PKT_POS) |
((CONFIG_IRQ_EPPI1_ERR - 7) << IRQ_EPPI1_ERR_POS) |
((CONFIG_IRQ_EPPI2_ERR - 7) << IRQ_EPPI2_ERR_POS));
bfin_write_SIC_IAR7(((CONFIG_IRQ_UART3_ERR - 7) << IRQ_UART3_ERR_POS) |
((CONFIG_IRQ_HOST_ERR - 7) << IRQ_HOST_ERR_POS) |
((CONFIG_IRQ_PIXC_ERR - 7) << IRQ_PIXC_ERR_POS) |
((CONFIG_IRQ_NFC_ERR - 7) << IRQ_NFC_ERR_POS) |
((CONFIG_IRQ_ATAPI_ERR - 7) << IRQ_ATAPI_ERR_POS) |
((CONFIG_IRQ_CAN1_ERR - 7) << IRQ_CAN1_ERR_POS) |
((CONFIG_IRQ_HS_DMA_ERR - 7) << IRQ_HS_DMA_ERR_POS));
bfin_write_SIC_IAR8(((CONFIG_IRQ_PIXC_IN0 - 7) << IRQ_PIXC_IN1_POS) |
((CONFIG_IRQ_PIXC_IN1 - 7) << IRQ_PIXC_IN1_POS) |
((CONFIG_IRQ_PIXC_OUT - 7) << IRQ_PIXC_OUT_POS) |
((CONFIG_IRQ_SDH - 7) << IRQ_SDH_POS) |
((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
((CONFIG_IRQ_KEY - 7) << IRQ_KEY_POS) |
((CONFIG_IRQ_CAN1_RX - 7) << IRQ_CAN1_RX_POS) |
((CONFIG_IRQ_CAN1_TX - 7) << IRQ_CAN1_TX_POS));
bfin_write_SIC_IAR9(((CONFIG_IRQ_SDH_MASK0 - 7) << IRQ_SDH_MASK0_POS) |
((CONFIG_IRQ_SDH_MASK1 - 7) << IRQ_SDH_MASK1_POS) |
((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS) |
((CONFIG_IRQ_OTPSEC - 7) << IRQ_OTPSEC_POS));
bfin_write_SIC_IAR10(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS));
bfin_write_SIC_IAR11(((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
((CONFIG_IRQ_PINT2 - 7) << IRQ_PINT2_POS) |
((CONFIG_IRQ_PINT3 - 7) << IRQ_PINT3_POS));
SSYNC();
}

2
arch/blackfin/mach-bf561/Makefile
View File

@ -4,6 +4,6 @@
extra-y := head.o
obj-y := ints-priority.o
obj-y := ints-priority.o dma.o
obj-$(CONFIG_BF561_COREB) += coreb.o

2
arch/blackfin/mach-bf561/boards/cm_bf561.c
View File

@ -34,7 +34,7 @@
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/usb_isp1362.h>
#include <asm/irq.h>
#include <linux/irq.h>
#include <asm/bfin5xx_spi.h>
/*

9
arch/blackfin/mach-bf561/boards/ezkit.c
View File

@ -30,10 +30,9 @@
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <asm/irq.h>
#include <asm/bfin5xx_spi.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <asm/bfin5xx_spi.h>
/*
* Name the Board for the /proc/cpuinfo
@ -45,13 +44,13 @@ char *bfin_board_name = "ADDS-BF561-EZKIT";
#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
static struct resource bfin_isp1761_resources[] = {
[0] = {
{
.name = "isp1761-regs",
.start = ISP1761_BASE + 0x00000000,
.end = ISP1761_BASE + 0x000fffff,
.flags = IORESOURCE_MEM,
},
[1] = {
{
.start = ISP1761_IRQ,
.end = ISP1761_IRQ,
.flags = IORESOURCE_IRQ,

2
arch/blackfin/mach-bf561/boards/generic_board.c
View File

@ -30,7 +30,7 @@
#include <linux/device.h>
#include <linux/platform_device.h>
#include <asm/irq.h>
#include <linux/irq.h>
char *bfin_board_name = "UNKNOWN BOARD";

2
arch/blackfin/mach-bf561/boards/tepla.c
View File

@ -14,7 +14,7 @@
#include <linux/device.h>
#include <linux/platform_device.h>
#include <asm/irq.h>
#include <linux/irq.h>
char *bfin_board_name = "Tepla-BF561";

2
arch/blackfin/mach-bf561/coreb.c
View File

@ -32,8 +32,8 @@
#include <linux/device.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/uaccess.h>
#include <asm/dma.h>
#include <asm/uaccess.h>
#define MODULE_VER "v0.1"

131
arch/blackfin/mach-bf561/dma.c Normal file
View File

@ -0,0 +1,131 @@
/*
* File: arch/blackfin/mach-bf561/dma.c
* Based on:
* Author:
*
* Created:
* Description: This file contains the simple DMA Implementation for Blackfin
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <asm/blackfin.h>
#include <asm/dma.h>
struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
(struct dma_register *) DMA1_0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_1_NEXT_DESC_PTR,
(struct dma_register *) DMA1_2_NEXT_DESC_PTR,
(struct dma_register *) DMA1_3_NEXT_DESC_PTR,
(struct dma_register *) DMA1_4_NEXT_DESC_PTR,
(struct dma_register *) DMA1_5_NEXT_DESC_PTR,
(struct dma_register *) DMA1_6_NEXT_DESC_PTR,
(struct dma_register *) DMA1_7_NEXT_DESC_PTR,
(struct dma_register *) DMA1_8_NEXT_DESC_PTR,
(struct dma_register *) DMA1_9_NEXT_DESC_PTR,
(struct dma_register *) DMA1_10_NEXT_DESC_PTR,
(struct dma_register *) DMA1_11_NEXT_DESC_PTR,
(struct dma_register *) DMA2_0_NEXT_DESC_PTR,
(struct dma_register *) DMA2_1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_2_NEXT_DESC_PTR,
(struct dma_register *) DMA2_3_NEXT_DESC_PTR,
(struct dma_register *) DMA2_4_NEXT_DESC_PTR,
(struct dma_register *) DMA2_5_NEXT_DESC_PTR,
(struct dma_register *) DMA2_6_NEXT_DESC_PTR,
(struct dma_register *) DMA2_7_NEXT_DESC_PTR,
(struct dma_register *) DMA2_8_NEXT_DESC_PTR,
(struct dma_register *) DMA2_9_NEXT_DESC_PTR,
(struct dma_register *) DMA2_10_NEXT_DESC_PTR,
(struct dma_register *) DMA2_11_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
};
int channel2irq(unsigned int channel)
{
int ret_irq = -1;
switch (channel) {
case CH_PPI0:
ret_irq = IRQ_PPI0;
break;
case CH_PPI1:
ret_irq = IRQ_PPI1;
break;
case CH_SPORT0_RX:
ret_irq = IRQ_SPORT0_RX;
break;
case CH_SPORT0_TX:
ret_irq = IRQ_SPORT0_TX;
break;
case CH_SPORT1_RX:
ret_irq = IRQ_SPORT1_RX;
break;
case CH_SPORT1_TX:
ret_irq = IRQ_SPORT1_TX;
break;
case CH_SPI:
ret_irq = IRQ_SPI;
break;
case CH_UART_RX:
ret_irq = IRQ_UART_RX;
break;
case CH_UART_TX:
ret_irq = IRQ_UART_TX;
break;
case CH_MEM_STREAM0_SRC:
case CH_MEM_STREAM0_DEST:
ret_irq = IRQ_MEM_DMA0;
break;
case CH_MEM_STREAM1_SRC:
case CH_MEM_STREAM1_DEST:
ret_irq = IRQ_MEM_DMA1;
break;
case CH_MEM_STREAM2_SRC:
case CH_MEM_STREAM2_DEST:
ret_irq = IRQ_MEM_DMA2;
break;
case CH_MEM_STREAM3_SRC:
case CH_MEM_STREAM3_DEST:
ret_irq = IRQ_MEM_DMA3;
break;
case CH_IMEM_STREAM0_SRC:
case CH_IMEM_STREAM0_DEST:
ret_irq = IRQ_IMEM_DMA0;
break;
case CH_IMEM_STREAM1_SRC:
case CH_IMEM_STREAM1_DEST:
ret_irq = IRQ_IMEM_DMA1;
break;
}
return ret_irq;
}

6
arch/blackfin/mach-bf561/head.S
View File

@ -30,6 +30,8 @@
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/blackfin.h>
#include <asm/trace.h>
#if CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach/mem_init.h>
#endif
@ -93,6 +95,10 @@ ENTRY(__start)
M2 = r0;
M3 = r0;
trace_buffer_start(p0,r0);
P0 = R1;
R0 = R1;
/* Turn off the icache */
p0.l = (IMEM_CONTROL & 0xFFFF);
p0.h = (IMEM_CONTROL >> 16);

2
arch/blackfin/mach-bf561/ints-priority.c
View File

@ -28,8 +28,8 @@
*/
#include <linux/module.h>
#include <linux/irq.h>
#include <asm/blackfin.h>
#include <asm/irq.h>
void program_IAR(void)
{

4
arch/blackfin/mach-common/Makefile
View File

@ -4,9 +4,9 @@
obj-y := \
cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \
interrupt.o lock.o dpmc.o irqpanic.o
interrupt.o lock.o irqpanic.o
obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o
obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM) += pm.o dpmc.o

89
arch/blackfin/mach-common/cacheinit.S
View File

@ -38,104 +38,37 @@
.text
#ifdef ANOMALY_05000125
#if defined(CONFIG_BLKFIN_CACHE)
ENTRY(_bfin_icache_init)
ENTRY(_bfin_write_IMEM_CONTROL)
/* Initialize Instruction CPLBS */
I0.L = (ICPLB_ADDR0 & 0xFFFF);
I0.H = (ICPLB_ADDR0 >> 16);
I1.L = (ICPLB_DATA0 & 0xFFFF);
I1.H = (ICPLB_DATA0 >> 16);
I2.L = _icplb_table;
I2.H = _icplb_table;
r1 = -1; /* end point comparison */
r3 = 15; /* max counter */
/* read entries from table */
.Lread_iaddr:
R0 = [I2++];
CC = R0 == R1;
IF CC JUMP .Lidone;
[I0++] = R0;
.Lread_idata:
R2 = [I2++];
[I1++] = R2;
R3 = R3 + R1;
CC = R3 == R1;
IF !CC JUMP .Lread_iaddr;
.Lidone:
/* Enable Instruction Cache */
P0.l = (IMEM_CONTROL & 0xFFFF);
P0.h = (IMEM_CONTROL >> 16);
R1 = [P0];
R0 = (IMC | ENICPLB);
R0 = R0 | R1;
/* Anomaly 05000125 */
CLI R2;
CLI R1;
SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
.align 8;
[P0] = R0;
SSYNC;
STI R2;
STI R1;
RTS;
ENDPROC(_bfin_icache_init)
ENDPROC(_bfin_write_IMEM_CONTROL)
#endif
#if defined(CONFIG_BLKFIN_DCACHE)
ENTRY(_bfin_dcache_init)
/* Initialize Data CPLBS */
I0.L = (DCPLB_ADDR0 & 0xFFFF);
I0.H = (DCPLB_ADDR0 >> 16);
I1.L = (DCPLB_DATA0 & 0xFFFF);
I1.H = (DCPLB_DATA0 >> 16);
I2.L = _dcplb_table;
I2.H = _dcplb_table;
R1 = -1; /* end point comparison */
R3 = 15; /* max counter */
/* read entries from table */
.Lread_daddr:
R0 = [I2++];
cc = R0 == R1;
IF CC JUMP .Lddone;
[I0++] = R0;
.Lread_ddata:
R2 = [I2++];
[I1++] = R2;
R3 = R3 + R1;
CC = R3 == R1;
IF !CC JUMP .Lread_daddr;
.Lddone:
P0.L = (DMEM_CONTROL & 0xFFFF);
P0.H = (DMEM_CONTROL >> 16);
R1 = [P0];
R0 = DMEM_CNTR;
R0 = R0 | R1;
/* Anomaly 05000125 */
CLI R2;
ENTRY(_bfin_write_DMEM_CONTROL)
CLI R1;
SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
.align 8;
[P0] = R0;
SSYNC;
STI R2;
STI R1;
RTS;
ENDPROC(_bfin_dcache_init)
ENDPROC(_bfin_write_DMEM_CONTROL)
#endif
#endif

13
arch/blackfin/mach-common/cplbinfo.c
View File

@ -31,11 +31,10 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/proc_fs.h>
#include <linux/uaccess.h>
#include <asm/current.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#include <asm/cplb.h>
#include <asm/blackfin.h>
@ -92,8 +91,7 @@ static char *cplb_print_entry(char *buf, int type)
} else
buf += sprintf(buf, "Data CPLB entry:\n");
buf += sprintf(buf, "Address\t\tData\tSize\tValid\tLocked\tSwapin\
\tiCount\toCount\n");
buf += sprintf(buf, "Address\t\tData\tSize\tValid\tLocked\tSwapin\n\tiCount\toCount\n");
while (*p_addr != 0xffffffff) {
entry = cplb_find_entry(cplb_addr, cplb_data, *p_addr, *p_data);
@ -144,8 +142,7 @@ static int cplbinfo_proc_output(char *buf)
p = buf;
p += sprintf(p,
"------------------ CPLB Information ------------------\n\n");
p += sprintf(p, "------------------ CPLB Information ------------------\n\n");
if (bfin_read_IMEM_CONTROL() & ENICPLB)
p = cplb_print_entry(p, CPLB_I);
@ -191,9 +188,9 @@ static int __init cplbinfo_init(void)
{
struct proc_dir_entry *entry;
if ((entry = create_proc_entry("cplbinfo", 0, NULL)) == NULL) {
entry = create_proc_entry("cplbinfo", 0, NULL);
if (!entry)
return -ENOMEM;
}
entry->read_proc = cplbinfo_read_proc;
entry->write_proc = cplbinfo_write_proc;

76
arch/blackfin/mach-common/entry.S
View File

@ -49,34 +49,15 @@
#include <linux/linkage.h>
#include <linux/unistd.h>
#include <asm/blackfin.h>
#include <asm/unistd.h>
#include <asm/errno.h>
#include <asm/thread_info.h> /* TIF_NEED_RESCHED */
#include <asm/asm-offsets.h>
#include <asm/trace.h>
#include <asm/mach-common/context.S>
#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
/*
* TODO: this should be proper save/restore, but for now
* we'll just cheat and use 0x1/0x13
*/
# define DEBUG_START_HWTRACE \
P5.l = LO(TBUFCTL); \
P5.h = HI(TBUFCTL); \
R7 = 0x13; \
[P5] = R7;
# define DEBUG_STOP_HWTRACE \
P5.l = LO(TBUFCTL); \
P5.h = HI(TBUFCTL); \
R7 = 0x01; \
[P5] = R7;
#else
# define DEBUG_START_HWTRACE
# define DEBUG_STOP_HWTRACE
#endif
#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
.section .l1.text
#else
@ -110,25 +91,14 @@ ENTRY(_ex_icplb)
ASTAT = [sp++];
SAVE_ALL_SYS
call __cplb_hdr;
DEBUG_START_HWTRACE
DEBUG_START_HWTRACE(p5, r7)
RESTORE_ALL_SYS
SP = RETN;
rtx;
ENDPROC(_ex_icplb)
ENTRY(_ex_spinlock)
/* Transform this into a syscall - twiddle the syscall vector. */
p5.l = lo(EVT15);
p5.h = hi(EVT15);
r7.l = _spinlock_bh;
r7.h = _spinlock_bh;
[p5] = r7;
csync;
/* Fall through. */
ENDPROC(_ex_spinlock)
ENTRY(_ex_syscall)
DEBUG_START_HWTRACE
DEBUG_START_HWTRACE(p5, r7)
(R7:6,P5:4) = [sp++];
ASTAT = [sp++];
raise 15; /* invoked by TRAP #0, for sys call */
@ -136,26 +106,6 @@ ENTRY(_ex_syscall)
rtx
ENDPROC(_ex_syscall)
ENTRY(_spinlock_bh)
SAVE_ALL_SYS
/* To end up here, vector 15 was changed - so we have to change it
* back.
*/
p0.l = lo(EVT15);
p0.h = hi(EVT15);
p1.l = _evt_system_call;
p1.h = _evt_system_call;
[p0] = p1;
csync;
r0 = [sp + PT_R0];
sp += -12;
call _sys_bfin_spinlock;
sp += 12;
[SP + PT_R0] = R0;
RESTORE_ALL_SYS
rti;
ENDPROC(_spinlock_bh)
ENTRY(_ex_soft_bp)
r7 = retx;
r7 += -2;
@ -186,7 +136,7 @@ ENTRY(_ex_single_step)
if !cc jump _ex_trap_c;
_return_from_exception:
DEBUG_START_HWTRACE
DEBUG_START_HWTRACE(p5, r7)
#ifdef ANOMALY_05000257
R7=LC0;
LC0=R7;
@ -208,7 +158,7 @@ ENTRY(_handle_bad_cplb)
* need to make a CPLB exception look like a normal exception
*/
DEBUG_START_HWTRACE
DEBUG_START_HWTRACE(p5, r7)
RESTORE_ALL_SYS
[--sp] = ASTAT;
[--sp] = (R7:6, P5:4);
@ -251,7 +201,7 @@ ENTRY(_ex_trap_c)
R6 = SEQSTAT;
[P5] = R6;
DEBUG_START_HWTRACE
DEBUG_START_HWTRACE(p5, r7)
(R7:6,P5:4) = [sp++];
ASTAT = [sp++];
SP = RETN;
@ -335,7 +285,7 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
/* Try to deal with syscalls quickly. */
[--sp] = ASTAT;
[--sp] = (R7:6, P5:4);
DEBUG_STOP_HWTRACE
DEBUG_STOP_HWTRACE(p5, r7)
r7 = SEQSTAT; /* reason code is in bit 5:0 */
r6.l = lo(SEQSTAT_EXCAUSE);
r6.h = hi(SEQSTAT_EXCAUSE);
@ -741,6 +691,10 @@ _schedule_and_signal_from_int:
r0 = [p0];
sti r0;
r0 = sp;
sp += -12;
call _finish_atomic_sections;
sp += 12;
jump.s .Lresume_userspace;
_schedule_and_signal:
@ -790,14 +744,14 @@ ENDPROC(_init_exception_buff)
ALIGN
_extable:
/* entry for each EXCAUSE[5:0]
* This table bmust be in sync with the table in ./kernel/traps.c
* This table must be in sync with the table in ./kernel/traps.c
* EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined
*/
.long _ex_syscall; /* 0x00 - User Defined - Linux Syscall */
.long _ex_soft_bp /* 0x01 - User Defined - Software breakpoint */
.long _ex_trap_c /* 0x02 - User Defined */
.long _ex_trap_c /* 0x03 - User Defined - Atomic test and set service */
.long _ex_spinlock /* 0x04 - User Defined */
.long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */
.long _ex_trap_c /* 0x04 - User Defined */
.long _ex_trap_c /* 0x05 - User Defined */
.long _ex_trap_c /* 0x06 - User Defined */
.long _ex_trap_c /* 0x07 - User Defined */

8
arch/blackfin/mach-common/interrupt.S
View File

@ -34,6 +34,7 @@
#include <linux/linkage.h>
#include <asm/entry.h>
#include <asm/asm-offsets.h>
#include <asm/trace.h>
#include <asm/mach-common/context.S>
@ -170,10 +171,9 @@ ENTRY(_evt_ivhw)
r7.l = W[p5];
1:
#endif
p0.l = lo(TBUFCTL);
p0.h = hi(TBUFCTL);
r0 = 1;
[p0] = r0;
trace_buffer_stop(p0, r0);
r0 = IRQ_HWERR;
r1 = sp;

5
arch/blackfin/mach-common/ints-priority-dc.c
View File

@ -371,6 +371,9 @@ int __init init_arch_irq(void)
bfin_write_SICA_IMASK1(SIC_UNMASK_ALL);
SSYNC();
bfin_write_SICA_IWR0(IWR_ENABLE_ALL);
bfin_write_SICA_IWR1(IWR_ENABLE_ALL);
local_irq_disable();
init_exception_buff();
@ -393,7 +396,7 @@ int __init init_arch_irq(void)
bfin_write_EVT15(evt_system_call);
CSYNC();
for (irq = 0; irq < SYS_IRQS; irq++) {
for (irq = 0; irq <= SYS_IRQS; irq++) {
if (irq <= IRQ_CORETMR)
set_irq_chip(irq, &bf561_core_irqchip);
else

393
arch/blackfin/mach-common/ints-priority-sc.c
View File

@ -13,7 +13,7 @@
* 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
* 2003 Metrowerks/Motorola
* 2003 Bas Vermeulen <bas@buyways.nl>
* Copyright 2004-2006 Analog Devices Inc.
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
@ -65,9 +65,9 @@ atomic_t num_spurious;
struct ivgx {
/* irq number for request_irq, available in mach-bf533/irq.h */
int irqno;
unsigned int irqno;
/* corresponding bit in the SIC_ISR register */
int isrflag;
unsigned int isrflag;
} ivg_table[NR_PERI_INTS];
struct ivg_slice {
@ -88,8 +88,7 @@ static void __init search_IAR(void)
for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
int irqn;
ivg7_13[ivg].istop = ivg7_13[ivg].ifirst =
&ivg_table[irq_pos];
ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
int iar_shift = (irqn & 7) * 4;
@ -98,7 +97,7 @@ static void __init search_IAR(void)
bfin_read32((unsigned long *)SIC_IAR0 +
(irqn >> 3)) >> iar_shift)) {
ivg_table[irq_pos].irqno = IVG7 + irqn;
ivg_table[irq_pos].isrflag = 1 << irqn;
ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
ivg7_13[ivg].istop++;
irq_pos++;
}
@ -141,15 +140,31 @@ static void bfin_core_unmask_irq(unsigned int irq)
static void bfin_internal_mask_irq(unsigned int irq)
{
#ifndef CONFIG_BF54x
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
~(1 << (irq - (IRQ_CORETMR + 1))));
#else
unsigned mask_bank, mask_bit;
mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
~(1 << mask_bit));
#endif
SSYNC();
}
static void bfin_internal_unmask_irq(unsigned int irq)
{
#ifndef CONFIG_BF54x
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
(1 << (irq - (IRQ_CORETMR + 1))));
#else
unsigned mask_bank, mask_bit;
mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
(1 << mask_bit));
#endif
SSYNC();
}
@ -279,11 +294,10 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
" INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
__FUNCTION__, __FILE__, __LINE__);
}
#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && !defined(CONFIG_BF54x)
static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
@ -361,8 +375,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
}
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
{
IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
ret = gpio_request(gpionr, NULL);
if (ret)
@ -407,7 +420,6 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
return 0;
}
static struct irq_chip bfin_gpio_irqchip = {
.ack = bfin_gpio_ack_irq,
.mask = bfin_gpio_mask_irq,
@ -422,17 +434,17 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
struct irq_desc *intb_desc)
{
u16 i;
struct irq_desc *desc;
for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
int irq = IRQ_PF0 + i;
int flag_d = get_gpiop_data(i);
int mask =
flag_d & (gpio_enabled[gpio_bank(i)] &
get_gpiop_maska(i));
flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i));
while (mask) {
if (mask & 1) {
struct irq_desc *desc = irq_desc + irq;
desc = irq_desc + irq;
desc->handle_irq(irq, desc);
}
irq++;
@ -441,6 +453,264 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
}
}
#else /* CONFIG_IRQCHIP_DEMUX_GPIO */
#define NR_PINT_SYS_IRQS 4
#define NR_PINT_BITS 32
#define NR_PINTS 160
#define IRQ_NOT_AVAIL 0xFF
#define PINT_2_BANK(x) ((x) >> 5)
#define PINT_2_BIT(x) ((x) & 0x1F)
#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
static unsigned char irq2pint_lut[NR_PINTS];
static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
struct pin_int_t {
unsigned int mask_set;
unsigned int mask_clear;
unsigned int request;
unsigned int assign;
unsigned int edge_set;
unsigned int edge_clear;
unsigned int invert_set;
unsigned int invert_clear;
unsigned int pinstate;
unsigned int latch;
};
static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
(struct pin_int_t *)PINT0_MASK_SET,
(struct pin_int_t *)PINT1_MASK_SET,
(struct pin_int_t *)PINT2_MASK_SET,
(struct pin_int_t *)PINT3_MASK_SET,
};
unsigned short get_irq_base(u8 bank, u8 bmap)
{
u16 irq_base;
if (bank < 2) { /*PA-PB */
irq_base = IRQ_PA0 + bmap * 16;
} else { /*PC-PJ */
irq_base = IRQ_PC0 + bmap * 16;
}
return irq_base;
}
/* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
void init_pint_lut(void)
{
u16 bank, bit, irq_base, bit_pos;
u32 pint_assign;
u8 bmap;
memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
pint_assign = pint[bank]->assign;
for (bit = 0; bit < NR_PINT_BITS; bit++) {
bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
irq_base = get_irq_base(bank, bmap);
irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
bit_pos = bit + bank * NR_PINT_BITS;
pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
}
}
}
static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
static void bfin_gpio_ack_irq(unsigned int irq)
{
u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val);
SSYNC();
}
static void bfin_gpio_mask_ack_irq(unsigned int irq)
{
u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
u32 pintbit = PINT_BIT(pint_val);
u8 bank = PINT_2_BANK(pint_val);
pint[bank]->request = pintbit;
pint[bank]->mask_clear = pintbit;
SSYNC();
}
static void bfin_gpio_mask_irq(unsigned int irq)
{
u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
SSYNC();
}
static void bfin_gpio_unmask_irq(unsigned int irq)
{
u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
u32 pintbit = PINT_BIT(pint_val);
u8 bank = PINT_2_BANK(pint_val);
pint[bank]->request = pintbit;
pint[bank]->mask_set = pintbit;
SSYNC();
}
static unsigned int bfin_gpio_irq_startup(unsigned int irq)
{
unsigned int ret;
u16 gpionr = irq - IRQ_PA0;
u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
if (pint_val == IRQ_NOT_AVAIL)
return -ENODEV;
if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
ret = gpio_request(gpionr, NULL);
if (ret)
return ret;
}
gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
bfin_gpio_unmask_irq(irq);
return ret;
}
static void bfin_gpio_irq_shutdown(unsigned int irq)
{
bfin_gpio_mask_irq(irq);
gpio_free(irq - IRQ_PA0);
gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0);
}
static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
{
unsigned int ret;
u16 gpionr = irq - IRQ_PA0;
u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
u32 pintbit = PINT_BIT(pint_val);
u8 bank = PINT_2_BANK(pint_val);
if (pint_val == IRQ_NOT_AVAIL)
return -ENODEV;
if (type == IRQ_TYPE_PROBE) {
/* only probe unenabled GPIO interrupt lines */
if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
return 0;
type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
ret = gpio_request(gpionr, NULL);
if (ret)
return ret;
}
gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
} else {
gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
return 0;
}
gpio_direction_input(gpionr);
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
pint[bank]->edge_set = pintbit;
} else {
pint[bank]->edge_clear = pintbit;
}
if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
else
pint[bank]->invert_set = pintbit; /* high or rising edge denoted by zero */
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
pint[bank]->invert_set = pintbit;
else
pint[bank]->invert_set = pintbit;
SSYNC();
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
set_irq_handler(irq, handle_edge_irq);
else
set_irq_handler(irq, handle_level_irq);
return 0;
}
static struct irq_chip bfin_gpio_irqchip = {
.ack = bfin_gpio_ack_irq,
.mask = bfin_gpio_mask_irq,
.mask_ack = bfin_gpio_mask_ack_irq,
.unmask = bfin_gpio_unmask_irq,
.set_type = bfin_gpio_irq_type,
.startup = bfin_gpio_irq_startup,
.shutdown = bfin_gpio_irq_shutdown
};
static void bfin_demux_gpio_irq(unsigned int intb_irq,
struct irq_desc *intb_desc)
{
u8 bank, pint_val;
u32 request, irq;
struct irq_desc *desc;
switch (intb_irq) {
case IRQ_PINT0:
bank = 0;
break;
case IRQ_PINT2:
bank = 2;
break;
case IRQ_PINT3:
bank = 3;
break;
case IRQ_PINT1:
bank = 1;
break;
default:
return;
}
pint_val = bank * NR_PINT_BITS;
request = pint[bank]->request;
while (request) {
if (request & 1) {
irq = pint2irq_lut[pint_val] + SYS_IRQS;
desc = irq_desc + irq;
desc->handle_irq(irq, desc);
}
pint_val++;
request >>= 1;
}
}
#endif /* CONFIG_IRQCHIP_DEMUX_GPIO */
/*
@ -452,7 +722,18 @@ int __init init_arch_irq(void)
int irq;
unsigned long ilat = 0;
/* Disable all the peripheral intrs - page 4-29 HW Ref manual */
#ifdef CONFIG_BF54x
bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
#else
bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
bfin_write_SIC_IWR(IWR_ENABLE_ALL);
#endif
SSYNC();
local_irq_disable();
@ -475,7 +756,18 @@ int __init init_arch_irq(void)
bfin_write_EVT15(evt_system_call);
CSYNC();
for (irq = 0; irq < SYS_IRQS; irq++) {
#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && defined(CONFIG_BF54x)
#ifdef CONFIG_PINTx_REASSIGN
pint[0]->assign = CONFIG_PINT0_ASSIGN;
pint[1]->assign = CONFIG_PINT1_ASSIGN;
pint[2]->assign = CONFIG_PINT2_ASSIGN;
pint[3]->assign = CONFIG_PINT3_ASSIGN;
#endif
/* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
init_pint_lut();
#endif
for (irq = 0; irq <= SYS_IRQS; irq++) {
if (irq <= IRQ_CORETMR)
set_irq_chip(irq, &bfin_core_irqchip);
else
@ -484,20 +776,42 @@ int __init init_arch_irq(void)
if (irq != IRQ_GENERIC_ERROR) {
#endif
switch (irq) {
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
if ((irq != IRQ_PROG_INTA) /*PORT F & G MASK_A Interrupt*/
# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
&& (irq != IRQ_MAC_RX) /*PORT H MASK_A Interrupt*/
# endif
) {
#endif
set_irq_handler(irq, handle_simple_irq);
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
} else {
#ifndef CONFIG_BF54x
case IRQ_PROG_INTA:
set_irq_chained_handler(irq,
bfin_demux_gpio_irq);
}
break;
#if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
case IRQ_MAC_RX:
set_irq_chained_handler(irq,
bfin_demux_gpio_irq);
break;
#endif
#else
case IRQ_PINT0:
set_irq_chained_handler(irq,
bfin_demux_gpio_irq);
break;
case IRQ_PINT1:
set_irq_chained_handler(irq,
bfin_demux_gpio_irq);
break;
case IRQ_PINT2:
set_irq_chained_handler(irq,
bfin_demux_gpio_irq);
break;
case IRQ_PINT3:
set_irq_chained_handler(irq,
bfin_demux_gpio_irq);
break;
#endif /*CONFIG_BF54x */
#endif
default:
set_irq_handler(irq, handle_simple_irq);
break;
}
#ifdef BF537_GENERIC_ERROR_INT_DEMUX
} else {
@ -513,7 +827,11 @@ int __init init_arch_irq(void)
#endif
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
#ifndef CONFIG_BF54x
for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
#else
for (irq = IRQ_PA0; irq < NR_IRQS; irq++) {
#endif
set_irq_chip(irq, &bfin_gpio_irqchip);
/* if configured as edge, then will be changed to do_edge_IRQ */
set_irq_handler(irq, handle_level_irq);
@ -526,8 +844,7 @@ int __init init_arch_irq(void)
bfin_write_ILAT(ilat);
CSYNC();
printk(KERN_INFO
"Configuring Blackfin Priority Driven Interrupts\n");
printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
/* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
* local_irq_enable()
*/
@ -538,8 +855,7 @@ int __init init_arch_irq(void)
/* Enable interrupts IVG7-15 */
irq_flags = irq_flags | IMASK_IVG15 |
IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 |
IMASK_IVGHW;
IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
return 0;
}
@ -555,8 +871,24 @@ void do_irq(int vec, struct pt_regs *fp)
} else {
struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
unsigned long sic_status;
#ifdef CONFIG_BF54x
unsigned long sic_status[3];
SSYNC();
sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
for (;; ivg++) {
if (ivg >= ivg_stop) {
atomic_inc(&num_spurious);
return;
}
if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
break;
}
#else
unsigned long sic_status;
SSYNC();
sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
@ -567,6 +899,7 @@ void do_irq(int vec, struct pt_regs *fp)
} else if (sic_status & ivg->isrflag)
break;
}
#endif
vec = ivg->irqno;
}
asm_do_IRQ(vec, fp);

4
arch/blackfin/mach-common/pm.c
View File

@ -35,10 +35,10 @@
#include <linux/pm.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <asm/io.h>
#include <asm/dpmc.h>
#include <asm/irq.h>
#include <asm/gpio.h>
#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H

47
arch/blackfin/mm/init.c
View File

@ -29,8 +29,8 @@
#include <linux/swap.h>
#include <linux/bootmem.h>
#include <linux/uaccess.h>
#include <asm/bfin-global.h>
#include <asm/uaccess.h>
#include <asm/l1layout.h>
#include "blackfin_sram.h"
@ -168,42 +168,31 @@ void __init mem_init(void)
}
}
static __init void free_init_pages(const char *what, unsigned long begin, unsigned long end)
{
unsigned long addr;
/* next to check that the page we free is not a partial page */
for (addr = begin; addr + PAGE_SIZE <= end; addr += PAGE_SIZE) {
ClearPageReserved(virt_to_page(addr));
init_page_count(virt_to_page(addr));
free_page(addr);
totalram_pages++;
}
printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
}
#ifdef CONFIG_BLK_DEV_INITRD
void __init free_initrd_mem(unsigned long start, unsigned long end)
{
int pages = 0;
for (; start < end; start += PAGE_SIZE) {
ClearPageReserved(virt_to_page(start));
init_page_count(virt_to_page(start));
free_page(start);
totalram_pages++;
pages++;
}
printk(KERN_NOTICE "Freeing initrd memory: %dk freed\n", pages);
free_init_pages("initrd memory", start, end);
}
#endif
void __init free_initmem(void)
{
#ifdef CONFIG_RAMKERNEL
unsigned long addr;
/*
* the following code should be cool even if these sections
* are not page aligned.
*/
addr = PAGE_ALIGN((unsigned long)(__init_begin));
/* next to check that the page we free is not a partial page */
for (; addr + PAGE_SIZE < (unsigned long)(__init_end);
addr += PAGE_SIZE) {
ClearPageReserved(virt_to_page(addr));
init_page_count(virt_to_page(addr));
free_page(addr);
totalram_pages++;
}
printk(KERN_NOTICE
"Freeing unused kernel memory: %ldk freed (0x%x - 0x%x)\n",
(addr - PAGE_ALIGN((long)__init_begin)) >> 10,
(int)(PAGE_ALIGN((unsigned long)(__init_begin))),
(int)(addr - PAGE_SIZE));
free_init_pages("unused kernel memory",
(unsigned long)(&__init_begin),
(unsigned long)(&__init_end));
#endif
}

6
arch/blackfin/oprofile/common.c
View File

@ -33,12 +33,12 @@
#include <linux/smp.h>
#include <linux/errno.h>
#include <linux/mutex.h>
#include <linux/ptrace.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/blackfin.h>
#include <asm/irq.h>
#include <asm/io.h>
#include "op_blackfin.h"

6
arch/blackfin/oprofile/op_model_bf533.c
View File

@ -32,12 +32,12 @@
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <asm/ptrace.h>
#include <linux/ptrace.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/system.h>
#include <asm/processor.h>
#include <asm/blackfin.h>
#include <asm/irq.h>
#include <asm/io.h>
#include "op_blackfin.h"

3
arch/blackfin/oprofile/timer_int.c
View File

@ -31,8 +31,7 @@
#include <linux/smp.h>
#include <linux/irq.h>
#include <linux/oprofile.h>
#include <asm/ptrace.h>
#include <linux/ptrace.h>
static void enable_sys_timer0()
{

2
drivers/net/Kconfig
View File

@ -877,7 +877,7 @@ config NET_NETX
config DM9000
tristate "DM9000 support"
depends on ARM || MIPS
depends on ARM || BLACKFIN || MIPS
select CRC32
select MII
---help---

17
drivers/net/dm9000.c
View File

@ -104,6 +104,18 @@
#define PRINTK(args...) printk(KERN_DEBUG args)
#endif
#ifdef CONFIG_BLACKFIN
#define readsb insb
#define readsw insw
#define readsl insl
#define writesb outsb
#define writesw outsw
#define writesl outsl
#define DM9000_IRQ_FLAGS (IRQF_SHARED | IRQF_TRIGGER_HIGH)
#else
#define DM9000_IRQ_FLAGS IRQF_SHARED
#endif
/*
* Transmit timeout, default 5 seconds.
*/
@ -431,6 +443,9 @@ dm9000_probe(struct platform_device *pdev)
db->io_addr = (void __iomem *)base;
db->io_data = (void __iomem *)(base + 4);
/* ensure at least we have a default set of IO routines */
dm9000_set_io(db, 2);
} else {
db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
@ -614,7 +629,7 @@ dm9000_open(struct net_device *dev)
PRINTK2("entering dm9000_open\n");
if (request_irq(dev->irq, &dm9000_interrupt, IRQF_SHARED, dev->name, dev))
if (request_irq(dev->irq, &dm9000_interrupt, DM9000_IRQ_FLAGS, dev->name, dev))
return -EAGAIN;
/* Initialize DM9000 board */

48
drivers/serial/Kconfig
View File

@ -556,7 +556,7 @@ choice
config SERIAL_BFIN_DMA
bool "DMA mode"
depends on DMA_UNCACHED_1M
depends on DMA_UNCACHED_1M && !KGDB_UART
help
This driver works under DMA mode. If this option is selected, the
blackfin simple dma driver is also enabled.
@ -599,7 +599,7 @@ config UART0_RTS_PIN
config SERIAL_BFIN_UART1
bool "Enable UART1"
depends on SERIAL_BFIN && (BF534 || BF536 || BF537)
depends on SERIAL_BFIN && (BF534 || BF536 || BF537 || BF54x)
help
Enable UART1
@ -612,18 +612,58 @@ config BFIN_UART1_CTSRTS
config UART1_CTS_PIN
int "UART1 CTS pin"
depends on BFIN_UART1_CTSRTS
depends on BFIN_UART1_CTSRTS && (BF53x || BF561)
default -1
help
Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
config UART1_RTS_PIN
int "UART1 RTS pin"
depends on BFIN_UART1_CTSRTS
depends on BFIN_UART1_CTSRTS && (BF53x || BF561)
default -1
help
Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
config SERIAL_BFIN_UART2
bool "Enable UART2"
depends on SERIAL_BFIN && (BF54x)
help
Enable UART2
config BFIN_UART2_CTSRTS
bool "Enable UART2 hardware flow control"
depends on SERIAL_BFIN_UART2
help
Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS
signal.
config UART2_CTS_PIN
int "UART2 CTS pin"
depends on BFIN_UART2_CTSRTS
default -1
help
Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
config UART2_RTS_PIN
int "UART2 RTS pin"
depends on BFIN_UART2_CTSRTS
default -1
help
Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
config SERIAL_BFIN_UART3
bool "Enable UART3"
depends on SERIAL_BFIN && (BF54x)
help
Enable UART3
config BFIN_UART3_CTSRTS
bool "Enable UART3 hardware flow control"
depends on SERIAL_BFIN_UART3
help
Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS
signal.
config SERIAL_IMX
bool "IMX serial port support"
depends on ARM && ARCH_IMX

182
drivers/serial/bfin_5xx.c
View File

@ -41,6 +41,11 @@
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#ifdef CONFIG_KGDB_UART
#include <linux/kgdb.h>
#include <asm/irq_regs.h>
#endif
#include <asm/gpio.h>
#include <asm/mach/bfin_serial_5xx.h>
@ -81,8 +86,21 @@ static void bfin_serial_stop_tx(struct uart_port *port)
{
struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
#ifdef CONFIG_BF54x
while (!(UART_GET_LSR(uart) & TEMT))
continue;
#endif
#ifdef CONFIG_SERIAL_BFIN_DMA
disable_dma(uart->tx_dma_channel);
#else
#ifdef CONFIG_BF54x
/* Waiting for Transmission Finished */
while (!(UART_GET_LSR(uart) & TFI))
continue;
/* Clear TFI bit */
UART_PUT_LSR(uart, TFI);
UART_CLEAR_IER(uart, ETBEI);
#else
unsigned short ier;
@ -90,6 +108,7 @@ static void bfin_serial_stop_tx(struct uart_port *port)
ier &= ~ETBEI;
UART_PUT_IER(uart, ier);
#endif
#endif
}
/*
@ -101,6 +120,9 @@ static void bfin_serial_start_tx(struct uart_port *port)
#ifdef CONFIG_SERIAL_BFIN_DMA
bfin_serial_dma_tx_chars(uart);
#else
#ifdef CONFIG_BF54x
UART_SET_IER(uart, ETBEI);
#else
unsigned short ier;
ier = UART_GET_IER(uart);
@ -108,6 +130,7 @@ static void bfin_serial_start_tx(struct uart_port *port)
UART_PUT_IER(uart, ier);
bfin_serial_tx_chars(uart);
#endif
#endif
}
/*
@ -116,11 +139,18 @@ static void bfin_serial_start_tx(struct uart_port *port)
static void bfin_serial_stop_rx(struct uart_port *port)
{
struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
#ifdef CONFIG_BF54x
UART_CLEAR_IER(uart, ERBFI);
#else
unsigned short ier;
ier = UART_GET_IER(uart);
#ifdef CONFIG_KGDB_UART
if (uart->port.line != CONFIG_KGDB_UART_PORT)
#endif
ier &= ~ERBFI;
UART_PUT_IER(uart, ier);
#endif
}
/*
@ -130,6 +160,49 @@ static void bfin_serial_enable_ms(struct uart_port *port)
{
}
#ifdef CONFIG_KGDB_UART
static int kgdb_entry_state;
void kgdb_put_debug_char(int chr)
{
struct bfin_serial_port *uart;
if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS)
uart = &bfin_serial_ports[0];
else
uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
while (!(UART_GET_LSR(uart) & THRE)) {
__builtin_bfin_ssync();
}
UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
__builtin_bfin_ssync();
UART_PUT_CHAR(uart, (unsigned char)chr);
__builtin_bfin_ssync();
}
int kgdb_get_debug_char(void)
{
struct bfin_serial_port *uart;
unsigned char chr;
if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS)
uart = &bfin_serial_ports[0];
else
uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
while(!(UART_GET_LSR(uart) & DR)) {
__builtin_bfin_ssync();
}
UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
__builtin_bfin_ssync();
chr = UART_GET_CHAR(uart);
__builtin_bfin_ssync();
return chr;
}
#endif
#ifdef CONFIG_SERIAL_BFIN_PIO
static void local_put_char(struct bfin_serial_port *uart, char ch)
{
@ -152,6 +225,9 @@ static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
{
struct tty_struct *tty = uart->port.info->tty;
unsigned int status, ch, flg;
#ifdef CONFIG_KGDB_UART
struct pt_regs *regs = get_irq_regs();
#endif
#ifdef BF533_FAMILY
static int in_break = 0;
#endif
@ -160,6 +236,27 @@ static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
ch = UART_GET_CHAR(uart);
uart->port.icount.rx++;
#ifdef CONFIG_KGDB_UART
if (uart->port.line == CONFIG_KGDB_UART_PORT) {
if (uart->port.cons->index == CONFIG_KGDB_UART_PORT && ch == 0x1) { /* Ctrl + A */
kgdb_breakkey_pressed(regs);
return;
} else if (kgdb_entry_state == 0 && ch == '$') {/* connection from KGDB */
kgdb_entry_state = 1;
} else if (kgdb_entry_state == 1 && ch == 'q') {
kgdb_entry_state = 0;
kgdb_breakkey_pressed(regs);
return;
} else if (ch == 0x3) {/* Ctrl + C */
kgdb_entry_state = 0;
kgdb_breakkey_pressed(regs);
return;
} else {
kgdb_entry_state = 0;
}
}
#endif
#ifdef BF533_FAMILY
/* The BF533 family of processors have a nice misbehavior where
* they continuously generate characters for a "single" break.
@ -250,10 +347,21 @@ static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
{
struct bfin_serial_port *uart = dev_id;
#ifdef CONFIG_BF54x
unsigned short status;
spin_lock(&uart->port.lock);
status = UART_GET_LSR(uart);
while ((UART_GET_IER(uart) & ERBFI) && (status & DR)) {
bfin_serial_rx_chars(uart);
status = UART_GET_LSR(uart);
}
spin_unlock(&uart->port.lock);
#else
spin_lock(&uart->port.lock);
while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_RX_READY)
bfin_serial_rx_chars(uart);
spin_unlock(&uart->port.lock);
#endif
return IRQ_HANDLED;
}
@ -261,10 +369,21 @@ static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
{
struct bfin_serial_port *uart = dev_id;
#ifdef CONFIG_BF54x
unsigned short status;
spin_lock(&uart->port.lock);
status = UART_GET_LSR(uart);
while ((UART_GET_IER(uart) & ETBEI) && (status & THRE)) {
bfin_serial_tx_chars(uart);
status = UART_GET_LSR(uart);
}
spin_unlock(&uart->port.lock);
#else
spin_lock(&uart->port.lock);
while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_TX_READY)
bfin_serial_tx_chars(uart);
spin_unlock(&uart->port.lock);
#endif
return IRQ_HANDLED;
}
@ -275,7 +394,6 @@ static void bfin_serial_do_work(struct work_struct *work)
bfin_serial_mctrl_check(uart);
}
#endif
#ifdef CONFIG_SERIAL_BFIN_DMA
@ -324,9 +442,13 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
set_dma_x_modify(uart->tx_dma_channel, 1);
enable_dma(uart->tx_dma_channel);
#ifdef CONFIG_BF54x
UART_SET_IER(uart, ETBEI);
#else
ier = UART_GET_IER(uart);
ier |= ETBEI;
UART_PUT_IER(uart, ier);
#endif
spin_unlock_irqrestore(&uart->port.lock, flags);
}
@ -406,9 +528,13 @@ static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
clear_dma_irqstat(uart->tx_dma_channel);
disable_dma(uart->tx_dma_channel);
#ifdef CONFIG_BF54x
UART_CLEAR_IER(uart, ETBEI);
#else
ier = UART_GET_IER(uart);
ier &= ~ETBEI;
UART_PUT_IER(uart, ier);
#endif
xmit->tail = (xmit->tail+uart->tx_count) &(UART_XMIT_SIZE -1);
uart->port.icount.tx+=uart->tx_count;
@ -570,8 +696,12 @@ static int bfin_serial_startup(struct uart_port *port)
uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
add_timer(&(uart->rx_dma_timer));
#else
# ifdef CONFIG_KGDB_UART
if (uart->port.line != CONFIG_KGDB_UART_PORT && request_irq
# else
if (request_irq
# endif
(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
"BFIN_UART_RX", uart)) {
printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
@ -586,7 +716,11 @@ static int bfin_serial_startup(struct uart_port *port)
return -EBUSY;
}
#endif
#ifdef CONFIG_BF54x
UART_SET_IER(uart, ERBFI);
#else
UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
#endif
return 0;
}
@ -601,6 +735,9 @@ static void bfin_serial_shutdown(struct uart_port *port)
free_dma(uart->rx_dma_channel);
del_timer(&(uart->rx_dma_timer));
#else
#ifdef CONFIG_KGDB_UART
if (uart->port.line != CONFIG_KGDB_UART_PORT)
#endif
free_irq(uart->port.irq, uart);
free_irq(uart->port.irq+1, uart);
#endif
@ -674,29 +811,41 @@ bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
/* Disable UART */
ier = UART_GET_IER(uart);
#ifdef CONFIG_BF54x
UART_CLEAR_IER(uart, 0xF);
#else
UART_PUT_IER(uart, 0);
#endif
#ifndef CONFIG_BF54x
/* Set DLAB in LCR to Access DLL and DLH */
val = UART_GET_LCR(uart);
val |= DLAB;
UART_PUT_LCR(uart, val);
SSYNC();
#endif
UART_PUT_DLL(uart, quot & 0xFF);
SSYNC();
UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
SSYNC();
#ifndef CONFIG_BF54x
/* Clear DLAB in LCR to Access THR RBR IER */
val = UART_GET_LCR(uart);
val &= ~DLAB;
UART_PUT_LCR(uart, val);
SSYNC();
#endif
UART_PUT_LCR(uart, lcr);
/* Enable UART */
#ifdef CONFIG_BF54x
UART_SET_IER(uart, ier);
#else
UART_PUT_IER(uart, ier);
#endif
val = UART_GET_GCTL(uart);
val |= UCEN;
@ -808,15 +957,15 @@ static void __init bfin_serial_init_ports(void)
bfin_serial_resource[i].uart_rts_pin;
#endif
bfin_serial_hw_init(&bfin_serial_ports[i]);
}
}
#ifdef CONFIG_SERIAL_BFIN_CONSOLE
static void bfin_serial_console_putchar(struct uart_port *port, int ch)
{
struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
while (!(UART_GET_LSR(uart)))
while (!(UART_GET_LSR(uart) & THRE))
barrier();
UART_PUT_CHAR(uart, ch);
SSYNC();
@ -868,18 +1017,22 @@ bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
case 2: *bits = 7; break;
case 3: *bits = 8; break;
}
#ifndef CONFIG_BF54x
/* Set DLAB in LCR to Access DLL and DLH */
val = UART_GET_LCR(uart);
val |= DLAB;
UART_PUT_LCR(uart, val);
#endif
dll = UART_GET_DLL(uart);
dlh = UART_GET_DLH(uart);
#ifndef CONFIG_BF54x
/* Clear DLAB in LCR to Access THR RBR IER */
val = UART_GET_LCR(uart);
val &= ~DLAB;
UART_PUT_LCR(uart, val);
#endif
*baud = get_sclk() / (16*(dll | dlh << 8));
}
@ -931,6 +1084,10 @@ static int __init bfin_serial_rs_console_init(void)
{
bfin_serial_init_ports();
register_console(&bfin_serial_console);
#ifdef CONFIG_KGDB_UART
kgdb_entry_state = 0;
init_kgdb_uart();
#endif
return 0;
}
console_initcall(bfin_serial_rs_console_init);
@ -1023,6 +1180,10 @@ static struct platform_driver bfin_serial_driver = {
static int __init bfin_serial_init(void)
{
int ret;
#ifdef CONFIG_KGDB_UART
struct bfin_serial_port *uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
struct termios t;
#endif
pr_info("Serial: Blackfin serial driver\n");
@ -1036,6 +1197,21 @@ static int __init bfin_serial_init(void)
uart_unregister_driver(&bfin_serial_reg);
}
}
#ifdef CONFIG_KGDB_UART
if (uart->port.cons->index != CONFIG_KGDB_UART_PORT) {
request_irq(uart->port.irq, bfin_serial_int,
IRQF_DISABLED, "BFIN_UART_RX", uart);
pr_info("Request irq for kgdb uart port\n");
UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
__builtin_bfin_ssync();
t.c_cflag = CS8|B57600;
t.c_iflag = 0;
t.c_oflag = 0;
t.c_lflag = ICANON;
t.c_line = CONFIG_KGDB_UART_PORT;
bfin_serial_set_termios(&uart->port, &t, &t);
}
#endif
return ret;
}

2
drivers/video/console/Kconfig
View File

@ -6,7 +6,7 @@ menu "Console display driver support"
config VGA_CONSOLE
bool "VGA text console" if EMBEDDED || !X86
depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH
depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BFIN
default y
help
Saying Y here will allow you to use Linux in text mode through a

2
include/asm-blackfin/Kbuild
View File

@ -1 +1,3 @@
include include/asm-generic/Kbuild.asm
header-y += fixed_code.h

12
include/asm-blackfin/bfin-global.h
View File

@ -67,6 +67,18 @@ extern void evt14_softirq(void);
extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type);
extern asmlinkage void finish_atomic_sections (struct pt_regs *regs);
extern char fixed_code_start;
extern char fixed_code_end;
extern int atomic_xchg32(void);
extern int atomic_cas32(void);
extern int atomic_add32(void);
extern int atomic_sub32(void);
extern int atomic_ior32(void);
extern int atomic_and32(void);
extern int atomic_xor32(void);
extern void sigreturn_stub(void);
extern void *l1_data_A_sram_alloc(size_t);
extern void *l1_data_B_sram_alloc(size_t);
extern void *l1_inst_sram_alloc(size_t);

133
include/asm-blackfin/cplbinit.h
View File

@ -57,8 +57,8 @@ struct cplb_tab {
u16 size;
};
u_long icplb_table[MAX_CPLBS+1];
u_long dcplb_table[MAX_CPLBS+1];
extern u_long icplb_table[MAX_CPLBS+1];
extern u_long dcplb_table[MAX_CPLBS+1];
/* Till here we are discussing about the static memory management model.
* However, the operating envoronments commonly define more CPLB
@ -70,134 +70,27 @@ u_long dcplb_table[MAX_CPLBS+1];
*/
#ifdef CONFIG_CPLB_SWITCH_TAB_L1
u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
#ifdef CONFIG_CPLB_INFO
u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
#endif /* CONFIG_CPLB_INFO */
#else
u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
#ifdef CONFIG_CPLB_INFO
u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
#endif /* CONFIG_CPLB_INFO */
#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
struct s_cplb {
struct cplb_tab init_i;
struct cplb_tab init_d;
struct cplb_tab switch_i;
struct cplb_tab switch_d;
};
extern unsigned long reserved_mem_dcache_on;
extern unsigned long reserved_mem_icache_on;
#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
static struct cplb_desc cplb_data[] = {
{
.start = 0,
.end = SIZE_4K,
.psize = SIZE_4K,
.attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
.i_conf = SDRAM_OOPS,
.d_conf = SDRAM_OOPS,
#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
.valid = 1,
#else
.valid = 0,
#endif
.name = "ZERO Pointer Saveguard",
},
{
.start = L1_CODE_START,
.end = L1_CODE_START + L1_CODE_LENGTH,
.psize = SIZE_4M,
.attr = INITIAL_T | SWITCH_T | I_CPLB,
.i_conf = L1_IMEMORY,
.d_conf = 0,
.valid = 1,
.name = "L1 I-Memory",
},
{
.start = L1_DATA_A_START,
.end = L1_DATA_B_START + L1_DATA_B_LENGTH,
.psize = SIZE_4M,
.attr = INITIAL_T | SWITCH_T | D_CPLB,
.i_conf = 0,
.d_conf = L1_DMEMORY,
#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
.valid = 1,
#else
.valid = 0,
#endif
.name = "L1 D-Memory",
},
{
.start = 0,
.end = 0, /* dynamic */
.psize = 0,
.attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
.i_conf = SDRAM_IGENERIC,
.d_conf = SDRAM_DGENERIC,
.valid = 1,
.name = "SDRAM Kernel",
},
{
.start = 0, /* dynamic */
.end = 0, /* dynamic */
.psize = 0,
.attr = INITIAL_T | SWITCH_T | D_CPLB,
.i_conf = SDRAM_IGENERIC,
.d_conf = SDRAM_DNON_CHBL,
.valid = 1,
.name = "SDRAM RAM MTD",
},
{
.start = 0, /* dynamic */
.end = 0, /* dynamic */
.psize = SIZE_1M,
.attr = INITIAL_T | SWITCH_T | D_CPLB,
.d_conf = SDRAM_DNON_CHBL,
.valid = 1,//(DMA_UNCACHED_REGION > 0),
.name = "SDRAM Uncached DMA ZONE",
},
{
.start = 0, /* dynamic */
.end = 0, /* dynamic */
.psize = 0,
.attr = SWITCH_T | D_CPLB,
.i_conf = 0, /* dynamic */
.d_conf = 0, /* dynamic */
.valid = 1,
.name = "SDRAM Reserved Memory",
},
{
.start = ASYNC_BANK0_BASE,
.end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
.psize = 0,
.attr = SWITCH_T | D_CPLB,
.d_conf = SDRAM_EBIU,
.valid = 1,
.name = "ASYNC Memory",
},
{
#if defined(CONFIG_BF561)
.start = L2_SRAM,
.end = L2_SRAM_END,
.psize = SIZE_1M,
.attr = SWITCH_T | D_CPLB,
.i_conf = L2_MEMORY,
.d_conf = L2_MEMORY,
.valid = 1,
#else
.valid = 0,
#endif
.name = "L2 Memory",
}
};
#endif
extern void generate_cpl_tables(void);

20
include/asm-blackfin/fixed_code.h Normal file
View File

@ -0,0 +1,20 @@
/* This file defines the fixed addresses where userspace programs can find
atomic code sequences. */
#define FIXED_CODE_START 0x400
#define SIGRETURN_STUB 0x400
#define ATOMIC_SEQS_START 0x410
#define ATOMIC_XCHG32 0x410
#define ATOMIC_CAS32 0x420
#define ATOMIC_ADD32 0x430
#define ATOMIC_SUB32 0x440
#define ATOMIC_IOR32 0x450
#define ATOMIC_AND32 0x460
#define ATOMIC_XOR32 0x470
#define ATOMIC_SEQS_END 0x480
#define FIXED_CODE_END 0x480

58
include/asm-blackfin/gpio.h
View File

@ -204,8 +204,62 @@
#endif
#ifdef BF548_FAMILY
#include <asm-blackfin/mach-bf548/gpio.h>
#endif
#ifdef BF561_FAMILY
#define MAX_BLACKFIN_GPIOS 48
#define GPIO_PF0 0
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PF16 16
#define GPIO_PF17 17
#define GPIO_PF18 18
#define GPIO_PF19 19
#define GPIO_PF20 20
#define GPIO_PF21 21
#define GPIO_PF22 22
#define GPIO_PF23 23
#define GPIO_PF24 24
#define GPIO_PF25 25
#define GPIO_PF26 26
#define GPIO_PF27 27
#define GPIO_PF28 28
#define GPIO_PF29 29
#define GPIO_PF30 30
#define GPIO_PF31 31
#define GPIO_PF32 32
#define GPIO_PF33 33
#define GPIO_PF34 34
#define GPIO_PF35 35
#define GPIO_PF36 36
#define GPIO_PF37 37
#define GPIO_PF38 38
#define GPIO_PF39 39
#define GPIO_PF40 40
#define GPIO_PF41 41
#define GPIO_PF42 42
#define GPIO_PF43 43
#define GPIO_PF44 44
#define GPIO_PF45 45
#define GPIO_PF46 46
#define GPIO_PF47 47
#define PORT_FIO0 GPIO_0
#define PORT_FIO1 GPIO_16
#define PORT_FIO2 GPIO_32
@ -230,6 +284,7 @@
* MODIFICATION HISTORY :
**************************************************************/
#ifndef BF548_FAMILY
void set_gpio_dir(unsigned short, unsigned short);
void set_gpio_inen(unsigned short, unsigned short);
void set_gpio_polar(unsigned short, unsigned short);
@ -299,6 +354,7 @@ struct gpio_port_t {
unsigned short dummy16;
unsigned short inen;
};
#endif
#ifdef CONFIG_PM
#define PM_WAKE_RISING 0x1
@ -357,8 +413,10 @@ void gpio_free(unsigned short);
void gpio_set_value(unsigned short gpio, unsigned short arg);
unsigned short gpio_get_value(unsigned short gpio);
#ifndef BF548_FAMILY
#define gpio_get_value(gpio) get_gpio_data(gpio)
#define gpio_set_value(gpio, value) set_gpio_data(gpio, value)
#endif
void gpio_direction_input(unsigned short gpio);
void gpio_direction_output(unsigned short gpio);

4
include/asm-blackfin/hardirq.h
View File

@ -28,7 +28,11 @@ typedef struct {
* SOFTIRQ_MASK: 0x00ff0000
*/
#if NR_IRQS > 256
#define HARDIRQ_BITS 9
#else
#define HARDIRQ_BITS 8
#endif
#ifdef NR_IRQS
# if (1 << HARDIRQ_BITS) < NR_IRQS

183
include/asm-blackfin/kgdb.h Normal file
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@ -0,0 +1,183 @@
/*
* File: include/asm-blackfin/kgdb.h
* Based on:
* Author: Sonic Zhang
*
* Created:
* Description:
*
* Rev: $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $
*
* Modified:
* Copyright 2005-2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __ASM_BLACKFIN_KGDB_H__
#define __ASM_BLACKFIN_KGDB_H__
#include <linux/ptrace.h>
/* gdb locks */
#define KGDB_MAX_NO_CPUS 8
/************************************************************************/
/* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/
/* at least NUMREGBYTES*2 are needed for register packets */
/* Longer buffer is needed to list all threads */
#define BUFMAX 2048
/*
* Note that this register image is different from
* the register image that Linux produces at interrupt time.
*
* Linux's register image is defined by struct pt_regs in ptrace.h.
*/
enum regnames {
/* Core Registers */
BFIN_R0 = 0,
BFIN_R1,
BFIN_R2,
BFIN_R3,
BFIN_R4,
BFIN_R5,
BFIN_R6,
BFIN_R7,
BFIN_P0,
BFIN_P1,
BFIN_P2,
BFIN_P3,
BFIN_P4,
BFIN_P5,
BFIN_SP,
BFIN_FP,
BFIN_I0,
BFIN_I1,
BFIN_I2,
BFIN_I3,
BFIN_M0,
BFIN_M1,
BFIN_M2,
BFIN_M3,
BFIN_B0,
BFIN_B1,
BFIN_B2,
BFIN_B3,
BFIN_L0,
BFIN_L1,
BFIN_L2,
BFIN_L3,
BFIN_A0_DOT_X,
BFIN_A0_DOT_W,
BFIN_A1_DOT_X,
BFIN_A1_DOT_W,
BFIN_ASTAT,
BFIN_RETS,
BFIN_LC0,
BFIN_LT0,
BFIN_LB0,
BFIN_LC1,
BFIN_LT1,
BFIN_LB1,
BFIN_CYCLES,
BFIN_CYCLES2,
BFIN_USP,
BFIN_SEQSTAT,
BFIN_SYSCFG,
BFIN_RETI,
BFIN_RETX,
BFIN_RETN,
BFIN_RETE,
/* Pseudo Registers */
BFIN_PC,
BFIN_CC,
BFIN_EXTRA1, /* Address of .text section. */
BFIN_EXTRA2, /* Address of .data section. */
BFIN_EXTRA3, /* Address of .bss section. */
BFIN_FDPIC_EXEC,
BFIN_FDPIC_INTERP,
/* MMRs */
BFIN_IPEND,
/* LAST ENTRY SHOULD NOT BE CHANGED. */
BFIN_NUM_REGS /* The number of all registers. */
};
/* Number of bytes of registers. */
#define NUMREGBYTES BFIN_NUM_REGS*4
#define BREAKPOINT() asm(" EXCPT 2;");
#define BREAK_INSTR_SIZE 2
#define HW_BREAKPOINT_NUM 6
/* Instruction watchpoint address control register bits mask */
#define WPPWR 0x1
#define WPIREN01 0x2
#define WPIRINV01 0x4
#define WPIAEN0 0x8
#define WPIAEN1 0x10
#define WPICNTEN0 0x20
#define WPICNTEN1 0x40
#define EMUSW0 0x80
#define EMUSW1 0x100
#define WPIREN23 0x200
#define WPIRINV23 0x400
#define WPIAEN2 0x800
#define WPIAEN3 0x1000
#define WPICNTEN2 0x2000
#define WPICNTEN3 0x4000
#define EMUSW2 0x8000
#define EMUSW3 0x10000
#define WPIREN45 0x20000
#define WPIRINV45 0x40000
#define WPIAEN4 0x80000
#define WPIAEN5 0x100000
#define WPICNTEN4 0x200000
#define WPICNTEN5 0x400000
#define EMUSW4 0x800000
#define EMUSW5 0x1000000
#define WPAND 0x2000000
/* Data watchpoint address control register bits mask */
#define WPDREN01 0x1
#define WPDRINV01 0x2
#define WPDAEN0 0x4
#define WPDAEN1 0x8
#define WPDCNTEN0 0x10
#define WPDCNTEN1 0x20
#define WPDSRC0 0xc0
#define WPDACC0 0x300
#define WPDSRC1 0xc00
#define WPDACC1 0x3000
/* Watchpoint status register bits mask */
#define STATIA0 0x1
#define STATIA1 0x2
#define STATIA2 0x4
#define STATIA3 0x8
#define STATIA4 0x10
#define STATIA5 0x20
#define STATDA0 0x40
#define STATDA1 0x80
extern void kgdb_print(const char *fmt, ...);
#endif

3
include/asm-blackfin/mach-bf533/dma.h
View File

@ -51,4 +51,7 @@
#define CH_MEM_STREAM1_DEST 10 /* TX */
#define CH_MEM_STREAM1_SRC 11 /* RX */
extern int channel2irq(unsigned int channel);
extern struct dma_register *base_addr[];
#endif

65
include/asm-blackfin/mach-bf533/portmux.h Normal file
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@ -0,0 +1,65 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define P_PPI0_CLK (P_DONTCARE)
#define P_PPI0_FS1 (P_DONTCARE)
#define P_PPI0_FS2 (P_DONTCARE)
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
#define P_PPI0_D0 (P_DONTCARE)
#define P_PPI0_D1 (P_DONTCARE)
#define P_PPI0_D2 (P_DONTCARE)
#define P_PPI0_D3 (P_DONTCARE)
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
#define P_SPORT1_TSCLK (P_DONTCARE)
#define P_SPORT1_RSCLK (P_DONTCARE)
#define P_SPORT0_TSCLK (P_DONTCARE)
#define P_SPORT0_RSCLK (P_DONTCARE)
#define P_UART0_RX (P_DONTCARE)
#define P_UART0_TX (P_DONTCARE)
#define P_SPORT1_DRSEC (P_DONTCARE)
#define P_SPORT1_RFS (P_DONTCARE)
#define P_SPORT1_DTPRI (P_DONTCARE)
#define P_SPORT1_DTSEC (P_DONTCARE)
#define P_SPORT1_TFS (P_DONTCARE)
#define P_SPORT1_DRPRI (P_DONTCARE)
#define P_SPORT0_DRSEC (P_DONTCARE)
#define P_SPORT0_RFS (P_DONTCARE)
#define P_SPORT0_DTPRI (P_DONTCARE)
#define P_SPORT0_DTSEC (P_DONTCARE)
#define P_SPORT0_TFS (P_DONTCARE)
#define P_SPORT0_DRPRI (P_DONTCARE)
#define P_SPI0_MOSI (P_DONTCARE)
#define P_SPI0_MIS0 (P_DONTCARE)
#define P_SPI0_SCK (P_DONTCARE)
#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
#define P_TMR2 (P_DONTCARE)
#define P_TMR1 (P_DONTCARE)
#define P_TMR0 (P_DONTCARE)
#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1))
#endif /* _MACH_PORTMUX_H_ */

3
include/asm-blackfin/mach-bf537/dma.h
View File

@ -52,4 +52,7 @@
#define CH_MEM_STREAM1_DEST 14 /* TX */
#define CH_MEM_STREAM1_SRC 15 /* RX */
extern int channel2irq(unsigned int channel);
extern struct dma_register *base_addr[];
#endif

109
include/asm-blackfin/mach-bf537/portmux.h Normal file
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@ -0,0 +1,109 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
#define PORT_PJ0 (GPIO_PH15 + 1)
#define PORT_PJ1 (GPIO_PH15 + 2)
#define PORT_PJ2 (GPIO_PH15 + 3)
#define PORT_PJ3 (GPIO_PH15 + 4)
#define PORT_PJ4 (GPIO_PH15 + 5)
#define PORT_PJ5 (GPIO_PH15 + 6)
#define PORT_PJ6 (GPIO_PH15 + 7)
#define PORT_PJ7 (GPIO_PH15 + 8)
#define PORT_PJ8 (GPIO_PH15 + 9)
#define PORT_PJ9 (GPIO_PH15 + 10)
#define PORT_PJ10 (GPIO_PH15 + 11)
#define PORT_PJ11 (GPIO_PH15 + 12)
#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
#endif /* _MACH_PORTMUX_H_ */

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/*
* File: include/asm-blackfin/mach-bf548/anomaly.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
slot1 and store of a P register in slot 2 is not
supported */
#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
Channel DMA stops */
#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
registers. */
#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the
Shadow of a Conditional Branch */
#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
interrupt not functional */
#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
SPORT external receive and transmit clocks. */
#define ANOMALY_05000272 /* Certain data cache write through modes fail for
VDDint <=0.9V */
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
not restored */
#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the
Boundary of Reserved Memory */
#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and
LC Registers Are Interrupted */
#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */
#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */
#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to
the USB FIFO Simultaneously */
#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write()
function */
#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional
*/
#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */
#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM
Skew */
#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */
#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration
of Host DMA Port */
#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent
Allowed Configuration on Host DMA Port */
#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
#endif /* _MACH_ANOMALY_H_ */

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/*
* File: include/asm-blackfin/mach-bf548/bf548.h
* Based on:
* Author:
*
* Created:
* Description: System MMR register and memory map for ADSP-BF548
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MACH_BF548_H__
#define __MACH_BF548_H__
#define SUPPORTED_REVID 0
#define OFFSET_(x) ((x) & 0x0000FFFF)
/*some misc defines*/
#define IMASK_IVG15 0x8000
#define IMASK_IVG14 0x4000
#define IMASK_IVG13 0x2000
#define IMASK_IVG12 0x1000
#define IMASK_IVG11 0x0800
#define IMASK_IVG10 0x0400
#define IMASK_IVG9 0x0200
#define IMASK_IVG8 0x0100
#define IMASK_IVG7 0x0080
#define IMASK_IVGTMR 0x0040
#define IMASK_IVGHW 0x0020
/***************************/
#define BLKFIN_DSUBBANKS 4
#define BLKFIN_DWAYS 2
#define BLKFIN_DLINES 64
#define BLKFIN_ISUBBANKS 4
#define BLKFIN_IWAYS 4
#define BLKFIN_ILINES 32
#define WAY0_L 0x1
#define WAY1_L 0x2
#define WAY01_L 0x3
#define WAY2_L 0x4
#define WAY02_L 0x5
#define WAY12_L 0x6
#define WAY012_L 0x7
#define WAY3_L 0x8
#define WAY03_L 0x9
#define WAY13_L 0xA
#define WAY013_L 0xB
#define WAY32_L 0xC
#define WAY320_L 0xD
#define WAY321_L 0xE
#define WAYALL_L 0xF
#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
/********************************* EBIU Settings ************************************/
#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
#ifdef CONFIG_C_AMBEN_ALL
#define V_AMBEN AMBEN_ALL
#endif
#ifdef CONFIG_C_AMBEN
#define V_AMBEN 0x0
#endif
#ifdef CONFIG_C_AMBEN_B0
#define V_AMBEN AMBEN_B0
#endif
#ifdef CONFIG_C_AMBEN_B0_B1
#define V_AMBEN AMBEN_B0_B1
#endif
#ifdef CONFIG_C_AMBEN_B0_B1_B2
#define V_AMBEN AMBEN_B0_B1_B2
#endif
#ifdef CONFIG_C_AMCKEN
#define V_AMCKEN AMCKEN
#else
#define V_AMCKEN 0x0
#endif
#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
#define MAX_VC 650000000
#define MIN_VC 50000000
/********************************PLL Settings **************************************/
#ifdef CONFIG_BFIN_KERNEL_CLOCK
#if (CONFIG_VCO_MULT < 0)
#error "VCO Multiplier is less than 0. Please select a different value"
#endif
#if (CONFIG_VCO_MULT == 0)
#error "VCO Multiplier should be greater than 0. Please select a different value"
#endif
#if (CONFIG_VCO_MULT > 64)
#error "VCO Multiplier is more than 64. Please select a different value"
#endif
#ifndef CONFIG_CLKIN_HALF
#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
#else
#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
#endif
#ifndef CONFIG_PLL_BYPASS
#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
#else
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
#endif
#if (CONFIG_SCLK_DIV < 1)
#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
#endif
#if (CONFIG_SCLK_DIV > 15)
#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
#endif
#if (CONFIG_CCLK_DIV != 1)
#if (CONFIG_CCLK_DIV != 2)
#if (CONFIG_CCLK_DIV != 4)
#if (CONFIG_CCLK_DIV != 8)
#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
#endif
#endif
#endif
#endif
#if (CONFIG_VCO_HZ > MAX_VC)
#error "VCO selected is more than maximum value. Please change the VCO multipler"
#endif
#if (CONFIG_SCLK_HZ > 133000000)
#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
#endif
#if (CONFIG_SCLK_HZ < 27000000)
#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
#endif
#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
#error "Please select sclk less than cclk"
#endif
#endif
#endif
#if (CONFIG_CCLK_DIV == 1)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
#endif
#if (CONFIG_CCLK_DIV == 2)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
#endif
#if (CONFIG_CCLK_DIV == 4)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
#endif
#if (CONFIG_CCLK_DIV == 8)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
#endif
#ifndef CONFIG_CCLK_ACT_DIV
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
#endif
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
#ifdef CONFIG_BF542
#define CPU "BF542"
#define CPUID 0x027c8000
#endif
#ifdef CONFIG_BF544
#define CPU "BF544"
#define CPUID 0x027c8000
#endif
#ifdef CONFIG_BF548
#define CPU "BF548"
#define CPUID 0x027c6000
#endif
#ifdef CONFIG_BF549
#define CPU "BF549"
#endif
#ifndef CPU
#define CPU "UNKNOWN"
#define CPUID 0x0
#endif
#if (CONFIG_MEM_SIZE % 4)
#error "SDRAM mem size must be multible of 4MB"
#endif
#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
#define ANOMALY_05000158_WORKAROUND 0x200
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#else /*Write Through */
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
#endif
#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
#define SIZE_1K 0x00000400 /* 1K */
#define SIZE_4K 0x00001000 /* 4K */
#define SIZE_1M 0x00100000 /* 1M */
#define SIZE_4M 0x00400000 /* 4M */
#define MAX_CPLBS (16 * 2)
/*
* Number of required data CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Data Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
* 1 for ASYNC Memory
*/
#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
/*
* Number of required instruction CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Instruction Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
*/
#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
#endif /* __MACH_BF48_H__ */

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#include <linux/serial.h>
#include <asm/dma.h>
#define NR_PORTS 4
#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
#define OFFSET_GCTL 0x08 /* Global Control Register */
#define OFFSET_LCR 0x0C /* Line Control Register */
#define OFFSET_MCR 0x10 /* Modem Control Register */
#define OFFSET_LSR 0x14 /* Line Status Register */
#define OFFSET_MSR 0x18 /* Modem Status Register */
#define OFFSET_SCR 0x1C /* SCR Scratch Register */
#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
#define OFFSET_THR 0x28 /* Transmit Holding register */
#define OFFSET_RBR 0x2C /* Receive Buffer register */
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN
# define CONFIG_UART0_CTS_PIN -1
# endif
# ifndef CONFIG_UART0_RTS_PIN
# define CONFIG_UART0_RTS_PIN -1
# endif
# ifndef CONFIG_UART1_CTS_PIN
# define CONFIG_UART1_CTS_PIN -1
# endif
# ifndef CONFIG_UART1_RTS_PIN
# define CONFIG_UART1_RTS_PIN -1
# endif
#endif
/*
* The pin configuration is different from schematic
*/
struct bfin_serial_port {
struct uart_port port;
unsigned int old_status;
#ifdef CONFIG_SERIAL_BFIN_DMA
int tx_done;
int tx_count;
struct circ_buf rx_dma_buf;
struct timer_list rx_dma_timer;
int rx_dma_nrows;
unsigned int tx_dma_channel;
unsigned int rx_dma_channel;
struct work_struct tx_dma_workqueue;
#else
struct work_struct cts_workqueue;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
int cts_pin;
int rts_pin;
#endif
};
struct bfin_serial_port bfin_serial_ports[NR_PORTS];
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
#ifdef CONFIG_SERIAL_BFIN_DMA
unsigned int uart_tx_dma_channel;
unsigned int uart_rx_dma_channel;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
int uart_cts_pin;
int uart_rts_pin;
#endif
};
struct bfin_serial_res bfin_serial_resource[] = {
#ifdef CONFIG_SERIAL_BFIN_UART0
{
0xFFC00400,
IRQ_UART0_RX,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART0_TX,
CH_UART0_RX,
#endif
#ifdef CONFIG_BFIN_UART0_CTSRTS
CONFIG_UART0_CTS_PIN,
CONFIG_UART0_RTS_PIN,
#endif
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
{
0xFFC02000,
IRQ_UART1_RX,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART1_TX,
CH_UART1_RX,
#endif
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART2
{
0xFFC02100,
IRQ_UART2_RX,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART2_TX,
CH_UART2_RX,
#endif
#ifdef CONFIG_BFIN_UART2_CTSRTS
CONFIG_UART2_CTS_PIN,
CONFIG_UART2_RTS_PIN,
#endif
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART3
{
0xFFC03100,
IRQ_UART3_RX,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART3_TX,
CH_UART3_RX,
#endif
},
#endif
};
int nr_ports = ARRAY_SIZE(bfin_serial_resource);
static void bfin_serial_hw_init(struct bfin_serial_port *uart)
{
#ifdef CONFIG_SERIAL_BFIN_UART0
/* Enable UART0 RX and TX on pin 7 & 8 of PORT E */
bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER());
bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX());
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
/* Enable UART1 RX and TX on pin 0 & 1 of PORT H */
bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER());
bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX());
#ifdef CONFIG_BFIN_UART1_CTSRTS
/* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */
bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER());
bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX());
#endif
#endif
#ifdef CONFIG_SERIAL_BFIN_UART2
/* Enable UART2 RX and TX on pin 4 & 5 of PORT B */
bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER());
bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX());
#endif
#ifdef CONFIG_SERIAL_BFIN_UART3
/* Enable UART3 RX and TX on pin 6 & 7 of PORT B */
bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER());
bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX());
#ifdef CONFIG_BFIN_UART3_CTSRTS
/* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */
bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER());
bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX());
#endif
#endif
SSYNC();
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
if (uart->cts_pin >= 0) {
gpio_request(uart->cts_pin, NULL);
gpio_direction_input(uart->cts_pin);
}
if (uart->rts_pin >= 0) {
gpio_request(uart->rts_pin, NULL);
gpio_direction_output(uart->rts_pin);
}
#endif
}

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@ -0,0 +1,168 @@
/*
* File: include/asm-blackfin/mach-bf548/blackfin.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _MACH_BLACKFIN_H_
#define _MACH_BLACKFIN_H_
#define BF548_FAMILY
#include "bf548.h"
#include "mem_map.h"
#include "anomaly.h"
#ifdef CONFIG_BF542
#include "defBF542.h"
#endif
#ifdef CONFIG_BF544
#include "defBF544.h"
#endif
#ifdef CONFIG_BF548
#include "defBF548.h"
#endif
#ifdef CONFIG_BF549
#include "defBF549.h"
#endif
#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
#ifdef CONFIG_BF542
#include "cdefBF542.h"
#endif
#ifdef CONFIG_BF544
#include "cdefBF544.h"
#endif
#ifdef CONFIG_BF548
#include "cdefBF548.h"
#endif
#ifdef CONFIG_BF549
#include "cdefBF549.h"
#endif
/* UART 1*/
#define bfin_read_UART_THR() bfin_read_UART1_THR()
#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val)
#define bfin_read_UART_RBR() bfin_read_UART1_RBR()
#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val)
#define bfin_read_UART_DLL() bfin_read_UART1_DLL()
#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val)
#define bfin_read_UART_IER() bfin_read_UART1_IER()
#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val)
#define bfin_read_UART_DLH() bfin_read_UART1_DLH()
#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val)
#define bfin_read_UART_IIR() bfin_read_UART1_IIR()
#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val)
#define bfin_read_UART_LCR() bfin_read_UART1_LCR()
#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val)
#define bfin_read_UART_MCR() bfin_read_UART1_MCR()
#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val)
#define bfin_read_UART_LSR() bfin_read_UART1_LSR()
#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val)
#define bfin_read_UART_SCR() bfin_read_UART1_SCR()
#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
#endif
/* MAP used DEFINES from BF533 to BF54x - so we don't need to change
* them in the driver, kernel, etc. */
/* UART_IIR Register */
#define STATUS(x) ((x << 1) & 0x06)
#define STATUS_P1 0x02
#define STATUS_P0 0x01
/* UART 0*/
/* DMA Channnel */
#define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX()
#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val)
#define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX()
#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART1_TX(val)
#define CH_UART_RX CH_UART1_RX
#define CH_UART_TX CH_UART1_TX
/* System Interrupt Controller */
#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART1_RX()
#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART1_RX(val)
#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART1_TX()
#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART1_TX(val)
#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART1_ERROR()
#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART1_ERROR(val)
#define IRQ_UART_RX IRQ_UART1_RX
#define IRQ_UART_TX IRQ_UART1_TX
#define IRQ_UART_ERROR IRQ_UART1_ERROR
/* MMR Registers*/
#define bfin_read_UART_THR() bfin_read_UART1_THR()
#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val)
#define bfin_read_UART_RBR() bfin_read_UART1_RBR()
#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val)
#define bfin_read_UART_DLL() bfin_read_UART1_DLL()
#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val)
#define bfin_read_UART_IER() bfin_read_UART1_IER()
#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val)
#define bfin_read_UART_DLH() bfin_read_UART1_DLH()
#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val)
#define bfin_read_UART_IIR() bfin_read_UART1_IIR()
#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val)
#define bfin_read_UART_LCR() bfin_read_UART1_LCR()
#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val)
#define bfin_read_UART_MCR() bfin_read_UART1_MCR()
#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val)
#define bfin_read_UART_LSR() bfin_read_UART1_LSR()
#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val)
#define bfin_read_UART_SCR() bfin_read_UART1_SCR()
#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
#define UART_THR UART1_THR
#define UART_RBR UART1_RBR
#define UART_DLL UART1_DLL
#define UART_IER UART1_IER
#define UART_DLH UART1_DLH
#define UART_IIR UART1_IIR
#define UART_LCR UART1_LCR
#define UART_MCR UART1_MCR
#define UART_LSR UART1_LSR
#define UART_SCR UART1_SCR
#define UART_GCTL UART1_GCTL
/* PLL_DIV Masks */
#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
#endif

72
include/asm-blackfin/mach-bf548/cdefBF54x_base.h
View File

@ -31,7 +31,8 @@
#ifndef _CDEF_BF54X_H
#define _CDEF_BF54X_H
#include <defBF54x_base.h>
#include "defBF54x_base.h"
#include <asm/system.h>
/* ************************************************************** */
/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
@ -44,7 +45,30 @@
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1, iwr2;
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
iwr2 = bfin_read32(SIC_IWR2);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write32(SIC_IWR2, 0);
bfin_write16(VR_CTL, val);
__builtin_bfin_ssync();
local_irq_save(flags);
asm("IDLE;");
local_irq_restore(flags);
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
bfin_write32(SIC_IWR2, iwr2);
}
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@ -70,12 +94,18 @@
#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2))
#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))
#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
@ -710,21 +740,21 @@
#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR)
#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR)
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY)
#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY)
#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR)
#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR)
#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
@ -734,23 +764,23 @@
#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR)
#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY)
#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY)
#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR)
#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR)
#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
@ -763,9 +793,9 @@
/* MDMA Stream 1 Registers */
#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR)
#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
@ -777,9 +807,9 @@
#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY)
#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR)
#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR)
#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
@ -789,9 +819,9 @@
#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR)
#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
@ -803,9 +833,9 @@
#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY)
#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR)
#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR)
#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)

281
include/asm-blackfin/mach-bf548/defBF542.h
View File

@ -362,7 +362,6 @@
/* Bit masks for KPAD_CTL */
#define KPAD_EN 0x1 /* Keypad Enable */
#define nKPAD_EN 0x0
#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
#define KPAD_COLEN 0xe000 /* Column Enable Width */
@ -384,29 +383,21 @@
/* Bit masks for KPAD_STAT */
#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
#define nKPAD_IRQ 0x0
#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
#define KPAD_PRESSED 0x8 /* Key press current status */
#define nKPAD_PRESSED 0x0
/* Bit masks for KPAD_SOFTEVAL */
#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
#define nKPAD_SOFTEVAL_E 0x0
/* Bit masks for SDH_COMMAND */
#define CMD_IDX 0x3f /* Command Index */
#define CMD_RSP 0x40 /* Response */
#define nCMD_RSP 0x0
#define CMD_L_RSP 0x80 /* Long Response */
#define nCMD_L_RSP 0x0
#define CMD_INT_E 0x100 /* Command Interrupt */
#define nCMD_INT_E 0x0
#define CMD_PEND_E 0x200 /* Command Pending */
#define nCMD_PEND_E 0x0
#define CMD_E 0x400 /* Command Enable */
#define nCMD_E 0x0
/* Bit masks for SDH_PWR_CTL */
@ -415,21 +406,15 @@
#define TBD 0x3c /* TBD */
#endif
#define SD_CMD_OD 0x40 /* Open Drain Output */
#define nSD_CMD_OD 0x0
#define ROD_CTL 0x80 /* Rod Control */
#define nROD_CTL 0x0
/* Bit masks for SDH_CLK_CTL */
#define CLKDIV 0xff /* MC_CLK Divisor */
#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
#define nCLK_E 0x0
#define PWR_SV_E 0x200 /* Power Save Enable */
#define nPWR_SV_E 0x0
#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
#define nCLKDIV_BYPASS 0x0
#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
#define nWIDE_BUS 0x0
/* Bit masks for SDH_RESP_CMD */
@ -438,133 +423,74 @@
/* Bit masks for SDH_DATA_CTL */
#define DTX_E 0x1 /* Data Transfer Enable */
#define nDTX_E 0x0
#define DTX_DIR 0x2 /* Data Transfer Direction */
#define nDTX_DIR 0x0
#define DTX_MODE 0x4 /* Data Transfer Mode */
#define nDTX_MODE 0x0
#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
#define nDTX_DMA_E 0x0
#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
/* Bit masks for SDH_STATUS */
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
#define nCMD_CRC_FAIL 0x0
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
#define nDAT_CRC_FAIL 0x0
#define CMD_TIMEOUT 0x4 /* CMD Time Out */
#define nCMD_TIMEOUT 0x0
#define DAT_TIMEOUT 0x8 /* Data Time Out */
#define nDAT_TIMEOUT 0x0
#define TX_UNDERRUN 0x10 /* Transmit Underrun */
#define nTX_UNDERRUN 0x0
#define RX_OVERRUN 0x20 /* Receive Overrun */
#define nRX_OVERRUN 0x0
#define CMD_RESP_END 0x40 /* CMD Response End */
#define nCMD_RESP_END 0x0
#define CMD_SENT 0x80 /* CMD Sent */
#define nCMD_SENT 0x0
#define DAT_END 0x100 /* Data End */
#define nDAT_END 0x0
#define START_BIT_ERR 0x200 /* Start Bit Error */
#define nSTART_BIT_ERR 0x0
#define DAT_BLK_END 0x400 /* Data Block End */
#define nDAT_BLK_END 0x0
#define CMD_ACT 0x800 /* CMD Active */
#define nCMD_ACT 0x0
#define TX_ACT 0x1000 /* Transmit Active */
#define nTX_ACT 0x0
#define RX_ACT 0x2000 /* Receive Active */
#define nRX_ACT 0x0
#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
#define nTX_FIFO_STAT 0x0
#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
#define nRX_FIFO_STAT 0x0
#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
#define nTX_FIFO_FULL 0x0
#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
#define nRX_FIFO_FULL 0x0
#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
#define nTX_FIFO_ZERO 0x0
#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
#define nRX_DAT_ZERO 0x0
#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
#define nTX_DAT_RDY 0x0
#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
#define nRX_FIFO_RDY 0x0
/* Bit masks for SDH_STATUS_CLR */
#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
#define nCMD_CRC_FAIL_STAT 0x0
#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
#define nDAT_CRC_FAIL_STAT 0x0
#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
#define nCMD_TIMEOUT_STAT 0x0
#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
#define nDAT_TIMEOUT_STAT 0x0
#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
#define nTX_UNDERRUN_STAT 0x0
#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
#define nRX_OVERRUN_STAT 0x0
#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
#define nCMD_RESP_END_STAT 0x0
#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
#define nCMD_SENT_STAT 0x0
#define DAT_END_STAT 0x100 /* Data End Status */
#define nDAT_END_STAT 0x0
#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
#define nSTART_BIT_ERR_STAT 0x0
#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
#define nDAT_BLK_END_STAT 0x0
/* Bit masks for SDH_MASK0 */
#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
#define nCMD_CRC_FAIL_MASK 0x0
#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
#define nDAT_CRC_FAIL_MASK 0x0
#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
#define nCMD_TIMEOUT_MASK 0x0
#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
#define nDAT_TIMEOUT_MASK 0x0
#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
#define nTX_UNDERRUN_MASK 0x0
#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
#define nRX_OVERRUN_MASK 0x0
#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
#define nCMD_RESP_END_MASK 0x0
#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
#define nCMD_SENT_MASK 0x0
#define DAT_END_MASK 0x100 /* Data End Mask */
#define nDAT_END_MASK 0x0
#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
#define nSTART_BIT_ERR_MASK 0x0
#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
#define nDAT_BLK_END_MASK 0x0
#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
#define nCMD_ACT_MASK 0x0
#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
#define nTX_ACT_MASK 0x0
#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
#define nRX_ACT_MASK 0x0
#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
#define nTX_FIFO_STAT_MASK 0x0
#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
#define nRX_FIFO_STAT_MASK 0x0
#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
#define nTX_FIFO_FULL_MASK 0x0
#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
#define nRX_FIFO_FULL_MASK 0x0
#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
#define nTX_FIFO_ZERO_MASK 0x0
#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
#define nRX_DAT_ZERO_MASK 0x0
#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
#define nTX_DAT_RDY_MASK 0x0
#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
#define nRX_FIFO_RDY_MASK 0x0
/* Bit masks for SDH_FIFO_CNT */
@ -573,73 +499,47 @@
/* Bit masks for SDH_E_STATUS */
#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
#define nSDIO_INT_DET 0x0
#define SD_CARD_DET 0x10 /* SD Card Detect */
#define nSD_CARD_DET 0x0
/* Bit masks for SDH_E_MASK */
#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
#define nSDIO_MSK 0x0
#define SCD_MSK 0x40 /* Mask Card Detect */
#define nSCD_MSK 0x0
/* Bit masks for SDH_CFG */
#define CLKS_EN 0x1 /* Clocks Enable */
#define nCLKS_EN 0x0
#define SD4E 0x4 /* SDIO 4-Bit Enable */
#define nSD4E 0x0
#define MWE 0x8 /* Moving Window Enable */
#define nMWE 0x0
#define SD_RST 0x10 /* SDMMC Reset */
#define nSD_RST 0x0
#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
#define nPUP_SDDAT 0x0
#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
#define nPUP_SDDAT3 0x0
#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
#define nPD_SDDAT3 0x0
/* Bit masks for SDH_RD_WAIT_EN */
#define RWR 0x1 /* Read Wait Request */
#define nRWR 0x0
/* Bit masks for ATAPI_CONTROL */
#define PIO_START 0x1 /* Start PIO/Reg Op */
#define nPIO_START 0x0
#define MULTI_START 0x2 /* Start Multi-DMA Op */
#define nMULTI_START 0x0
#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
#define nULTRA_START 0x0
#define XFER_DIR 0x8 /* Transfer Direction */
#define nXFER_DIR 0x0
#define IORDY_EN 0x10 /* IORDY Enable */
#define nIORDY_EN 0x0
#define FIFO_FLUSH 0x20 /* Flush FIFOs */
#define nFIFO_FLUSH 0x0
#define SOFT_RST 0x40 /* Soft Reset */
#define nSOFT_RST 0x0
#define DEV_RST 0x80 /* Device Reset */
#define nDEV_RST 0x0
#define TFRCNT_RST 0x100 /* Trans Count Reset */
#define nTFRCNT_RST 0x0
#define END_ON_TERM 0x200 /* End/Terminate Select */
#define nEND_ON_TERM 0x0
#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
#define nPIO_USE_DMA 0x0
#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
/* Bit masks for ATAPI_STATUS */
#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
#define nPIO_XFER_ON 0x0
#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
#define nMULTI_XFER_ON 0x0
#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
#define nULTRA_XFER_ON 0x0
#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
/* Bit masks for ATAPI_DEV_ADDR */
@ -649,66 +549,39 @@
/* Bit masks for ATAPI_INT_MASK */
#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
#define nATAPI_DEV_INT_MASK 0x0
#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
#define nPIO_DONE_MASK 0x0
#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
#define nMULTI_DONE_MASK 0x0
#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
#define nUDMAIN_DONE_MASK 0x0
#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
#define nUDMAOUT_DONE_MASK 0x0
#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
#define nHOST_TERM_XFER_MASK 0x0
#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
#define nMULTI_TERM_MASK 0x0
#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
#define nUDMAIN_TERM_MASK 0x0
#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
#define nUDMAOUT_TERM_MASK 0x0
/* Bit masks for ATAPI_INT_STATUS */
#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
#define nATAPI_DEV_INT 0x0
#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
#define nPIO_DONE_INT 0x0
#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
#define nMULTI_DONE_INT 0x0
#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
#define nUDMAIN_DONE_INT 0x0
#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
#define nUDMAOUT_DONE_INT 0x0
#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
#define nHOST_TERM_XFER_INT 0x0
#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
#define nMULTI_TERM_INT 0x0
#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
#define nUDMAIN_TERM_INT 0x0
#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
#define nUDMAOUT_TERM_INT 0x0
/* Bit masks for ATAPI_LINE_STATUS */
#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
#define nATAPI_INTR 0x0
#define ATAPI_DASP 0x2 /* Device dasp to host line status */
#define nATAPI_DASP 0x0
#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
#define nATAPI_CS0N 0x0
#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
#define nATAPI_CS1N 0x0
#define ATAPI_ADDR 0x70 /* ATAPI address line status */
#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
#define nATAPI_DMAREQ 0x0
#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
#define nATAPI_DMAACKN 0x0
#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
#define nATAPI_DIOWN 0x0
#define ATAPI_DIORN 0x400 /* ATAPI read line status */
#define nATAPI_DIORN 0x0
#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
#define nATAPI_IORDY 0x0
/* Bit masks for ATAPI_SM_STATE */
@ -720,7 +593,6 @@
/* Bit masks for ATAPI_TERMINATE */
#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
#define nATAPI_HOST_TERM 0x0
/* Bit masks for ATAPI_REG_TIM_0 */
@ -779,131 +651,77 @@
/* Bit masks for USB_POWER */
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
#define nENABLE_SUSPENDM 0x0
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
#define nSUSPEND_MODE 0x0
#define RESUME_MODE 0x4 /* DMA Mode */
#define nRESUME_MODE 0x0
#define RESET 0x8 /* Reset indicator */
#define nRESET 0x0
#define HS_MODE 0x10 /* High Speed mode indicator */
#define nHS_MODE 0x0
#define HS_ENABLE 0x20 /* high Speed Enable */
#define nHS_ENABLE 0x0
#define SOFT_CONN 0x40 /* Soft connect */
#define nSOFT_CONN 0x0
#define ISO_UPDATE 0x80 /* Isochronous update */
#define nISO_UPDATE 0x0
/* Bit masks for USB_INTRTX */
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
#define nEP0_TX 0x0
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
#define nEP1_TX 0x0
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
#define nEP2_TX 0x0
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
#define nEP3_TX 0x0
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
#define nEP4_TX 0x0
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
#define nEP5_TX 0x0
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
#define nEP6_TX 0x0
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
#define nEP7_TX 0x0
/* Bit masks for USB_INTRRX */
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
#define nEP1_RX 0x0
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
#define nEP2_RX 0x0
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
#define nEP3_RX 0x0
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
#define nEP4_RX 0x0
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
#define nEP5_RX 0x0
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
#define nEP6_RX 0x0
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
#define nEP7_RX 0x0
/* Bit masks for USB_INTRTXE */
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
#define nEP0_TX_E 0x0
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
#define nEP1_TX_E 0x0
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
#define nEP2_TX_E 0x0
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
#define nEP3_TX_E 0x0
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
#define nEP4_TX_E 0x0
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
#define nEP5_TX_E 0x0
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
#define nEP6_TX_E 0x0
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
#define nEP7_TX_E 0x0
/* Bit masks for USB_INTRRXE */
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
#define nEP1_RX_E 0x0
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
#define nEP2_RX_E 0x0
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
#define nEP3_RX_E 0x0
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
#define nEP4_RX_E 0x0
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
#define nEP5_RX_E 0x0
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
#define nEP6_RX_E 0x0
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
#define nEP7_RX_E 0x0
/* Bit masks for USB_INTRUSB */
#define SUSPEND_B 0x1 /* Suspend indicator */
#define nSUSPEND_B 0x0
#define RESUME_B 0x2 /* Resume indicator */
#define nRESUME_B 0x0
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
#define nRESET_OR_BABLE_B 0x0
#define SOF_B 0x8 /* Start of frame */
#define nSOF_B 0x0
#define CONN_B 0x10 /* Connection indicator */
#define nCONN_B 0x0
#define DISCON_B 0x20 /* Disconnect indicator */
#define nDISCON_B 0x0
#define SESSION_REQ_B 0x40 /* Session Request */
#define nSESSION_REQ_B 0x0
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
#define nVBUS_ERROR_B 0x0
/* Bit masks for USB_INTRUSBE */
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
#define nSUSPEND_BE 0x0
#define RESUME_BE 0x2 /* Resume indicator int enable */
#define nRESUME_BE 0x0
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
#define nRESET_OR_BABLE_BE 0x0
#define SOF_BE 0x8 /* Start of frame int enable */
#define nSOF_BE 0x0
#define CONN_BE 0x10 /* Connection indicator int enable */
#define nCONN_BE 0x0
#define DISCON_BE 0x20 /* Disconnect indicator int enable */
#define nDISCON_BE 0x0
#define SESSION_REQ_BE 0x40 /* Session Request int enable */
#define nSESSION_REQ_BE 0x0
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
#define nVBUS_ERROR_BE 0x0
/* Bit masks for USB_FRAME */
@ -916,117 +734,67 @@
/* Bit masks for USB_GLOBAL_CTL */
#define GLOBAL_ENA 0x1 /* enables USB module */
#define nGLOBAL_ENA 0x0
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
#define nEP1_TX_ENA 0x0
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
#define nEP2_TX_ENA 0x0
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
#define nEP3_TX_ENA 0x0
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
#define nEP4_TX_ENA 0x0
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
#define nEP5_TX_ENA 0x0
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
#define nEP6_TX_ENA 0x0
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
#define nEP7_TX_ENA 0x0
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
#define nEP1_RX_ENA 0x0
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
#define nEP2_RX_ENA 0x0
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
#define nEP3_RX_ENA 0x0
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
#define nEP4_RX_ENA 0x0
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
#define nEP5_RX_ENA 0x0
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
#define nEP6_RX_ENA 0x0
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
#define nEP7_RX_ENA 0x0
/* Bit masks for USB_OTG_DEV_CTL */
#define SESSION 0x1 /* session indicator */
#define nSESSION 0x0
#define HOST_REQ 0x2 /* Host negotiation request */
#define nHOST_REQ 0x0
#define HOST_MODE 0x4 /* indicates USBDRC is a host */
#define nHOST_MODE 0x0
#define VBUS0 0x8 /* Vbus level indicator[0] */
#define nVBUS0 0x0
#define VBUS1 0x10 /* Vbus level indicator[1] */
#define nVBUS1 0x0
#define LSDEV 0x20 /* Low-speed indicator */
#define nLSDEV 0x0
#define FSDEV 0x40 /* Full or High-speed indicator */
#define nFSDEV 0x0
#define B_DEVICE 0x80 /* A' or 'B' device indicator */
#define nB_DEVICE 0x0
/* Bit masks for USB_OTG_VBUS_IRQ */
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
#define nDRIVE_VBUS_ON 0x0
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
#define nDRIVE_VBUS_OFF 0x0
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
#define nCHRG_VBUS_START 0x0
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
#define nCHRG_VBUS_END 0x0
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
#define nDISCHRG_VBUS_START 0x0
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
#define nDISCHRG_VBUS_END 0x0
/* Bit masks for USB_OTG_VBUS_MASK */
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
#define nDRIVE_VBUS_ON_ENA 0x0
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
#define nDRIVE_VBUS_OFF_ENA 0x0
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
#define nCHRG_VBUS_START_ENA 0x0
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
#define nCHRG_VBUS_END_ENA 0x0
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
#define nDISCHRG_VBUS_START_ENA 0x0
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
#define nDISCHRG_VBUS_END_ENA 0x0
/* Bit masks for USB_CSR0 */
#define RXPKTRDY 0x1 /* data packet receive indicator */
#define nRXPKTRDY 0x0
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
#define nTXPKTRDY 0x0
#define STALL_SENT 0x4 /* STALL handshake sent */
#define nSTALL_SENT 0x0
#define DATAEND 0x8 /* Data end indicator */
#define nDATAEND 0x0
#define SETUPEND 0x10 /* Setup end */
#define nSETUPEND 0x0
#define SENDSTALL 0x20 /* Send STALL handshake */
#define nSENDSTALL 0x0
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
#define nSERVICED_RXPKTRDY 0x0
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
#define nSERVICED_SETUPEND 0x0
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
#define nFLUSHFIFO 0x0
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
#define nSTALL_RECEIVED_H 0x0
#define SETUPPKT_H 0x8 /* send Setup token host mode */
#define nSETUPPKT_H 0x0
#define ERROR_H 0x10 /* timeout error indicator host mode */
#define nERROR_H 0x0
#define REQPKT_H 0x20 /* Request an IN transaction host mode */
#define nREQPKT_H 0x0
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
#define nSTATUSPKT_H 0x0
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
#define nNAK_TIMEOUT_H 0x0
/* Bit masks for USB_COUNT0 */
@ -1047,37 +815,21 @@
/* Bit masks for USB_TXCSR */
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
#define nTXPKTRDY_T 0x0
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
#define nFIFO_NOT_EMPTY_T 0x0
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
#define nUNDERRUN_T 0x0
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
#define nFLUSHFIFO_T 0x0
#define STALL_SEND_T 0x10 /* issue a Stall handshake */
#define nSTALL_SEND_T 0x0
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
#define nSTALL_SENT_T 0x0
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
#define nCLEAR_DATATOGGLE_T 0x0
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
#define nINCOMPTX_T 0x0
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
#define nDMAREQMODE_T 0x0
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
#define nFORCE_DATATOGGLE_T 0x0
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
#define nDMAREQ_ENA_T 0x0
#define ISO_T 0x4000 /* enable Isochronous transfers */
#define nISO_T 0x0
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
#define nAUTOSET_T 0x0
#define ERROR_TH 0x4 /* error condition host mode */
#define nERROR_TH 0x0
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
#define nSTALL_RECEIVED_TH 0x0
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
#define nNAK_TIMEOUT_TH 0x0
/* Bit masks for USB_TXCOUNT */
@ -1086,45 +838,25 @@
/* Bit masks for USB_RXCSR */
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
#define nRXPKTRDY_R 0x0
#define FIFO_FULL_R 0x2 /* FIFO not empty */
#define nFIFO_FULL_R 0x0
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
#define nOVERRUN_R 0x0
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
#define nDATAERROR_R 0x0
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
#define nFLUSHFIFO_R 0x0
#define STALL_SEND_R 0x20 /* issue a Stall handshake */
#define nSTALL_SEND_R 0x0
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
#define nSTALL_SENT_R 0x0
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
#define nCLEAR_DATATOGGLE_R 0x0
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
#define nINCOMPRX_R 0x0
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
#define nDMAREQMODE_R 0x0
#define DISNYET_R 0x1000 /* disable Nyet handshakes */
#define nDISNYET_R 0x0
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
#define nDMAREQ_ENA_R 0x0
#define ISO_R 0x4000 /* enable Isochronous transfers */
#define nISO_R 0x0
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
#define nAUTOCLEAR_R 0x0
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
#define nERROR_RH 0x0
#define REQPKT_RH 0x20 /* request an IN transaction host mode */
#define nREQPKT_RH 0x0
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
#define nSTALL_RECEIVED_RH 0x0
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
#define nINCOMPRX_RH 0x0
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
#define nDMAREQMODE_RH 0x0
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
#define nAUTOREQ_RH 0x0
/* Bit masks for USB_RXCOUNT */
@ -1151,35 +883,22 @@
/* Bit masks for USB_DMA_INTERRUPT */
#define DMA0_INT 0x1 /* DMA0 pending interrupt */
#define nDMA0_INT 0x0
#define DMA1_INT 0x2 /* DMA1 pending interrupt */
#define nDMA1_INT 0x0
#define DMA2_INT 0x4 /* DMA2 pending interrupt */
#define nDMA2_INT 0x0
#define DMA3_INT 0x8 /* DMA3 pending interrupt */
#define nDMA3_INT 0x0
#define DMA4_INT 0x10 /* DMA4 pending interrupt */
#define nDMA4_INT 0x0
#define DMA5_INT 0x20 /* DMA5 pending interrupt */
#define nDMA5_INT 0x0
#define DMA6_INT 0x40 /* DMA6 pending interrupt */
#define nDMA6_INT 0x0
#define DMA7_INT 0x80 /* DMA7 pending interrupt */
#define nDMA7_INT 0x0
/* Bit masks for USB_DMAxCONTROL */
#define DMA_ENA 0x1 /* DMA enable */
#define nDMA_ENA 0x0
#define DIRECTION 0x2 /* direction of DMA transfer */
#define nDIRECTION 0x0
#define MODE 0x4 /* DMA Bus error */
#define nMODE 0x0
#define INT_ENA 0x8 /* Interrupt enable */
#define nINT_ENA 0x0
#define EPNUM 0xf0 /* EP number */
#define BUSERROR 0x100 /* DMA Bus error */
#define nBUSERROR 0x0
/* Bit masks for USB_DMAxADDRHIGH */

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