Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (152 commits) powerpc: Fix hard CPU IDs detection powerpc/pmac: Update via-pmu to new syscore_ops powerpc/kvm: Fix the build for 32-bit Book 3S (classic) processors powerpc/kvm: Fix kvmppc_core_pending_dec powerpc: Remove last piece of GEMINI powerpc: Fix for Pegasos keyboard and mouse powerpc: Make early memory scan more resilient to out of order nodes powerpc/pseries/iommu: Cleanup ddw naming powerpc/pseries/iommu: Find windows after kexec during boot powerpc/pseries/iommu: Remove ddw property when destroying window powerpc/pseries/iommu: Add additional checks when changing iommu mask powerpc/pseries/iommu: Use correct return type in dupe_ddw_if_already_created powerpc: Remove unused/obsolete CONFIG_XICS misc: Add CARMA DATA-FPGA Programmer support misc: Add CARMA DATA-FPGA Access Driver powerpc: Make IRQ_NOREQUEST last to clear, first to set powerpc: Integrated Flash controller device tree bindings powerpc/85xx: Create dts of each core in CAMP mode for P1020RDB powerpc/85xx: Fix PCIe IDSEL for Px020RDB powerpc/85xx: P2020 DTS: re-organize dts files ...
This commit is contained in:
Linus Torvalds
commit
82aff107f8
61
Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
Executable file
61
Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
Executable file
@ -0,0 +1,61 @@
|
||||
CAN Device Tree Bindings
|
||||
------------------------
|
||||
2011 Freescale Semiconductor, Inc.
|
||||
|
||||
fsl,flexcan-v1.0 nodes
|
||||
-----------------------
|
||||
In addition to the required compatible-, reg- and interrupt-properties, you can
|
||||
also specify which clock source shall be used for the controller.
|
||||
|
||||
CPI Clock- Can Protocol Interface Clock
|
||||
This CLK_SRC bit of CTRL(control register) selects the clock source to
|
||||
the CAN Protocol Interface(CPI) to be either the peripheral clock
|
||||
(driven by the PLL) or the crystal oscillator clock. The selected clock
|
||||
is the one fed to the prescaler to generate the Serial Clock (Sclock).
|
||||
The PRESDIV field of CTRL(control register) controls a prescaler that
|
||||
generates the Serial Clock (Sclock), whose period defines the
|
||||
time quantum used to compose the CAN waveform.
|
||||
|
||||
Can Engine Clock Source
|
||||
There are two sources for CAN clock
|
||||
- Platform Clock It represents the bus clock
|
||||
- Oscillator Clock
|
||||
|
||||
Peripheral Clock (PLL)
|
||||
--------------
|
||||
|
|
||||
--------- -------------
|
||||
| |CPI Clock | Prescaler | Sclock
|
||||
| |---------------->| (1.. 256) |------------>
|
||||
--------- -------------
|
||||
| |
|
||||
-------------- ---------------------CLK_SRC
|
||||
Oscillator Clock
|
||||
|
||||
- fsl,flexcan-clock-source : CAN Engine Clock Source.This property selects
|
||||
the peripheral clock. PLL clock is fed to the
|
||||
prescaler to generate the Serial Clock (Sclock).
|
||||
Valid values are "oscillator" and "platform"
|
||||
"oscillator": CAN engine clock source is oscillator clock.
|
||||
"platform" The CAN engine clock source is the bus clock
|
||||
(platform clock).
|
||||
|
||||
- fsl,flexcan-clock-divider : for the reference and system clock, an additional
|
||||
clock divider can be specified.
|
||||
- clock-frequency: frequency required to calculate the bitrate for FlexCAN.
|
||||
|
||||
Note:
|
||||
- v1.0 of flexcan-v1.0 represent the IP block version for P1010 SOC.
|
||||
- P1010 does not have oscillator as the Clock Source.So the default
|
||||
Clock Source is platform clock.
|
||||
Examples:
|
||||
|
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can0@1c000 {
|
||||
compatible = "fsl,flexcan-v1.0";
|
||||
reg = <0x1c000 0x1000>;
|
||||
interrupts = <48 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,flexcan-clock-source = "platform";
|
||||
fsl,flexcan-clock-divider = <2>;
|
||||
clock-frequency = <fixed by u-boot>;
|
||||
};
|
||||
76
Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
Normal file
76
Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
Normal file
@ -0,0 +1,76 @@
|
||||
Integrated Flash Controller
|
||||
|
||||
Properties:
|
||||
- name : Should be ifc
|
||||
- compatible : should contain "fsl,ifc". The version of the integrated
|
||||
flash controller can be found in the IFC_REV register at
|
||||
offset zero.
|
||||
|
||||
- #address-cells : Should be either two or three. The first cell is the
|
||||
chipselect number, and the remaining cells are the
|
||||
offset into the chipselect.
|
||||
- #size-cells : Either one or two, depending on how large each chipselect
|
||||
can be.
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts : IFC has two interrupts. The first one is the "common"
|
||||
interrupt(CM_EVTER_STAT), and second is the NAND interrupt
|
||||
(NAND_EVTER_STAT).
|
||||
|
||||
- ranges : Each range corresponds to a single chipselect, and covers
|
||||
the entire access window as configured.
|
||||
|
||||
Child device nodes describe the devices connected to IFC such as NOR (e.g.
|
||||
cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
|
||||
like FPGAs, CPLDs, etc.
|
||||
|
||||
Example:
|
||||
|
||||
ifc@ffe1e000 {
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0 0xffe1e000 0 0x2000>;
|
||||
interrupts = <16 2 19 2>;
|
||||
|
||||
/* NOR, NAND Flashes and CPLD on board */
|
||||
ranges = <0x0 0x0 0x0 0xee000000 0x02000000
|
||||
0x1 0x0 0x0 0xffa00000 0x00010000
|
||||
0x3 0x0 0x0 0xffb00000 0x00020000>;
|
||||
|
||||
flash@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x2000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
|
||||
partition@0 {
|
||||
/* 32MB for user data */
|
||||
reg = <0x0 0x02000000>;
|
||||
label = "NOR Data";
|
||||
};
|
||||
};
|
||||
|
||||
flash@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x1 0x0 0x10000>;
|
||||
|
||||
partition@0 {
|
||||
/* This location must not be altered */
|
||||
/* 1MB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "NAND U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
cpld@3,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1010rdb-cpld";
|
||||
reg = <0x3 0x0 0x000001f>;
|
||||
};
|
||||
};
|
||||
38
Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt
Normal file
38
Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt
Normal file
@ -0,0 +1,38 @@
|
||||
* Freescale MPIC timers
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,mpic-global-timer"
|
||||
|
||||
- reg : Contains two regions. The first is the main timer register bank
|
||||
(GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control
|
||||
register (TCRx) for the group.
|
||||
|
||||
- fsl,available-ranges: use <start count> style section to define which
|
||||
timer interrupts can be used. This property is optional; without this,
|
||||
all timers within the group can be used.
|
||||
|
||||
- interrupts: one interrupt per timer in the group, in order, starting
|
||||
with timer zero. If timer-available-ranges is present, only the
|
||||
interrupts that correspond to available timers shall be present.
|
||||
|
||||
Example:
|
||||
/* Note that this requires #interrupt-cells to be 4 */
|
||||
timer0: timer@41100 {
|
||||
compatible = "fsl,mpic-global-timer";
|
||||
reg = <0x41100 0x100 0x41300 4>;
|
||||
|
||||
/* Another AMP partition is using timers 0 and 1 */
|
||||
fsl,available-ranges = <2 2>;
|
||||
|
||||
interrupts = <2 0 3 0
|
||||
3 0 3 0>;
|
||||
};
|
||||
|
||||
timer1: timer@42100 {
|
||||
compatible = "fsl,mpic-global-timer";
|
||||
reg = <0x42100 0x100 0x42300 4>;
|
||||
interrupts = <4 0 3 0
|
||||
5 0 3 0
|
||||
6 0 3 0
|
||||
7 0 3 0>;
|
||||
};
|
||||
@ -190,7 +190,7 @@ EXAMPLE 4
|
||||
*/
|
||||
timer0: timer@41100 {
|
||||
compatible = "fsl,mpic-global-timer";
|
||||
reg = <0x41100 0x100>;
|
||||
reg = <0x41100 0x100 0x41300 4>;
|
||||
interrupts = <0 0 3 0
|
||||
1 0 3 0
|
||||
2 0 3 0
|
||||
|
||||
@ -193,6 +193,12 @@ config SYS_SUPPORTS_APM_EMULATION
|
||||
default y if PMAC_APM_EMU
|
||||
bool
|
||||
|
||||
config EPAPR_BOOT
|
||||
bool
|
||||
help
|
||||
Used to allow a board to specify it wants an ePAPR compliant wrapper.
|
||||
default n
|
||||
|
||||
config DEFAULT_UIMAGE
|
||||
bool
|
||||
help
|
||||
|
||||
@ -267,6 +267,11 @@ config PPC_EARLY_DEBUG_USBGECKO
|
||||
Select this to enable early debugging for Nintendo GameCube/Wii
|
||||
consoles via an external USB Gecko adapter.
|
||||
|
||||
config PPC_EARLY_DEBUG_WSP
|
||||
bool "Early debugging via WSP's internal UART"
|
||||
depends on PPC_WSP
|
||||
select PPC_UDBG_16550
|
||||
|
||||
endchoice
|
||||
|
||||
config PPC_EARLY_DEBUG_44x_PHYSLOW
|
||||
|
||||
@ -69,7 +69,8 @@ src-wlib := string.S crt0.S crtsavres.S stdio.c main.c \
|
||||
cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \
|
||||
fsl-soc.c mpc8xx.c pq2.c ugecon.c
|
||||
src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c \
|
||||
cuboot-ebony.c cuboot-hotfoot.c treeboot-ebony.c prpmc2800.c \
|
||||
cuboot-ebony.c cuboot-hotfoot.c epapr.c treeboot-ebony.c \
|
||||
prpmc2800.c \
|
||||
ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
|
||||
cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \
|
||||
cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
|
||||
@ -127,7 +128,7 @@ quiet_cmd_bootas = BOOTAS $@
|
||||
cmd_bootas = $(CROSS32CC) -Wp,-MD,$(depfile) $(BOOTAFLAGS) -c -o $@ $<
|
||||
|
||||
quiet_cmd_bootar = BOOTAR $@
|
||||
cmd_bootar = $(CROSS32AR) -cr $@.$$$$ $(filter-out FORCE,$^); mv $@.$$$$ $@
|
||||
cmd_bootar = $(CROSS32AR) -cr$(KBUILD_ARFLAGS) $@.$$$$ $(filter-out FORCE,$^); mv $@.$$$$ $@
|
||||
|
||||
$(obj-libfdt): $(obj)/%.o: $(srctree)/scripts/dtc/libfdt/%.c FORCE
|
||||
$(call if_changed_dep,bootcc)
|
||||
@ -182,6 +183,7 @@ image-$(CONFIG_PPC_HOLLY) += dtbImage.holly
|
||||
image-$(CONFIG_PPC_PRPMC2800) += dtbImage.prpmc2800
|
||||
image-$(CONFIG_PPC_ISERIES) += zImage.iseries
|
||||
image-$(CONFIG_DEFAULT_UIMAGE) += uImage
|
||||
image-$(CONFIG_EPAPR_BOOT) += zImage.epapr
|
||||
|
||||
#
|
||||
# Targets which embed a device tree blob
|
||||
|
||||
@ -6,16 +6,28 @@
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* NOTE: this code runs in 32 bit mode and is packaged as ELF32.
|
||||
* NOTE: this code runs in 32 bit mode, is position-independent,
|
||||
* and is packaged as ELF32.
|
||||
*/
|
||||
|
||||
#include "ppc_asm.h"
|
||||
|
||||
.text
|
||||
/* a procedure descriptor used when booting this as a COFF file */
|
||||
/* A procedure descriptor used when booting this as a COFF file.
|
||||
* When making COFF, this comes first in the link and we're
|
||||
* linked at 0x500000.
|
||||
*/
|
||||
.globl _zimage_start_opd
|
||||
_zimage_start_opd:
|
||||
.long _zimage_start, 0, 0, 0
|
||||
.long 0x500000, 0, 0, 0
|
||||
|
||||
p_start: .long _start
|
||||
p_etext: .long _etext
|
||||
p_bss_start: .long __bss_start
|
||||
p_end: .long _end
|
||||
|
||||
.weak _platform_stack_top
|
||||
p_pstack: .long _platform_stack_top
|
||||
|
||||
.weak _zimage_start
|
||||
.globl _zimage_start
|
||||
@ -24,37 +36,65 @@ _zimage_start:
|
||||
_zimage_start_lib:
|
||||
/* Work out the offset between the address we were linked at
|
||||
and the address where we're running. */
|
||||
bl 1f
|
||||
1: mflr r0
|
||||
lis r9,1b@ha
|
||||
addi r9,r9,1b@l
|
||||
subf. r0,r9,r0
|
||||
beq 3f /* if running at same address as linked */
|
||||
bl .+4
|
||||
p_base: mflr r10 /* r10 now points to runtime addr of p_base */
|
||||
/* grab the link address of the dynamic section in r11 */
|
||||
addis r11,r10,(_GLOBAL_OFFSET_TABLE_-p_base)@ha
|
||||
lwz r11,(_GLOBAL_OFFSET_TABLE_-p_base)@l(r11)
|
||||
cmpwi r11,0
|
||||
beq 3f /* if not linked -pie */
|
||||
/* get the runtime address of the dynamic section in r12 */
|
||||
.weak __dynamic_start
|
||||
addis r12,r10,(__dynamic_start-p_base)@ha
|
||||
addi r12,r12,(__dynamic_start-p_base)@l
|
||||
subf r11,r11,r12 /* runtime - linktime offset */
|
||||
|
||||
/* The .got2 section contains a list of addresses, so add
|
||||
the address offset onto each entry. */
|
||||
lis r9,__got2_start@ha
|
||||
addi r9,r9,__got2_start@l
|
||||
lis r8,__got2_end@ha
|
||||
addi r8,r8,__got2_end@l
|
||||
subf. r8,r9,r8
|
||||
/* The dynamic section contains a series of tagged entries.
|
||||
* We need the RELA and RELACOUNT entries. */
|
||||
RELA = 7
|
||||
RELACOUNT = 0x6ffffff9
|
||||
li r9,0
|
||||
li r0,0
|
||||
9: lwz r8,0(r12) /* get tag */
|
||||
cmpwi r8,0
|
||||
beq 10f /* end of list */
|
||||
cmpwi r8,RELA
|
||||
bne 11f
|
||||
lwz r9,4(r12) /* get RELA pointer in r9 */
|
||||
b 12f
|
||||
11: addis r8,r8,(-RELACOUNT)@ha
|
||||
cmpwi r8,RELACOUNT@l
|
||||
bne 12f
|
||||
lwz r0,4(r12) /* get RELACOUNT value in r0 */
|
||||
12: addi r12,r12,8
|
||||
b 9b
|
||||
|
||||
/* The relocation section contains a list of relocations.
|
||||
* We now do the R_PPC_RELATIVE ones, which point to words
|
||||
* which need to be initialized with addend + offset.
|
||||
* The R_PPC_RELATIVE ones come first and there are RELACOUNT
|
||||
* of them. */
|
||||
10: /* skip relocation if we don't have both */
|
||||
cmpwi r0,0
|
||||
beq 3f
|
||||
srwi. r8,r8,2
|
||||
mtctr r8
|
||||
add r9,r0,r9
|
||||
2: lwz r8,0(r9)
|
||||
add r8,r8,r0
|
||||
stw r8,0(r9)
|
||||
addi r9,r9,4
|
||||
cmpwi r9,0
|
||||
beq 3f
|
||||
|
||||
add r9,r9,r11 /* Relocate RELA pointer */
|
||||
mtctr r0
|
||||
2: lbz r0,4+3(r9) /* ELF32_R_INFO(reloc->r_info) */
|
||||
cmpwi r0,22 /* R_PPC_RELATIVE */
|
||||
bne 3f
|
||||
lwz r12,0(r9) /* reloc->r_offset */
|
||||
lwz r0,8(r9) /* reloc->r_addend */
|
||||
add r0,r0,r11
|
||||
stwx r0,r11,r12
|
||||
addi r9,r9,12
|
||||
bdnz 2b
|
||||
|
||||
/* Do a cache flush for our text, in case the loader didn't */
|
||||
3: lis r9,_start@ha
|
||||
addi r9,r9,_start@l
|
||||
add r9,r0,r9
|
||||
lis r8,_etext@ha
|
||||
addi r8,r8,_etext@l
|
||||
add r8,r0,r8
|
||||
3: lwz r9,p_start-p_base(r10) /* note: these are relocated now */
|
||||
lwz r8,p_etext-p_base(r10)
|
||||
4: dcbf r0,r9
|
||||
icbi r0,r9
|
||||
addi r9,r9,0x20
|
||||
@ -64,27 +104,19 @@ _zimage_start_lib:
|
||||
isync
|
||||
|
||||
/* Clear the BSS */
|
||||
lis r9,__bss_start@ha
|
||||
addi r9,r9,__bss_start@l
|
||||
add r9,r0,r9
|
||||
lis r8,_end@ha
|
||||
addi r8,r8,_end@l
|
||||
add r8,r0,r8
|
||||
li r10,0
|
||||
5: stw r10,0(r9)
|
||||
lwz r9,p_bss_start-p_base(r10)
|
||||
lwz r8,p_end-p_base(r10)
|
||||
li r0,0
|
||||
5: stw r0,0(r9)
|
||||
addi r9,r9,4
|
||||
cmplw cr0,r9,r8
|
||||
blt 5b
|
||||
|
||||
/* Possibly set up a custom stack */
|
||||
.weak _platform_stack_top
|
||||
lis r8,_platform_stack_top@ha
|
||||
addi r8,r8,_platform_stack_top@l
|
||||
lwz r8,p_pstack-p_base(r10)
|
||||
cmpwi r8,0
|
||||
beq 6f
|
||||
add r8,r0,r8
|
||||
lwz r1,0(r8)
|
||||
add r1,r0,r1
|
||||
li r0,0
|
||||
stwu r0,-16(r1) /* establish a stack frame */
|
||||
6:
|
||||
|
||||
@ -9,12 +9,11 @@
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "p1020si.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P1020";
|
||||
model = "fsl,P1020RDB";
|
||||
compatible = "fsl,P1020RDB";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
@ -26,34 +25,11 @@
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P1020@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,P1020@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
localbus@ffe05000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xffe05000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
|
||||
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
|
||||
@ -165,88 +141,14 @@
|
||||
};
|
||||
|
||||
soc@ffe00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p1020-immr", "simple-bus";
|
||||
ranges = <0x0 0x0 0xffe00000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p1020-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p1020-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,espi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <59 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
mode = "cpu";
|
||||
|
||||
fsl_m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
@ -294,66 +196,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
gpio: gpio-controller@f000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x100>;
|
||||
interrupts = <47 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p1020-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,etsec2-mdio";
|
||||
reg = <0x24000 0x1000 0xb0030 0x4>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
@ -369,10 +212,6 @@
|
||||
};
|
||||
|
||||
mdio@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,etsec2-tbi";
|
||||
reg = <0x25000 0x1000 0xb1030 0x4>;
|
||||
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
@ -381,97 +220,25 @@
|
||||
};
|
||||
|
||||
enet0: ethernet@b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupt-parent = <&mpic>;
|
||||
fixed-link = <1 1 1000 0 0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
queue-group@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb0000 0x1000>;
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
};
|
||||
|
||||
queue-group@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb4000 0x1000>;
|
||||
interrupts = <17 2 18 2 24 2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@b1000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy0>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
queue-group@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb1000 0x1000>;
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
};
|
||||
|
||||
queue-group@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb5000 0x1000>;
|
||||
interrupts = <51 2 52 2 67 2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ethernet@b2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
queue-group@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb2000 0x1000>;
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
};
|
||||
|
||||
queue-group@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb6000 0x1000>;
|
||||
interrupts = <25 2 26 2 27 2>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x22000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <28 0x2>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
@ -481,82 +248,23 @@
|
||||
it enables USB2. OTOH, U-Boot does create a new node
|
||||
when there isn't any. So, just comment it out.
|
||||
usb@23000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <46 0x2>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
*/
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,p1020-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <72 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
|
||||
"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xbfe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,p1020-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,p1020-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe09000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe09000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
@ -573,18 +281,16 @@
|
||||
};
|
||||
|
||||
pci1: pcie@ffe0a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe0a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
|
||||
213
arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
Normal file
213
arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
Normal file
@ -0,0 +1,213 @@
|
||||
/*
|
||||
* P1020 RDB Core0 Device Tree Source in CAMP mode.
|
||||
*
|
||||
* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
|
||||
* can be shared, all the other devices must be assigned to one core only.
|
||||
* This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb,
|
||||
* eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
|
||||
*
|
||||
* Please note to add "-b 0" for core0's dts compiling.
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/include/ "p1020si.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P1020RDB";
|
||||
compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
|
||||
|
||||
aliases {
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
serial0 = &serial0;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
PowerPC,P1020@1 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
localbus@ffe05000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
soc@ffe00000 {
|
||||
i2c@3000 {
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
fsl_m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,espi-flash";
|
||||
reg = <0>;
|
||||
linux,modalias = "fsl_m25p80";
|
||||
spi-max-frequency = <40000000>;
|
||||
|
||||
partition@0 {
|
||||
/* 512KB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00080000>;
|
||||
label = "SPI (RO) U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
/* 512KB for DTB Image */
|
||||
reg = <0x00080000 0x00080000>;
|
||||
label = "SPI (RO) DTB Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
/* 4MB for Linux Kernel Image */
|
||||
reg = <0x00100000 0x00400000>;
|
||||
label = "SPI (RO) Linux Kernel Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@500000 {
|
||||
/* 4MB for Compressed RFS Image */
|
||||
reg = <0x00500000 0x00400000>;
|
||||
label = "SPI (RO) Compressed RFS Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@900000 {
|
||||
/* 7MB for JFFS2 based RFS */
|
||||
reg = <0x00900000 0x00700000>;
|
||||
label = "SPI (RW) JFFS2 RFS";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24000 {
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <2 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@25000 {
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@b0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet1: ethernet@b1000 {
|
||||
phy-handle = <&phy0>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
enet2: ethernet@b2000 {
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
/* USB2 is shared with localbus, so it must be disabled
|
||||
by default. We can't put 'status = "disabled";' here
|
||||
since U-Boot doesn't clear the status property when
|
||||
it enables USB2. OTOH, U-Boot does create a new node
|
||||
when there isn't any. So, just comment it out.
|
||||
usb@23000 {
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
*/
|
||||
|
||||
mpic: pic@40000 {
|
||||
protected-sources = <
|
||||
42 29 30 34 /* serial1, enet0-queue-group0 */
|
||||
17 18 24 45 /* enet0-queue-group1, crypto */
|
||||
>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci0: pcie@ffe09000 {
|
||||
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0xa0000000
|
||||
0x2000000 0x0 0xa0000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ffe0a000 {
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0x80000000
|
||||
0x2000000 0x0 0x80000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
148
arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
Normal file
148
arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
Normal file
@ -0,0 +1,148 @@
|
||||
/*
|
||||
* P1020 RDB Core1 Device Tree Source in CAMP mode.
|
||||
*
|
||||
* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
|
||||
* can be shared, all the other devices must be assigned to one core only.
|
||||
* This dts allows core1 to have l2, eth0, crypto.
|
||||
*
|
||||
* Please note to add "-b 1" for core1's dts compiling.
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/include/ "p1020si.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P1020RDB";
|
||||
compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
serial0 = &serial1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
PowerPC,P1020@0 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
localbus@ffe05000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
soc@ffe00000 {
|
||||
ecm-law@0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio: gpio-controller@f000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio@24000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio@25000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@b0000 {
|
||||
fixed-link = <1 1 1000 0 0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
};
|
||||
|
||||
enet1: ethernet@b1000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet2: ethernet@b2000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
protected-sources = <
|
||||
16 /* ecm, mem, L2, pci0, pci1 */
|
||||
43 42 59 /* i2c, serial0, spi */
|
||||
47 63 62 /* gpio, tdm */
|
||||
20 21 22 23 /* dma */
|
||||
03 02 /* mdio */
|
||||
35 36 40 /* enet1-queue-group0 */
|
||||
51 52 67 /* enet1-queue-group1 */
|
||||
31 32 33 /* enet2-queue-group0 */
|
||||
25 26 27 /* enet2-queue-group1 */
|
||||
28 72 58 /* usb, sdhci, crypto */
|
||||
0xb0 0xb1 0xb2 /* message */
|
||||
0xb3 0xb4 0xb5
|
||||
0xb6 0xb7
|
||||
0xe0 0xe1 0xe2 /* msi */
|
||||
0xe3 0xe4 0xe5
|
||||
0xe6 0xe7 /* sdhci, crypto , pci */
|
||||
>;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci0: pcie@ffe09000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pci1: pcie@ffe0a000 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
377
arch/powerpc/boot/dts/p1020si.dtsi
Normal file
377
arch/powerpc/boot/dts/p1020si.dtsi
Normal file
@ -0,0 +1,377 @@
|
||||
/*
|
||||
* P1020si Device Tree Source
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
compatible = "fsl,P1020";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P1020@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,P1020@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
localbus@ffe05000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xffe05000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
soc@ffe00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p1020-immr", "simple-bus";
|
||||
ranges = <0x0 0x0 0xffe00000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p1020-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p1020-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,espi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <59 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
gpio: gpio-controller@f000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x100>;
|
||||
interrupts = <47 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p1020-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,etsec2-mdio";
|
||||
reg = <0x24000 0x1000 0xb0030 0x4>;
|
||||
|
||||
};
|
||||
|
||||
mdio@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,etsec2-tbi";
|
||||
reg = <0x25000 0x1000 0xb1030 0x4>;
|
||||
|
||||
};
|
||||
|
||||
enet0: ethernet@b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
queue-group@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb0000 0x1000>;
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
};
|
||||
|
||||
queue-group@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb4000 0x1000>;
|
||||
interrupts = <17 2 18 2 24 2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@b1000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
queue-group@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb1000 0x1000>;
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
};
|
||||
|
||||
queue-group@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb5000 0x1000>;
|
||||
interrupts = <51 2 52 2 67 2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ethernet@b2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
queue-group@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb2000 0x1000>;
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
};
|
||||
|
||||
queue-group@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb6000 0x1000>;
|
||||
interrupts = <25 2 26 2 27 2>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x22000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <28 0x2>;
|
||||
};
|
||||
|
||||
/* USB2 is shared with localbus, so it must be disabled
|
||||
by default. We can't put 'status = "disabled";' here
|
||||
since U-Boot doesn't clear the status property when
|
||||
it enables USB2. OTOH, U-Boot does create a new node
|
||||
when there isn't any. So, just comment it out.
|
||||
usb@23000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <46 0x2>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
*/
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,p1020-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <72 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
|
||||
"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xbfe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,p1020-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,p1020-guts","fsl,p2020-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe09000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe09000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
pci1: pcie@ffe0a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe0a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
};
|
||||
@ -52,7 +52,7 @@
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xffe05000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupts = <19 2 0 0>;
|
||||
|
||||
ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
|
||||
0x1 0x0 0xf 0xe0000000 0x08000000
|
||||
@ -157,7 +157,7 @@
|
||||
* IRQ8 is generated if the "EVENT" switch is pressed
|
||||
* and PX_CTL[EVESEL] is set to 00.
|
||||
*/
|
||||
interrupts = <8 8>;
|
||||
interrupts = <8 8 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -178,13 +178,13 @@
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p1022-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p1022-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <16 2>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
@ -193,7 +193,7 @@
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupts = <43 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
@ -203,7 +203,7 @@
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupts = <43 2 0 0>;
|
||||
dfsrr;
|
||||
|
||||
wm8776:codec@1a {
|
||||
@ -220,7 +220,7 @@
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupts = <42 2 0 0>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
@ -229,7 +229,7 @@
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupts = <42 2 0 0>;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
@ -238,7 +238,7 @@
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,espi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <59 0x2>;
|
||||
interrupts = <59 0x2 0 0>;
|
||||
espi,num-ss-bits = <4>;
|
||||
mode = "cpu";
|
||||
|
||||
@ -275,7 +275,7 @@
|
||||
compatible = "fsl,mpc8610-ssi";
|
||||
cell-index = <0>;
|
||||
reg = <0x15000 0x100>;
|
||||
interrupts = <75 2>;
|
||||
interrupts = <75 2 0 0>;
|
||||
fsl,mode = "i2s-slave";
|
||||
codec-handle = <&wm8776>;
|
||||
fsl,playback-dma = <&dma00>;
|
||||
@ -294,25 +294,25 @@
|
||||
compatible = "fsl,ssi-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupts = <76 2>;
|
||||
interrupts = <76 2 0 0>;
|
||||
};
|
||||
dma01: dma-channel@80 {
|
||||
compatible = "fsl,ssi-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupts = <77 2>;
|
||||
interrupts = <77 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupts = <78 2>;
|
||||
interrupts = <78 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupts = <79 2>;
|
||||
interrupts = <79 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -320,7 +320,7 @@
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x100>;
|
||||
interrupts = <47 0x2>;
|
||||
interrupts = <47 0x2 0 0>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
@ -329,7 +329,7 @@
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2, 256K
|
||||
interrupts = <16 2>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
@ -343,25 +343,25 @@
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupts = <20 2>;
|
||||
interrupts = <20 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupts = <21 2>;
|
||||
interrupts = <21 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupts = <22 2>;
|
||||
interrupts = <22 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupts = <23 2>;
|
||||
interrupts = <23 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -370,7 +370,7 @@
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x22000 0x1000>;
|
||||
interrupts = <28 0x2>;
|
||||
interrupts = <28 0x2 0 0>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
@ -381,11 +381,11 @@
|
||||
reg = <0x24000 0x1000 0xb0030 0x4>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupts = <3 1>;
|
||||
interrupts = <3 1 0 0>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupts = <9 1>;
|
||||
interrupts = <9 1 0 0>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
};
|
||||
@ -416,13 +416,13 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xB0000 0x1000>;
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
|
||||
};
|
||||
queue-group@1{
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xB4000 0x1000>;
|
||||
interrupts = <17 2 18 2 24 2>;
|
||||
interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -443,20 +443,20 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xB1000 0x1000>;
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
|
||||
};
|
||||
queue-group@1{
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xB5000 0x1000>;
|
||||
interrupts = <51 2 52 2 67 2>;
|
||||
interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,p1022-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <72 0x2>;
|
||||
interrupts = <72 0x2 0 0>;
|
||||
fsl,sdhci-auto-cmd12;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
@ -467,7 +467,7 @@
|
||||
"fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
|
||||
"fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupts = <45 2 0 0 58 2 0 0>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x97c>;
|
||||
@ -478,14 +478,14 @@
|
||||
compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
|
||||
reg = <0x18000 0x1000>;
|
||||
cell-index = <1>;
|
||||
interrupts = <74 0x2>;
|
||||
interrupts = <74 0x2 0 0>;
|
||||
};
|
||||
|
||||
sata@19000 {
|
||||
compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
|
||||
reg = <0x19000 0x1000>;
|
||||
cell-index = <2>;
|
||||
interrupts = <41 0x2>;
|
||||
interrupts = <41 0x2 0 0>;
|
||||
};
|
||||
|
||||
power@e0070{
|
||||
@ -496,21 +496,33 @@
|
||||
display@10000 {
|
||||
compatible = "fsl,diu", "fsl,p1022-diu";
|
||||
reg = <0x10000 1000>;
|
||||
interrupts = <64 2>;
|
||||
interrupts = <64 2 0 0>;
|
||||
};
|
||||
|
||||
timer@41100 {
|
||||
compatible = "fsl,mpic-global-timer";
|
||||
reg = <0x41100 0x204>;
|
||||
interrupts = <0xf7 0x2>;
|
||||
reg = <0x41100 0x100 0x41300 4>;
|
||||
interrupts = <0 0 3 0
|
||||
1 0 3 0
|
||||
2 0 3 0
|
||||
3 0 3 0>;
|
||||
};
|
||||
|
||||
timer@42100 {
|
||||
compatible = "fsl,mpic-global-timer";
|
||||
reg = <0x42100 0x100 0x42300 4>;
|
||||
interrupts = <4 0 3 0
|
||||
5 0 3 0
|
||||
6 0 3 0
|
||||
7 0 3 0>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
compatible = "fsl,mpic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
@ -519,14 +531,14 @@
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
0xe0 0 0 0
|
||||
0xe1 0 0 0
|
||||
0xe2 0 0 0
|
||||
0xe3 0 0 0
|
||||
0xe4 0 0 0
|
||||
0xe5 0 0 0
|
||||
0xe6 0 0 0
|
||||
0xe7 0 0 0>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
@ -547,7 +559,7 @@
|
||||
ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2>;
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
@ -582,7 +594,7 @@
|
||||
ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2>;
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
@ -618,7 +630,7 @@
|
||||
ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2>;
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* P2020 DS Device Tree Source
|
||||
*
|
||||
* Copyright 2009 Freescale Semiconductor Inc.
|
||||
* Copyright 2009-2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
@ -9,12 +9,11 @@
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "p2020si.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P2020";
|
||||
model = "fsl,P2020DS";
|
||||
compatible = "fsl,P2020DS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
@ -27,35 +26,13 @@
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P2020@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,P2020@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
localbus@ffe05000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xffe05000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
|
||||
0x1 0x0 0x0 0xe0000000 0x08000000
|
||||
0x2 0x0 0x0 0xffa00000 0x00040000
|
||||
@ -158,352 +135,77 @@
|
||||
};
|
||||
|
||||
soc@ffe00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p2020-immr", "simple-bus";
|
||||
ranges = <0x0 0 0xffe00000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p2020-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p2020-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
compatible = "fsl,espi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <59 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
dma@c300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eloplus-dma";
|
||||
reg = <0xc300 0x4>;
|
||||
ranges = <0x0 0xc100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <76 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <77 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <78 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <79 2>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio: gpio-controller@f000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x100>;
|
||||
interrupts = <47 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p2020-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512k
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x22000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <28 0x2>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
mdio@24520 {
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
};
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
mdio@25520 {
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
mdio@26520 {
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <72 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
|
||||
"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xbfe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,p2020-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe08000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe08000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
@ -528,18 +230,8 @@
|
||||
};
|
||||
|
||||
pci1: pcie@ffe09000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe09000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <25 2>;
|
||||
interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
|
||||
@ -667,18 +359,8 @@
|
||||
};
|
||||
|
||||
pci2: pcie@ffe0a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe0a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
|
||||
@ -9,12 +9,11 @@
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "p2020si.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P2020";
|
||||
model = "fsl,P2020RDB";
|
||||
compatible = "fsl,P2020RDB";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
@ -26,34 +25,11 @@
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P2020@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,P2020@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
localbus@ffe05000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xffe05000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
/* NOR and NAND Flashes */
|
||||
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
|
||||
@ -165,90 +141,16 @@
|
||||
};
|
||||
|
||||
soc@ffe00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p2020-immr", "simple-bus";
|
||||
ranges = <0x0 0x0 0xffe00000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p2020-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p2020-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
spi@7000 {
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,espi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <59 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
mode = "cpu";
|
||||
|
||||
fsl_m25p80@0 {
|
||||
fsl_m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,espi-flash";
|
||||
@ -294,254 +196,68 @@
|
||||
};
|
||||
};
|
||||
|
||||
dma@c300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eloplus-dma";
|
||||
reg = <0xc300 0x4>;
|
||||
ranges = <0x0 0xc100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <76 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <77 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <78 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <79 2>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio: gpio-controller@f000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x100>;
|
||||
interrupts = <47 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p2020-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2,512K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x22000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <28 0x2>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@25520 {
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
mdio@26520 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fixed-link = <1 1 1000 0 0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <72 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
|
||||
"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xbfe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,p2020-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,p2020-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe09000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe09000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
pci0: pcie@ffe08000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pci1: pcie@ffe09000 {
|
||||
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <25 2>;
|
||||
pcie@0 {
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
@ -556,19 +272,17 @@
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ffe0a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe0a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
pci2: pcie@ffe0a000 {
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
|
||||
@ -14,12 +14,11 @@
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "p2020si.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P2020";
|
||||
model = "fsl,P2020RDB";
|
||||
compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet1 = &enet1;
|
||||
@ -29,91 +28,33 @@
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P2020@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
PowerPC,P2020@1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
localbus@ffe05000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
soc@ffe00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p2020-immr", "simple-bus";
|
||||
ranges = <0x0 0x0 0xffe00000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p2020-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p2020-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
serial1: serial@4600 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,espi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <59 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
mode = "cpu";
|
||||
|
||||
fsl_m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
@ -161,76 +102,15 @@
|
||||
};
|
||||
};
|
||||
|
||||
gpio: gpio-controller@f000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x100>;
|
||||
interrupts = <47 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p2020-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2,512K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
dma@c300 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x22000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <28 0x2>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
@ -245,29 +125,21 @@
|
||||
};
|
||||
|
||||
mdio@25520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x26520 0x20>;
|
||||
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
mdio@26520 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "sgmii";
|
||||
@ -275,49 +147,12 @@
|
||||
};
|
||||
|
||||
enet2: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <72 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
|
||||
"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xbfe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
protected-sources = <
|
||||
42 76 77 78 79 /* serial1 , dma2 */
|
||||
29 30 34 26 /* enet0, pci1 */
|
||||
@ -326,26 +161,28 @@
|
||||
>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,p2020-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
msi@41600 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
};
|
||||
|
||||
pci0: pcie@ffe09000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe09000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
pci0: pcie@ffe08000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pci1: pcie@ffe09000 {
|
||||
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <25 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
@ -360,4 +197,8 @@
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pcie@ffe0a000 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@ -15,27 +15,21 @@
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "p2020si.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P2020";
|
||||
model = "fsl,P2020RDB";
|
||||
compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
serial0 = &serial0;
|
||||
serial0 = &serial1;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P2020@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
PowerPC,P2020@0 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@ -43,20 +37,37 @@
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
soc@ffe00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p2020-immr", "simple-bus";
|
||||
ranges = <0x0 0x0 0xffe00000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
localbus@ffe05000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial0: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
soc@ffe00000 {
|
||||
ecm-law@0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dma@c300 {
|
||||
@ -96,6 +107,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
gpio: gpio-controller@f000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p2020-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
@ -104,31 +119,49 @@
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio@25520 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio@26520 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fixed-link = <1 1 1000 0 0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet2: ethernet@26000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
protected-sources = <
|
||||
17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */
|
||||
16 20 21 22 23 28 /* L2, dma1, USB */
|
||||
@ -152,21 +185,32 @@
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci1: pcie@ffe0a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe0a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
pci0: pcie@ffe08000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pci1: pcie@ffe09000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pci2: pcie@ffe0a000 {
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
|
||||
382
arch/powerpc/boot/dts/p2020si.dtsi
Normal file
382
arch/powerpc/boot/dts/p2020si.dtsi
Normal file
@ -0,0 +1,382 @@
|
||||
/*
|
||||
* P2020 Device Tree Source
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
compatible = "fsl,P2020";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P2020@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,P2020@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
localbus@ffe05000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xffe05000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
soc@ffe00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p2020-immr", "simple-bus";
|
||||
ranges = <0x0 0x0 0xffe00000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p2020-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p2020-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,espi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <59 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@c300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eloplus-dma";
|
||||
reg = <0xc300 0x4>;
|
||||
ranges = <0x0 0xc100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <76 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <77 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <78 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <79 2>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio: gpio-controller@f000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x100>;
|
||||
interrupts = <47 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p2020-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2,512K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x22000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <28 0x2>;
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
};
|
||||
|
||||
mdio@25520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x26520 0x20>;
|
||||
};
|
||||
|
||||
mdio@26520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
};
|
||||
|
||||
enet2: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <72 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
|
||||
"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xbfe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,p2020-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,p2020-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe08000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe08000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
};
|
||||
|
||||
pci1: pcie@ffe09000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe09000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <25 2>;
|
||||
};
|
||||
|
||||
pci2: pcie@ffe0a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe0a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
};
|
||||
};
|
||||
66
arch/powerpc/boot/epapr.c
Normal file
66
arch/powerpc/boot/epapr.c
Normal file
@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Bootwrapper for ePAPR compliant firmwares
|
||||
*
|
||||
* Copyright 2010 David Gibson <david@gibson.dropbear.id.au>, IBM Corporation.
|
||||
*
|
||||
* Based on earlier bootwrappers by:
|
||||
* (c) Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp,\
|
||||
* and
|
||||
* Scott Wood <scottwood@freescale.com>
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "io.h"
|
||||
#include <libfdt.h>
|
||||
|
||||
BSS_STACK(4096);
|
||||
|
||||
#define EPAPR_SMAGIC 0x65504150
|
||||
#define EPAPR_EMAGIC 0x45504150
|
||||
|
||||
static unsigned epapr_magic;
|
||||
static unsigned long ima_size;
|
||||
static unsigned long fdt_addr;
|
||||
|
||||
static void platform_fixups(void)
|
||||
{
|
||||
if ((epapr_magic != EPAPR_EMAGIC)
|
||||
&& (epapr_magic != EPAPR_SMAGIC))
|
||||
fatal("r6 contained 0x%08x instead of ePAPR magic number\n",
|
||||
epapr_magic);
|
||||
|
||||
if (ima_size < (unsigned long)_end)
|
||||
printf("WARNING: Image loaded outside IMA!"
|
||||
" (_end=%p, ima_size=0x%lx)\n", _end, ima_size);
|
||||
if (ima_size < fdt_addr)
|
||||
printf("WARNING: Device tree address is outside IMA!"
|
||||
"(fdt_addr=0x%lx, ima_size=0x%lx)\n", fdt_addr,
|
||||
ima_size);
|
||||
if (ima_size < fdt_addr + fdt_totalsize((void *)fdt_addr))
|
||||
printf("WARNING: Device tree extends outside IMA!"
|
||||
" (fdt_addr=0x%lx, size=0x%x, ima_size=0x%lx\n",
|
||||
fdt_addr, fdt_totalsize((void *)fdt_addr), ima_size);
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
epapr_magic = r6;
|
||||
ima_size = r7;
|
||||
fdt_addr = r3;
|
||||
|
||||
/* FIXME: we should process reserve entries */
|
||||
|
||||
simple_alloc_init(_end, ima_size - (unsigned long)_end, 32, 64);
|
||||
|
||||
fdt_init((void *)fdt_addr);
|
||||
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
@ -39,6 +39,7 @@ dts=
|
||||
cacheit=
|
||||
binary=
|
||||
gzip=.gz
|
||||
pie=
|
||||
|
||||
# cross-compilation prefix
|
||||
CROSS=
|
||||
@ -157,9 +158,10 @@ pmac|chrp)
|
||||
platformo=$object/of.o
|
||||
;;
|
||||
coff)
|
||||
platformo=$object/of.o
|
||||
platformo="$object/crt0.o $object/of.o"
|
||||
lds=$object/zImage.coff.lds
|
||||
link_address='0x500000'
|
||||
pie=
|
||||
;;
|
||||
miboot|uboot)
|
||||
# miboot and U-boot want just the bare bits, not an ELF binary
|
||||
@ -208,6 +210,7 @@ ps3)
|
||||
ksection=.kernel:vmlinux.bin
|
||||
isection=.kernel:initrd
|
||||
link_address=''
|
||||
pie=
|
||||
;;
|
||||
ep88xc|ep405|ep8248e)
|
||||
platformo="$object/fixed-head.o $object/$platform.o"
|
||||
@ -244,6 +247,10 @@ gamecube|wii)
|
||||
treeboot-iss4xx-mpic)
|
||||
platformo="$object/treeboot-iss4xx.o"
|
||||
;;
|
||||
epapr)
|
||||
link_address='0x20000000'
|
||||
pie=-pie
|
||||
;;
|
||||
esac
|
||||
|
||||
vmz="$tmpdir/`basename \"$kernel\"`.$ext"
|
||||
@ -251,7 +258,7 @@ if [ -z "$cacheit" -o ! -f "$vmz$gzip" -o "$vmz$gzip" -ot "$kernel" ]; then
|
||||
${CROSS}objcopy $objflags "$kernel" "$vmz.$$"
|
||||
|
||||
if [ -n "$gzip" ]; then
|
||||
gzip -f -9 "$vmz.$$"
|
||||
gzip -n -f -9 "$vmz.$$"
|
||||
fi
|
||||
|
||||
if [ -n "$cacheit" ]; then
|
||||
@ -310,9 +317,9 @@ fi
|
||||
|
||||
if [ "$platform" != "miboot" ]; then
|
||||
if [ -n "$link_address" ] ; then
|
||||
text_start="-Ttext $link_address --defsym _start=$link_address"
|
||||
text_start="-Ttext $link_address"
|
||||
fi
|
||||
${CROSS}ld -m elf32ppc -T $lds $text_start -o "$ofile" \
|
||||
${CROSS}ld -m elf32ppc -T $lds $text_start $pie -o "$ofile" \
|
||||
$platformo $tmp $object/wrapper.a
|
||||
rm $tmp
|
||||
fi
|
||||
@ -336,7 +343,7 @@ coff)
|
||||
$objbin/hack-coff "$ofile"
|
||||
;;
|
||||
cuboot*)
|
||||
gzip -f -9 "$ofile"
|
||||
gzip -n -f -9 "$ofile"
|
||||
${MKIMAGE} -A ppc -O linux -T kernel -C gzip -a "$base" -e "$entry" \
|
||||
$uboot_version -d "$ofile".gz "$ofile"
|
||||
;;
|
||||
@ -383,6 +390,6 @@ ps3)
|
||||
|
||||
odir="$(dirname "$ofile.bin")"
|
||||
rm -f "$odir/otheros.bld"
|
||||
gzip --force -9 --stdout "$ofile.bin" > "$odir/otheros.bld"
|
||||
gzip -n --force -9 --stdout "$ofile.bin" > "$odir/otheros.bld"
|
||||
;;
|
||||
esac
|
||||
|
||||
@ -3,13 +3,13 @@ ENTRY(_zimage_start_opd)
|
||||
EXTERN(_zimage_start_opd)
|
||||
SECTIONS
|
||||
{
|
||||
_start = .;
|
||||
.text :
|
||||
{
|
||||
_start = .;
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
_etext = .;
|
||||
}
|
||||
_etext = .;
|
||||
. = ALIGN(4096);
|
||||
.data :
|
||||
{
|
||||
@ -17,9 +17,7 @@ SECTIONS
|
||||
*(.data*)
|
||||
*(__builtin_*)
|
||||
*(.sdata*)
|
||||
__got2_start = .;
|
||||
*(.got2)
|
||||
__got2_end = .;
|
||||
|
||||
_dtb_start = .;
|
||||
*(.kernel:dtb)
|
||||
|
||||
@ -3,49 +3,64 @@ ENTRY(_zimage_start)
|
||||
EXTERN(_zimage_start)
|
||||
SECTIONS
|
||||
{
|
||||
_start = .;
|
||||
.text :
|
||||
{
|
||||
_start = .;
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
_etext = .;
|
||||
}
|
||||
_etext = .;
|
||||
. = ALIGN(4096);
|
||||
.data :
|
||||
{
|
||||
*(.rodata*)
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
__got2_start = .;
|
||||
*(.got2)
|
||||
__got2_end = .;
|
||||
}
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.dynamic :
|
||||
{
|
||||
__dynamic_start = .;
|
||||
*(.dynamic)
|
||||
}
|
||||
.hash : { *(.hash) }
|
||||
.interp : { *(.interp) }
|
||||
.rela.dyn : { *(.rela*) }
|
||||
|
||||
. = ALIGN(8);
|
||||
_dtb_start = .;
|
||||
.kernel:dtb : { *(.kernel:dtb) }
|
||||
_dtb_end = .;
|
||||
.kernel:dtb :
|
||||
{
|
||||
_dtb_start = .;
|
||||
*(.kernel:dtb)
|
||||
_dtb_end = .;
|
||||
}
|
||||
|
||||
. = ALIGN(4096);
|
||||
_vmlinux_start = .;
|
||||
.kernel:vmlinux.strip : { *(.kernel:vmlinux.strip) }
|
||||
_vmlinux_end = .;
|
||||
.kernel:vmlinux.strip :
|
||||
{
|
||||
_vmlinux_start = .;
|
||||
*(.kernel:vmlinux.strip)
|
||||
_vmlinux_end = .;
|
||||
}
|
||||
|
||||
. = ALIGN(4096);
|
||||
_initrd_start = .;
|
||||
.kernel:initrd : { *(.kernel:initrd) }
|
||||
_initrd_end = .;
|
||||
.kernel:initrd :
|
||||
{
|
||||
_initrd_start = .;
|
||||
*(.kernel:initrd)
|
||||
_initrd_end = .;
|
||||
}
|
||||
|
||||
. = ALIGN(4096);
|
||||
_edata = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss)
|
||||
*(.bss)
|
||||
_edata = .;
|
||||
__bss_start = .;
|
||||
*(.sbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
_end = . ;
|
||||
}
|
||||
. = ALIGN(4096);
|
||||
_end = . ;
|
||||
}
|
||||
|
||||
@ -104,7 +104,6 @@ CONFIG_ROOT_NFS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
|
||||
@ -101,7 +101,6 @@ CONFIG_ROOT_NFS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
|
||||
@ -58,7 +58,6 @@ CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
|
||||
@ -59,7 +59,6 @@ CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
|
||||
@ -63,7 +63,6 @@ CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
|
||||
@ -168,7 +168,6 @@ CONFIG_MAC_PARTITION=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
|
||||
@ -132,8 +132,8 @@ CONFIG_NET_CLS_RSVP=m
|
||||
CONFIG_NET_CLS_RSVP6=m
|
||||
CONFIG_NET_CLS_IND=y
|
||||
CONFIG_BT=m
|
||||
CONFIG_BT_L2CAP=m
|
||||
CONFIG_BT_SCO=m
|
||||
CONFIG_BT_L2CAP=y
|
||||
CONFIG_BT_SCO=y
|
||||
CONFIG_BT_RFCOMM=m
|
||||
CONFIG_BT_RFCOMM_TTY=y
|
||||
CONFIG_BT_BNEP=m
|
||||
|
||||
@ -6,10 +6,10 @@ CONFIG_NR_CPUS=2
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_SYSFS_DEPRECATED_V2=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_EXPERT=y
|
||||
@ -25,8 +25,32 @@ CONFIG_P5020_DS=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
# CONFIG_PCI is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=y
|
||||
CONFIG_NET_KEY=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IP_PNP_RARP=y
|
||||
CONFIG_NET_IPIP=y
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
CONFIG_ARPD=y
|
||||
CONFIG_INET_ESP=y
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IP_SCTP=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
@ -34,6 +58,9 @@ CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=131072
|
||||
CONFIG_MISC_DEVICES=y
|
||||
CONFIG_EEPROM_LEGACY=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
@ -64,22 +91,14 @@ CONFIG_NLS=y
|
||||
CONFIG_NLS_UTF8=m
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CRC_ITU_T=m
|
||||
CONFIG_LIBCRC32C=m
|
||||
CONFIG_FRAME_WARN=1024
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_VIRQ_DEBUG=y
|
||||
CONFIG_CRYPTO=y
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_MD5=y
|
||||
CONFIG_CRYPTO_SHA1=m
|
||||
CONFIG_CRYPTO_DES=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRYPTO_DEV_TALITOS=y
|
||||
|
||||
@ -204,7 +204,6 @@ CONFIG_CRC_T10DIF=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
|
||||
@ -206,7 +206,6 @@ CONFIG_CRC_T10DIF=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
|
||||
@ -171,7 +171,6 @@ CONFIG_MAC_PARTITION=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
|
||||
@ -112,8 +112,8 @@ CONFIG_IRDA_CACHE_LAST_LSAP=y
|
||||
CONFIG_IRDA_FAST_RR=y
|
||||
CONFIG_IRTTY_SIR=m
|
||||
CONFIG_BT=m
|
||||
CONFIG_BT_L2CAP=m
|
||||
CONFIG_BT_SCO=m
|
||||
CONFIG_BT_L2CAP=y
|
||||
CONFIG_BT_SCO=y
|
||||
CONFIG_BT_RFCOMM=m
|
||||
CONFIG_BT_RFCOMM_TTY=y
|
||||
CONFIG_BT_BNEP=m
|
||||
|
||||
@ -351,8 +351,8 @@ CONFIG_VLSI_FIR=m
|
||||
CONFIG_VIA_FIR=m
|
||||
CONFIG_MCS_FIR=m
|
||||
CONFIG_BT=m
|
||||
CONFIG_BT_L2CAP=m
|
||||
CONFIG_BT_SCO=m
|
||||
CONFIG_BT_L2CAP=y
|
||||
CONFIG_BT_SCO=y
|
||||
CONFIG_BT_RFCOMM=m
|
||||
CONFIG_BT_RFCOMM_TTY=y
|
||||
CONFIG_BT_BNEP=m
|
||||
|
||||
@ -52,8 +52,8 @@ CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_BT=m
|
||||
CONFIG_BT_L2CAP=m
|
||||
CONFIG_BT_SCO=m
|
||||
CONFIG_BT_L2CAP=y
|
||||
CONFIG_BT_SCO=y
|
||||
CONFIG_BT_RFCOMM=m
|
||||
CONFIG_BT_RFCOMM_TTY=y
|
||||
CONFIG_BT_BNEP=m
|
||||
|
||||
@ -146,12 +146,18 @@ CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_FC_ATTRS=y
|
||||
CONFIG_SCSI_SAS_ATTRS=m
|
||||
CONFIG_SCSI_CXGB3_ISCSI=m
|
||||
CONFIG_SCSI_CXGB4_ISCSI=m
|
||||
CONFIG_SCSI_BNX2_ISCSI=m
|
||||
CONFIG_SCSI_BNX2_ISCSI=m
|
||||
CONFIG_BE2ISCSI=m
|
||||
CONFIG_SCSI_IBMVSCSI=y
|
||||
CONFIG_SCSI_IBMVFC=m
|
||||
CONFIG_SCSI_SYM53C8XX_2=y
|
||||
CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0
|
||||
CONFIG_SCSI_IPR=y
|
||||
CONFIG_SCSI_QLA_FC=m
|
||||
CONFIG_SCSI_QLA_ISCSI=m
|
||||
CONFIG_SCSI_LPFC=m
|
||||
CONFIG_ATA=y
|
||||
# CONFIG_ATA_SFF is not set
|
||||
@ -197,6 +203,8 @@ CONFIG_S2IO=m
|
||||
CONFIG_MYRI10GE=m
|
||||
CONFIG_NETXEN_NIC=m
|
||||
CONFIG_MLX4_EN=m
|
||||
CONFIG_QLGE=m
|
||||
CONFIG_BE2NET=m
|
||||
CONFIG_PPP=m
|
||||
CONFIG_PPP_ASYNC=m
|
||||
CONFIG_PPP_SYNC_TTY=m
|
||||
|
||||
@ -157,6 +157,7 @@ extern const char *powerpc_base_platform;
|
||||
#define CPU_FTR_476_DD2 ASM_CONST(0x0000000000010000)
|
||||
#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
|
||||
#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
|
||||
#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x0000000000080000)
|
||||
#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
|
||||
#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
|
||||
#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
|
||||
@ -178,22 +179,18 @@ extern const char *powerpc_base_platform;
|
||||
#define LONG_ASM_CONST(x) 0
|
||||
#endif
|
||||
|
||||
#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
|
||||
#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
|
||||
#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
|
||||
|
||||
#define CPU_FTR_HVMODE_206 LONG_ASM_CONST(0x0000000800000000)
|
||||
#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000001000000000)
|
||||
#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
|
||||
#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
|
||||
#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
|
||||
#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
|
||||
#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
|
||||
#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
|
||||
#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
|
||||
#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
|
||||
#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
|
||||
#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
|
||||
#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
|
||||
#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
|
||||
#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
|
||||
#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
|
||||
#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
|
||||
#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
|
||||
@ -202,12 +199,14 @@ extern const char *powerpc_base_platform;
|
||||
#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0200000000000000)
|
||||
#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0400000000000000)
|
||||
#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000)
|
||||
#define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000000000000000)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
|
||||
CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
|
||||
CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
|
||||
#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
|
||||
|
||||
#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
|
||||
MMU_FTR_16M_PAGE)
|
||||
|
||||
/* We only set the altivec features if the kernel was compiled with altivec
|
||||
* support
|
||||
@ -387,7 +386,8 @@ extern const char *powerpc_base_platform;
|
||||
CPU_FTR_DBELL)
|
||||
#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
|
||||
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
|
||||
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)
|
||||
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
|
||||
CPU_FTR_DEBUG_LVL_EXC)
|
||||
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
|
||||
|
||||
/* 64-bit CPUs */
|
||||
@ -407,44 +407,45 @@ extern const char *powerpc_base_platform;
|
||||
#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
||||
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
||||
CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
||||
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
|
||||
CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS | \
|
||||
CPU_FTR_POPCNTB)
|
||||
CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
|
||||
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
|
||||
#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
||||
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
||||
CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
||||
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
|
||||
CPU_FTR_COHERENT_ICACHE | \
|
||||
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
|
||||
CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
|
||||
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
|
||||
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
|
||||
#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
||||
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
||||
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_HVMODE_206 |\
|
||||
CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
||||
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
|
||||
CPU_FTR_COHERENT_ICACHE | \
|
||||
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
|
||||
CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
|
||||
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)
|
||||
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
|
||||
CPU_FTR_ICSWX | CPU_FTR_CFAR)
|
||||
#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
||||
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
||||
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
||||
CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \
|
||||
CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
|
||||
CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
|
||||
CPU_FTR_UNALIGNED_LD_STD)
|
||||
#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
||||
CPU_FTR_PPCAS_ARCH_V2 | \
|
||||
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
|
||||
CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
|
||||
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
|
||||
CPU_FTR_PURR | CPU_FTR_REAL_LE)
|
||||
#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
|
||||
|
||||
#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
|
||||
CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
|
||||
|
||||
#ifdef __powerpc64__
|
||||
#ifdef CONFIG_PPC_BOOK3E
|
||||
#define CPU_FTRS_POSSIBLE (CPU_FTRS_E5500)
|
||||
#define CPU_FTRS_POSSIBLE (CPU_FTRS_E5500 | CPU_FTRS_A2)
|
||||
#else
|
||||
#define CPU_FTRS_POSSIBLE \
|
||||
(CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
|
||||
CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
|
||||
CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
|
||||
CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
|
||||
CPU_FTR_VSX)
|
||||
#endif
|
||||
#else
|
||||
enum {
|
||||
@ -487,7 +488,7 @@ enum {
|
||||
|
||||
#ifdef __powerpc64__
|
||||
#ifdef CONFIG_PPC_BOOK3E
|
||||
#define CPU_FTRS_ALWAYS (CPU_FTRS_E5500)
|
||||
#define CPU_FTRS_ALWAYS (CPU_FTRS_E5500 & CPU_FTRS_A2)
|
||||
#else
|
||||
#define CPU_FTRS_ALWAYS \
|
||||
(CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
|
||||
|
||||
@ -37,16 +37,16 @@ extern cpumask_t threads_core_mask;
|
||||
* This can typically be used for things like IPI for tlb invalidations
|
||||
* since those need to be done only once per core/TLB
|
||||
*/
|
||||
static inline cpumask_t cpu_thread_mask_to_cores(cpumask_t threads)
|
||||
static inline cpumask_t cpu_thread_mask_to_cores(const struct cpumask *threads)
|
||||
{
|
||||
cpumask_t tmp, res;
|
||||
int i;
|
||||
|
||||
res = CPU_MASK_NONE;
|
||||
cpumask_clear(&res);
|
||||
for (i = 0; i < NR_CPUS; i += threads_per_core) {
|
||||
cpus_shift_left(tmp, threads_core_mask, i);
|
||||
if (cpus_intersects(threads, tmp))
|
||||
cpu_set(i, res);
|
||||
cpumask_shift_left(&tmp, &threads_core_mask, i);
|
||||
if (cpumask_intersects(threads, &tmp))
|
||||
cpumask_set_cpu(i, &res);
|
||||
}
|
||||
return res;
|
||||
}
|
||||
@ -58,7 +58,7 @@ static inline int cpu_nr_cores(void)
|
||||
|
||||
static inline cpumask_t cpu_online_cores_map(void)
|
||||
{
|
||||
return cpu_thread_mask_to_cores(cpu_online_map);
|
||||
return cpu_thread_mask_to_cores(cpu_online_mask);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
|
||||
@ -27,9 +27,8 @@ enum ppc_dbell {
|
||||
PPC_G_DBELL_MC = 4, /* guest mcheck doorbell */
|
||||
};
|
||||
|
||||
extern void doorbell_message_pass(int target, int msg);
|
||||
extern void doorbell_cause_ipi(int cpu, unsigned long data);
|
||||
extern void doorbell_exception(struct pt_regs *regs);
|
||||
extern void doorbell_check_self(void);
|
||||
extern void doorbell_setup_this_cpu(void);
|
||||
|
||||
static inline void ppc_msgsnd(enum ppc_dbell type, u32 flags, u32 tag)
|
||||
|
||||
@ -52,6 +52,10 @@ extern struct ppc_emulated {
|
||||
#ifdef CONFIG_VSX
|
||||
struct ppc_emulated_entry vsx;
|
||||
#endif
|
||||
#ifdef CONFIG_PPC64
|
||||
struct ppc_emulated_entry mfdscr;
|
||||
struct ppc_emulated_entry mtdscr;
|
||||
#endif
|
||||
} ppc_emulated;
|
||||
|
||||
extern u32 ppc_warn_emulated;
|
||||
|
||||
@ -46,6 +46,7 @@
|
||||
#define EX_CCR 60
|
||||
#define EX_R3 64
|
||||
#define EX_LR 72
|
||||
#define EX_CFAR 80
|
||||
|
||||
/*
|
||||
* We're short on space and time in the exception prolog, so we can't
|
||||
@ -56,30 +57,40 @@
|
||||
#define LOAD_HANDLER(reg, label) \
|
||||
addi reg,reg,(label)-_stext; /* virt addr of handler ... */
|
||||
|
||||
#define EXCEPTION_PROLOG_1(area) \
|
||||
mfspr r13,SPRN_SPRG_PACA; /* get paca address into r13 */ \
|
||||
/* Exception register prefixes */
|
||||
#define EXC_HV H
|
||||
#define EXC_STD
|
||||
|
||||
#define EXCEPTION_PROLOG_1(area) \
|
||||
GET_PACA(r13); \
|
||||
std r9,area+EX_R9(r13); /* save r9 - r12 */ \
|
||||
std r10,area+EX_R10(r13); \
|
||||
std r11,area+EX_R11(r13); \
|
||||
std r12,area+EX_R12(r13); \
|
||||
mfspr r9,SPRN_SPRG_SCRATCH0; \
|
||||
BEGIN_FTR_SECTION_NESTED(66); \
|
||||
mfspr r10,SPRN_CFAR; \
|
||||
std r10,area+EX_CFAR(r13); \
|
||||
END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
|
||||
GET_SCRATCH0(r9); \
|
||||
std r9,area+EX_R13(r13); \
|
||||
mfcr r9
|
||||
|
||||
#define EXCEPTION_PROLOG_PSERIES_1(label) \
|
||||
#define __EXCEPTION_PROLOG_PSERIES_1(label, h) \
|
||||
ld r12,PACAKBASE(r13); /* get high part of &label */ \
|
||||
ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \
|
||||
mfspr r11,SPRN_SRR0; /* save SRR0 */ \
|
||||
mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
|
||||
LOAD_HANDLER(r12,label) \
|
||||
mtspr SPRN_SRR0,r12; \
|
||||
mfspr r12,SPRN_SRR1; /* and SRR1 */ \
|
||||
mtspr SPRN_SRR1,r10; \
|
||||
rfid; \
|
||||
mtspr SPRN_##h##SRR0,r12; \
|
||||
mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
|
||||
mtspr SPRN_##h##SRR1,r10; \
|
||||
h##rfid; \
|
||||
b . /* prevent speculative execution */
|
||||
#define EXCEPTION_PROLOG_PSERIES_1(label, h) \
|
||||
__EXCEPTION_PROLOG_PSERIES_1(label, h)
|
||||
|
||||
#define EXCEPTION_PROLOG_PSERIES(area, label) \
|
||||
#define EXCEPTION_PROLOG_PSERIES(area, label, h) \
|
||||
EXCEPTION_PROLOG_1(area); \
|
||||
EXCEPTION_PROLOG_PSERIES_1(label);
|
||||
EXCEPTION_PROLOG_PSERIES_1(label, h);
|
||||
|
||||
/*
|
||||
* The common exception prolog is used for all except a few exceptions
|
||||
@ -98,10 +109,11 @@
|
||||
beq- 1f; \
|
||||
ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
|
||||
1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
|
||||
bge- cr1,2f; /* abort if it is */ \
|
||||
b 3f; \
|
||||
2: li r1,(n); /* will be reloaded later */ \
|
||||
blt+ cr1,3f; /* abort if it is */ \
|
||||
li r1,(n); /* will be reloaded later */ \
|
||||
sth r1,PACA_TRAP_SAVE(r13); \
|
||||
std r3,area+EX_R3(r13); \
|
||||
addi r3,r13,area; /* r3 -> where regs are saved*/ \
|
||||
b bad_stack; \
|
||||
3: std r9,_CCR(r1); /* save CR in stackframe */ \
|
||||
std r11,_NIP(r1); /* save SRR0 in stackframe */ \
|
||||
@ -123,6 +135,10 @@
|
||||
std r9,GPR11(r1); \
|
||||
std r10,GPR12(r1); \
|
||||
std r11,GPR13(r1); \
|
||||
BEGIN_FTR_SECTION_NESTED(66); \
|
||||
ld r10,area+EX_CFAR(r13); \
|
||||
std r10,ORIG_GPR3(r1); \
|
||||
END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
|
||||
ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
|
||||
mflr r9; /* save LR in stackframe */ \
|
||||
std r9,_LINK(r1); \
|
||||
@ -143,57 +159,62 @@
|
||||
/*
|
||||
* Exception vectors.
|
||||
*/
|
||||
#define STD_EXCEPTION_PSERIES(n, label) \
|
||||
. = n; \
|
||||
#define STD_EXCEPTION_PSERIES(loc, vec, label) \
|
||||
. = loc; \
|
||||
.globl label##_pSeries; \
|
||||
label##_pSeries: \
|
||||
HMT_MEDIUM; \
|
||||
DO_KVM n; \
|
||||
mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \
|
||||
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
|
||||
DO_KVM vec; \
|
||||
SET_SCRATCH0(r13); /* save r13 */ \
|
||||
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, EXC_STD)
|
||||
|
||||
#define HSTD_EXCEPTION_PSERIES(n, label) \
|
||||
. = n; \
|
||||
.globl label##_pSeries; \
|
||||
label##_pSeries: \
|
||||
#define STD_EXCEPTION_HV(loc, vec, label) \
|
||||
. = loc; \
|
||||
.globl label##_hv; \
|
||||
label##_hv: \
|
||||
HMT_MEDIUM; \
|
||||
mtspr SPRN_SPRG_SCRATCH0,r20; /* save r20 */ \
|
||||
mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \
|
||||
mtspr SPRN_SRR0,r20; \
|
||||
mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
|
||||
mtspr SPRN_SRR1,r20; \
|
||||
mfspr r20,SPRN_SPRG_SCRATCH0; /* restore r20 */ \
|
||||
mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \
|
||||
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
|
||||
DO_KVM vec; \
|
||||
SET_SCRATCH0(r13); /* save r13 */ \
|
||||
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, EXC_HV)
|
||||
|
||||
|
||||
#define MASKABLE_EXCEPTION_PSERIES(n, label) \
|
||||
. = n; \
|
||||
.globl label##_pSeries; \
|
||||
label##_pSeries: \
|
||||
#define __MASKABLE_EXCEPTION_PSERIES(vec, label, h) \
|
||||
HMT_MEDIUM; \
|
||||
DO_KVM n; \
|
||||
mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \
|
||||
mfspr r13,SPRN_SPRG_PACA; /* get paca address into r13 */ \
|
||||
DO_KVM vec; \
|
||||
SET_SCRATCH0(r13); /* save r13 */ \
|
||||
GET_PACA(r13); \
|
||||
std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \
|
||||
std r10,PACA_EXGEN+EX_R10(r13); \
|
||||
lbz r10,PACASOFTIRQEN(r13); \
|
||||
mfcr r9; \
|
||||
cmpwi r10,0; \
|
||||
beq masked_interrupt; \
|
||||
mfspr r10,SPRN_SPRG_SCRATCH0; \
|
||||
beq masked_##h##interrupt; \
|
||||
GET_SCRATCH0(r10); \
|
||||
std r10,PACA_EXGEN+EX_R13(r13); \
|
||||
std r11,PACA_EXGEN+EX_R11(r13); \
|
||||
std r12,PACA_EXGEN+EX_R12(r13); \
|
||||
ld r12,PACAKBASE(r13); /* get high part of &label */ \
|
||||
ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \
|
||||
mfspr r11,SPRN_SRR0; /* save SRR0 */ \
|
||||
mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
|
||||
LOAD_HANDLER(r12,label##_common) \
|
||||
mtspr SPRN_SRR0,r12; \
|
||||
mfspr r12,SPRN_SRR1; /* and SRR1 */ \
|
||||
mtspr SPRN_SRR1,r10; \
|
||||
rfid; \
|
||||
mtspr SPRN_##h##SRR0,r12; \
|
||||
mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
|
||||
mtspr SPRN_##h##SRR1,r10; \
|
||||
h##rfid; \
|
||||
b . /* prevent speculative execution */
|
||||
#define _MASKABLE_EXCEPTION_PSERIES(vec, label, h) \
|
||||
__MASKABLE_EXCEPTION_PSERIES(vec, label, h)
|
||||
|
||||
#define MASKABLE_EXCEPTION_PSERIES(loc, vec, label) \
|
||||
. = loc; \
|
||||
.globl label##_pSeries; \
|
||||
label##_pSeries: \
|
||||
_MASKABLE_EXCEPTION_PSERIES(vec, label, EXC_STD)
|
||||
|
||||
#define MASKABLE_EXCEPTION_HV(loc, vec, label) \
|
||||
. = loc; \
|
||||
.globl label##_hv; \
|
||||
label##_hv: \
|
||||
_MASKABLE_EXCEPTION_PSERIES(vec, label, EXC_HV)
|
||||
|
||||
#ifdef CONFIG_PPC_ISERIES
|
||||
#define DISABLE_INTS \
|
||||
|
||||
@ -49,7 +49,7 @@ label##5: \
|
||||
FTR_ENTRY_OFFSET label##2b-label##5b; \
|
||||
FTR_ENTRY_OFFSET label##3b-label##5b; \
|
||||
FTR_ENTRY_OFFSET label##4b-label##5b; \
|
||||
.ifgt (label##4b-label##3b)-(label##2b-label##1b); \
|
||||
.ifgt (label##4b- label##3b)-(label##2b- label##1b); \
|
||||
.error "Feature section else case larger than body"; \
|
||||
.endif; \
|
||||
.popsection;
|
||||
@ -146,6 +146,19 @@ label##5: \
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define ASM_FTR_IF(section_if, section_else, msk, val) \
|
||||
stringify_in_c(BEGIN_FTR_SECTION) \
|
||||
section_if "; " \
|
||||
stringify_in_c(FTR_SECTION_ELSE) \
|
||||
section_else "; " \
|
||||
stringify_in_c(ALT_FTR_SECTION_END((msk), (val)))
|
||||
|
||||
#define ASM_FTR_IFSET(section_if, section_else, msk) \
|
||||
ASM_FTR_IF(section_if, section_else, (msk), (msk))
|
||||
|
||||
#define ASM_FTR_IFCLR(section_if, section_else, msk) \
|
||||
ASM_FTR_IF(section_if, section_else, (msk), 0)
|
||||
|
||||
#define ASM_MMU_FTR_IF(section_if, section_else, msk, val) \
|
||||
stringify_in_c(BEGIN_MMU_FTR_SECTION) \
|
||||
section_if "; " \
|
||||
|
||||
@ -47,6 +47,7 @@
|
||||
#define FW_FEATURE_BEAT ASM_CONST(0x0000000001000000)
|
||||
#define FW_FEATURE_CMO ASM_CONST(0x0000000002000000)
|
||||
#define FW_FEATURE_VPHN ASM_CONST(0x0000000004000000)
|
||||
#define FW_FEATURE_XCMO ASM_CONST(0x0000000008000000)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
@ -60,7 +61,7 @@ enum {
|
||||
FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN |
|
||||
FW_FEATURE_BULK_REMOVE | FW_FEATURE_XDABR |
|
||||
FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR |
|
||||
FW_FEATURE_CMO | FW_FEATURE_VPHN,
|
||||
FW_FEATURE_CMO | FW_FEATURE_VPHN | FW_FEATURE_XCMO,
|
||||
FW_FEATURE_PSERIES_ALWAYS = 0,
|
||||
FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
|
||||
FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
|
||||
|
||||
@ -102,6 +102,7 @@
|
||||
#define H_ANDCOND (1UL<<(63-33))
|
||||
#define H_ICACHE_INVALIDATE (1UL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
|
||||
#define H_ICACHE_SYNCHRONIZE (1UL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
|
||||
#define H_COALESCE_CAND (1UL<<(63-42)) /* page is a good candidate for coalescing */
|
||||
#define H_ZERO_PAGE (1UL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
|
||||
#define H_COPY_PAGE (1UL<<(63-49))
|
||||
#define H_N (1UL<<(63-61))
|
||||
@ -234,6 +235,7 @@
|
||||
#define H_GET_MPP 0x2D4
|
||||
#define H_HOME_NODE_ASSOCIATIVITY 0x2EC
|
||||
#define H_BEST_ENERGY 0x2F4
|
||||
#define H_GET_MPP_X 0x314
|
||||
#define MAX_HCALL_OPCODE H_BEST_ENERGY
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
@ -312,6 +314,16 @@ struct hvcall_mpp_data {
|
||||
|
||||
int h_get_mpp(struct hvcall_mpp_data *);
|
||||
|
||||
struct hvcall_mpp_x_data {
|
||||
unsigned long coalesced_bytes;
|
||||
unsigned long pool_coalesced_bytes;
|
||||
unsigned long pool_purr_cycles;
|
||||
unsigned long pool_spurr_cycles;
|
||||
unsigned long reserved[3];
|
||||
};
|
||||
|
||||
int h_get_mpp_x(struct hvcall_mpp_x_data *mpp_x_data);
|
||||
|
||||
#ifdef CONFIG_PPC_PSERIES
|
||||
extern int CMO_PrPSP;
|
||||
extern int CMO_SecPSP;
|
||||
|
||||
@ -31,7 +31,6 @@ struct iowa_bus {
|
||||
void *private;
|
||||
};
|
||||
|
||||
void __devinit io_workaround_init(void);
|
||||
void __devinit iowa_register_bus(struct pci_controller *, struct ppc_pci_io *,
|
||||
int (*)(struct iowa_bus *, void *), void *);
|
||||
struct iowa_bus *iowa_mem_find_bus(const PCI_IO_ADDR);
|
||||
@ -2,6 +2,8 @@
|
||||
#define _ASM_POWERPC_IO_H
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#define ARCH_HAS_IOREMAP_WC
|
||||
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
@ -481,10 +483,16 @@ __do_out_asm(_rec_outl, "stwbrx")
|
||||
_memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
|
||||
#endif /* !CONFIG_EEH */
|
||||
|
||||
#ifdef CONFIG_PPC_INDIRECT_IO
|
||||
#define DEF_PCI_HOOK(x) x
|
||||
#ifdef CONFIG_PPC_INDIRECT_PIO
|
||||
#define DEF_PCI_HOOK_pio(x) x
|
||||
#else
|
||||
#define DEF_PCI_HOOK(x) NULL
|
||||
#define DEF_PCI_HOOK_pio(x) NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PPC_INDIRECT_MMIO
|
||||
#define DEF_PCI_HOOK_mem(x) x
|
||||
#else
|
||||
#define DEF_PCI_HOOK_mem(x) NULL
|
||||
#endif
|
||||
|
||||
/* Structure containing all the hooks */
|
||||
@ -504,7 +512,7 @@ extern struct ppc_pci_io {
|
||||
#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
|
||||
static inline ret name at \
|
||||
{ \
|
||||
if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \
|
||||
if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
|
||||
return ppc_pci_io.name al; \
|
||||
return __do_##name al; \
|
||||
}
|
||||
@ -512,7 +520,7 @@ static inline ret name at \
|
||||
#define DEF_PCI_AC_NORET(name, at, al, space, aa) \
|
||||
static inline void name at \
|
||||
{ \
|
||||
if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \
|
||||
if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
|
||||
ppc_pci_io.name al; \
|
||||
else \
|
||||
__do_##name al; \
|
||||
@ -616,12 +624,13 @@ static inline void iosync(void)
|
||||
* * ioremap is the standard one and provides non-cacheable guarded mappings
|
||||
* and can be hooked by the platform via ppc_md
|
||||
*
|
||||
* * ioremap_flags allows to specify the page flags as an argument and can
|
||||
* also be hooked by the platform via ppc_md. ioremap_prot is the exact
|
||||
* same thing as ioremap_flags.
|
||||
* * ioremap_prot allows to specify the page flags as an argument and can
|
||||
* also be hooked by the platform via ppc_md.
|
||||
*
|
||||
* * ioremap_nocache is identical to ioremap
|
||||
*
|
||||
* * ioremap_wc enables write combining
|
||||
*
|
||||
* * iounmap undoes such a mapping and can be hooked
|
||||
*
|
||||
* * __ioremap_at (and the pending __iounmap_at) are low level functions to
|
||||
@ -629,7 +638,7 @@ static inline void iosync(void)
|
||||
* currently be hooked. Must be page aligned.
|
||||
*
|
||||
* * __ioremap is the low level implementation used by ioremap and
|
||||
* ioremap_flags and cannot be hooked (but can be used by a hook on one
|
||||
* ioremap_prot and cannot be hooked (but can be used by a hook on one
|
||||
* of the previous ones)
|
||||
*
|
||||
* * __ioremap_caller is the same as above but takes an explicit caller
|
||||
@ -640,10 +649,10 @@ static inline void iosync(void)
|
||||
*
|
||||
*/
|
||||
extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
|
||||
extern void __iomem *ioremap_flags(phys_addr_t address, unsigned long size,
|
||||
unsigned long flags);
|
||||
extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
|
||||
unsigned long flags);
|
||||
extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
|
||||
#define ioremap_nocache(addr, size) ioremap((addr), (size))
|
||||
#define ioremap_prot(addr, size, prot) ioremap_flags((addr), (size), (prot))
|
||||
|
||||
extern void iounmap(volatile void __iomem *addr);
|
||||
|
||||
|
||||
54
arch/powerpc/include/asm/io_event_irq.h
Normal file
54
arch/powerpc/include/asm/io_event_irq.h
Normal file
@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Copyright 2010, 2011 Mark Nelson and Tseng-Hui (Frank) Lin, IBM Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_POWERPC_IO_EVENT_IRQ_H
|
||||
#define _ASM_POWERPC_IO_EVENT_IRQ_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/notifier.h>
|
||||
|
||||
#define PSERIES_IOEI_RPC_MAX_LEN 216
|
||||
|
||||
#define PSERIES_IOEI_TYPE_ERR_DETECTED 0x01
|
||||
#define PSERIES_IOEI_TYPE_ERR_RECOVERED 0x02
|
||||
#define PSERIES_IOEI_TYPE_EVENT 0x03
|
||||
#define PSERIES_IOEI_TYPE_RPC_PASS_THRU 0x04
|
||||
|
||||
#define PSERIES_IOEI_SUBTYPE_NOT_APP 0x00
|
||||
#define PSERIES_IOEI_SUBTYPE_REBALANCE_REQ 0x01
|
||||
#define PSERIES_IOEI_SUBTYPE_NODE_ONLINE 0x03
|
||||
#define PSERIES_IOEI_SUBTYPE_NODE_OFFLINE 0x04
|
||||
#define PSERIES_IOEI_SUBTYPE_DUMP_SIZE_CHANGE 0x05
|
||||
#define PSERIES_IOEI_SUBTYPE_TORRENT_IRV_UPDATE 0x06
|
||||
#define PSERIES_IOEI_SUBTYPE_TORRENT_HFI_CFGED 0x07
|
||||
|
||||
#define PSERIES_IOEI_SCOPE_NOT_APP 0x00
|
||||
#define PSERIES_IOEI_SCOPE_RIO_HUB 0x36
|
||||
#define PSERIES_IOEI_SCOPE_RIO_BRIDGE 0x37
|
||||
#define PSERIES_IOEI_SCOPE_PHB 0x38
|
||||
#define PSERIES_IOEI_SCOPE_EADS_GLOBAL 0x39
|
||||
#define PSERIES_IOEI_SCOPE_EADS_SLOT 0x3A
|
||||
#define PSERIES_IOEI_SCOPE_TORRENT_HUB 0x3B
|
||||
#define PSERIES_IOEI_SCOPE_SERVICE_PROC 0x51
|
||||
|
||||
/* Platform Event Log Format, Version 6, data portition of IO event section */
|
||||
struct pseries_io_event {
|
||||
uint8_t event_type; /* 0x00 IO-Event Type */
|
||||
uint8_t rpc_data_len; /* 0x01 RPC data length */
|
||||
uint8_t scope; /* 0x02 Error/Event Scope */
|
||||
uint8_t event_subtype; /* 0x03 I/O-Event Sub-Type */
|
||||
uint32_t drc_index; /* 0x04 DRC Index */
|
||||
uint8_t rpc_data[PSERIES_IOEI_RPC_MAX_LEN];
|
||||
/* 0x08 RPC Data (0-216 bytes, */
|
||||
/* padded to 4 bytes alignment) */
|
||||
};
|
||||
|
||||
extern struct atomic_notifier_head pseries_ioei_notifier_list;
|
||||
|
||||
#endif /* _ASM_POWERPC_IO_EVENT_IRQ_H */
|
||||
@ -88,9 +88,6 @@ struct irq_host_ops {
|
||||
/* Dispose of such a mapping */
|
||||
void (*unmap)(struct irq_host *h, unsigned int virq);
|
||||
|
||||
/* Update of such a mapping */
|
||||
void (*remap)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
|
||||
|
||||
/* Translate device-tree interrupt specifier from raw format coming
|
||||
* from the firmware to a irq_hw_number_t (interrupt line number) and
|
||||
* type (sense) that can be passed to set_irq_type(). In the absence
|
||||
@ -128,19 +125,10 @@ struct irq_host {
|
||||
struct device_node *of_node;
|
||||
};
|
||||
|
||||
/* The main irq map itself is an array of NR_IRQ entries containing the
|
||||
* associate host and irq number. An entry with a host of NULL is free.
|
||||
* An entry can be allocated if it's free, the allocator always then sets
|
||||
* hwirq first to the host's invalid irq number and then fills ops.
|
||||
*/
|
||||
struct irq_map_entry {
|
||||
irq_hw_number_t hwirq;
|
||||
struct irq_host *host;
|
||||
};
|
||||
|
||||
extern struct irq_map_entry irq_map[NR_IRQS];
|
||||
|
||||
struct irq_data;
|
||||
extern irq_hw_number_t irqd_to_hwirq(struct irq_data *d);
|
||||
extern irq_hw_number_t virq_to_hw(unsigned int virq);
|
||||
extern bool virq_is_host(unsigned int virq, struct irq_host *host);
|
||||
|
||||
/**
|
||||
* irq_alloc_host - Allocate a new irq_host data structure
|
||||
|
||||
@ -76,7 +76,7 @@ extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *));
|
||||
extern cpumask_t cpus_in_sr;
|
||||
static inline int kexec_sr_activated(int cpu)
|
||||
{
|
||||
return cpu_isset(cpu,cpus_in_sr);
|
||||
return cpumask_test_cpu(cpu, &cpus_in_sr);
|
||||
}
|
||||
|
||||
struct kimage;
|
||||
|
||||
@ -59,6 +59,7 @@
|
||||
#define BOOK3S_INTERRUPT_INST_SEGMENT 0x480
|
||||
#define BOOK3S_INTERRUPT_EXTERNAL 0x500
|
||||
#define BOOK3S_INTERRUPT_EXTERNAL_LEVEL 0x501
|
||||
#define BOOK3S_INTERRUPT_EXTERNAL_HV 0x502
|
||||
#define BOOK3S_INTERRUPT_ALIGNMENT 0x600
|
||||
#define BOOK3S_INTERRUPT_PROGRAM 0x700
|
||||
#define BOOK3S_INTERRUPT_FP_UNAVAIL 0x800
|
||||
|
||||
@ -34,6 +34,7 @@
|
||||
(\intno == BOOK3S_INTERRUPT_DATA_SEGMENT) || \
|
||||
(\intno == BOOK3S_INTERRUPT_INST_SEGMENT) || \
|
||||
(\intno == BOOK3S_INTERRUPT_EXTERNAL) || \
|
||||
(\intno == BOOK3S_INTERRUPT_EXTERNAL_HV) || \
|
||||
(\intno == BOOK3S_INTERRUPT_ALIGNMENT) || \
|
||||
(\intno == BOOK3S_INTERRUPT_PROGRAM) || \
|
||||
(\intno == BOOK3S_INTERRUPT_FP_UNAVAIL) || \
|
||||
|
||||
@ -210,6 +210,8 @@ struct dtl_entry {
|
||||
#define DISPATCH_LOG_BYTES 4096 /* bytes per cpu */
|
||||
#define N_DISPATCH_LOG (DISPATCH_LOG_BYTES / sizeof(struct dtl_entry))
|
||||
|
||||
extern struct kmem_cache *dtl_cache;
|
||||
|
||||
/*
|
||||
* When CONFIG_VIRT_CPU_ACCOUNTING = y, the cpu accounting code controls
|
||||
* reading from the dispatch trace log. If other code wants to consume
|
||||
|
||||
@ -29,21 +29,6 @@ struct file;
|
||||
struct pci_controller;
|
||||
struct kimage;
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
struct smp_ops_t {
|
||||
void (*message_pass)(int target, int msg);
|
||||
int (*probe)(void);
|
||||
void (*kick_cpu)(int nr);
|
||||
void (*setup_cpu)(int nr);
|
||||
void (*bringup_done)(void);
|
||||
void (*take_timebase)(void);
|
||||
void (*give_timebase)(void);
|
||||
int (*cpu_disable)(void);
|
||||
void (*cpu_die)(unsigned int nr);
|
||||
int (*cpu_bootable)(unsigned int nr);
|
||||
};
|
||||
#endif
|
||||
|
||||
struct machdep_calls {
|
||||
char *name;
|
||||
#ifdef CONFIG_PPC64
|
||||
@ -267,6 +252,7 @@ struct machdep_calls {
|
||||
|
||||
extern void e500_idle(void);
|
||||
extern void power4_idle(void);
|
||||
extern void power7_idle(void);
|
||||
extern void ppc6xx_idle(void);
|
||||
extern void book3e_idle(void);
|
||||
|
||||
@ -311,12 +297,6 @@ extern sys_ctrler_t sys_ctrler;
|
||||
|
||||
#endif /* CONFIG_PPC_PMAC */
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
/* Poor default implementations */
|
||||
extern void __devinit smp_generic_give_timebase(void);
|
||||
extern void __devinit smp_generic_take_timebase(void);
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
|
||||
/* Functions to produce codes on the leds.
|
||||
* The SRC code should be unique for the message category and should
|
||||
|
||||
@ -43,6 +43,7 @@
|
||||
#define MAS0_TLBSEL(x) (((x) << 28) & 0x30000000)
|
||||
#define MAS0_ESEL(x) (((x) << 16) & 0x0FFF0000)
|
||||
#define MAS0_NV(x) ((x) & 0x00000FFF)
|
||||
#define MAS0_ESEL_MASK 0x0FFF0000
|
||||
#define MAS0_HES 0x00004000
|
||||
#define MAS0_WQ_ALLWAYS 0x00000000
|
||||
#define MAS0_WQ_COND 0x00001000
|
||||
@ -137,6 +138,21 @@
|
||||
#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
|
||||
#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
|
||||
|
||||
/* MMUCFG bits */
|
||||
#define MMUCFG_MAVN_NASK 0x00000003
|
||||
#define MMUCFG_MAVN_V1_0 0x00000000
|
||||
#define MMUCFG_MAVN_V2_0 0x00000001
|
||||
#define MMUCFG_NTLB_MASK 0x0000000c
|
||||
#define MMUCFG_NTLB_SHIFT 2
|
||||
#define MMUCFG_PIDSIZE_MASK 0x000007c0
|
||||
#define MMUCFG_PIDSIZE_SHIFT 6
|
||||
#define MMUCFG_TWC 0x00008000
|
||||
#define MMUCFG_LRAT 0x00010000
|
||||
#define MMUCFG_RASIZE_MASK 0x00fe0000
|
||||
#define MMUCFG_RASIZE_SHIFT 17
|
||||
#define MMUCFG_LPIDSIZE_MASK 0x0f000000
|
||||
#define MMUCFG_LPIDSIZE_SHIFT 24
|
||||
|
||||
/* TLBnCFG encoding */
|
||||
#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
|
||||
#define TLBnCFG_HES 0x00002000 /* HW select supported */
|
||||
@ -229,6 +245,10 @@ extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
|
||||
extern int mmu_linear_psize;
|
||||
extern int mmu_vmemmap_psize;
|
||||
|
||||
#ifdef CONFIG_PPC64
|
||||
extern unsigned long linear_map_top;
|
||||
#endif
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */
|
||||
|
||||
@ -408,6 +408,7 @@ static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
|
||||
#endif /* CONFIG_PPC_SUBPAGE_PROT */
|
||||
|
||||
typedef unsigned long mm_context_id_t;
|
||||
struct spinlock;
|
||||
|
||||
typedef struct {
|
||||
mm_context_id_t id;
|
||||
@ -423,6 +424,11 @@ typedef struct {
|
||||
#ifdef CONFIG_PPC_SUBPAGE_PROT
|
||||
struct subpage_prot_table spt;
|
||||
#endif /* CONFIG_PPC_SUBPAGE_PROT */
|
||||
#ifdef CONFIG_PPC_ICSWX
|
||||
struct spinlock *cop_lockp; /* guard acop and cop_pid */
|
||||
unsigned long acop; /* mask of enabled coprocessor types */
|
||||
unsigned int cop_pid; /* pid value used with coprocessors */
|
||||
#endif /* CONFIG_PPC_ICSWX */
|
||||
} mm_context_t;
|
||||
|
||||
|
||||
|
||||
@ -56,11 +56,6 @@
|
||||
*/
|
||||
#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
|
||||
|
||||
/* This indicates that the processor uses the ISA 2.06 server tlbie
|
||||
* mnemonics
|
||||
*/
|
||||
#define MMU_FTR_TLBIE_206 ASM_CONST(0x00400000)
|
||||
|
||||
/* Enable use of TLB reservation. Processor should support tlbsrx.
|
||||
* instruction and MAS0[WQ].
|
||||
*/
|
||||
@ -70,6 +65,53 @@
|
||||
*/
|
||||
#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
|
||||
|
||||
/* MMU is SLB-based
|
||||
*/
|
||||
#define MMU_FTR_SLB ASM_CONST(0x02000000)
|
||||
|
||||
/* Support 16M large pages
|
||||
*/
|
||||
#define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
|
||||
|
||||
/* Supports TLBIEL variant
|
||||
*/
|
||||
#define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
|
||||
|
||||
/* Supports tlbies w/o locking
|
||||
*/
|
||||
#define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
|
||||
|
||||
/* Large pages can be marked CI
|
||||
*/
|
||||
#define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
|
||||
|
||||
/* 1T segments available
|
||||
*/
|
||||
#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
|
||||
|
||||
/* Doesn't support the B bit (1T segment) in SLBIE
|
||||
*/
|
||||
#define MMU_FTR_NO_SLBIE_B ASM_CONST(0x80000000)
|
||||
|
||||
/* MMU feature bit sets for various CPUs */
|
||||
#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
|
||||
MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
|
||||
#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
|
||||
#define MMU_FTRS_PPC970 MMU_FTRS_POWER4
|
||||
#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
|
||||
#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
|
||||
#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
|
||||
#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
|
||||
MMU_FTR_CI_LARGE_PAGE
|
||||
#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
|
||||
MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
|
||||
#define MMU_FTRS_A2 MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | \
|
||||
MMU_FTR_USE_TLBIVAX_BCAST | \
|
||||
MMU_FTR_LOCK_BCAST_INVAL | \
|
||||
MMU_FTR_USE_TLBRSRV | \
|
||||
MMU_FTR_USE_PAIRED_MAS | \
|
||||
MMU_FTR_TLBIEL | \
|
||||
MMU_FTR_16M_PAGE
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/cputable.h>
|
||||
|
||||
|
||||
@ -32,6 +32,10 @@ extern void __destroy_context(unsigned long context_id);
|
||||
extern void mmu_context_init(void);
|
||||
#endif
|
||||
|
||||
extern void switch_cop(struct mm_struct *next);
|
||||
extern int use_cop(unsigned long acop, struct mm_struct *mm);
|
||||
extern void drop_cop(unsigned long acop, struct mm_struct *mm);
|
||||
|
||||
/*
|
||||
* switch_mm is the entry point called from the architecture independent
|
||||
* code in kernel/sched.c
|
||||
@ -55,6 +59,12 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
|
||||
if (prev == next)
|
||||
return;
|
||||
|
||||
#ifdef CONFIG_PPC_ICSWX
|
||||
/* Switch coprocessor context only if prev or next uses a coprocessor */
|
||||
if (prev->context.acop || next->context.acop)
|
||||
switch_cop(next);
|
||||
#endif /* CONFIG_PPC_ICSWX */
|
||||
|
||||
/* We must stop all altivec streams before changing the HW
|
||||
* context
|
||||
*/
|
||||
@ -67,7 +77,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
|
||||
* sub architectures.
|
||||
*/
|
||||
#ifdef CONFIG_PPC_STD_MMU_64
|
||||
if (cpu_has_feature(CPU_FTR_SLB))
|
||||
if (mmu_has_feature(MMU_FTR_SLB))
|
||||
switch_slb(tsk, next);
|
||||
else
|
||||
switch_stab(tsk, next);
|
||||
|
||||
@ -262,6 +262,7 @@ struct mpic
|
||||
#ifdef CONFIG_SMP
|
||||
struct irq_chip hc_ipi;
|
||||
#endif
|
||||
struct irq_chip hc_tm;
|
||||
const char *name;
|
||||
/* Flags */
|
||||
unsigned int flags;
|
||||
@ -280,7 +281,7 @@ struct mpic
|
||||
|
||||
/* vector numbers used for internal sources (ipi/timers) */
|
||||
unsigned int ipi_vecs[4];
|
||||
unsigned int timer_vecs[4];
|
||||
unsigned int timer_vecs[8];
|
||||
|
||||
/* Spurious vector to program into unused sources */
|
||||
unsigned int spurious_vec;
|
||||
@ -368,6 +369,8 @@ struct mpic
|
||||
* NOTE: This flag trumps MPIC_WANTS_RESET.
|
||||
*/
|
||||
#define MPIC_NO_RESET 0x00004000
|
||||
/* Freescale MPIC (compatible includes "fsl,mpic") */
|
||||
#define MPIC_FSL 0x00008000
|
||||
|
||||
/* MPIC HW modification ID */
|
||||
#define MPIC_REGSET_MASK 0xf0000000
|
||||
|
||||
@ -18,13 +18,18 @@
|
||||
extern int pSeries_reconfig_notifier_register(struct notifier_block *);
|
||||
extern void pSeries_reconfig_notifier_unregister(struct notifier_block *);
|
||||
extern struct blocking_notifier_head pSeries_reconfig_chain;
|
||||
/* Not the best place to put this, will be fixed when we move some
|
||||
* of the rtas suspend-me stuff to pseries */
|
||||
extern void pSeries_coalesce_init(void);
|
||||
#else /* !CONFIG_PPC_PSERIES */
|
||||
static inline int pSeries_reconfig_notifier_register(struct notifier_block *nb)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline void pSeries_reconfig_notifier_unregister(struct notifier_block *nb) { }
|
||||
static inline void pSeries_coalesce_init(void) { }
|
||||
#endif /* CONFIG_PPC_PSERIES */
|
||||
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* _PPC64_PSERIES_RECONFIG_H */
|
||||
|
||||
@ -92,9 +92,9 @@ struct paca_struct {
|
||||
* Now, starting in cacheline 2, the exception save areas
|
||||
*/
|
||||
/* used for most interrupts/exceptions */
|
||||
u64 exgen[10] __attribute__((aligned(0x80)));
|
||||
u64 exmc[10]; /* used for machine checks */
|
||||
u64 exslb[10]; /* used for SLB/segment table misses
|
||||
u64 exgen[11] __attribute__((aligned(0x80)));
|
||||
u64 exmc[11]; /* used for machine checks */
|
||||
u64 exslb[11]; /* used for SLB/segment table misses
|
||||
* on the linear mapping */
|
||||
/* SLB related definitions */
|
||||
u16 vmalloc_sllp;
|
||||
@ -106,7 +106,8 @@ struct paca_struct {
|
||||
pgd_t *pgd; /* Current PGD */
|
||||
pgd_t *kernel_pgd; /* Kernel PGD */
|
||||
u64 exgen[8] __attribute__((aligned(0x80)));
|
||||
u64 extlb[EX_TLB_SIZE*3] __attribute__((aligned(0x80)));
|
||||
/* We can have up to 3 levels of reentrancy in the TLB miss handler */
|
||||
u64 extlb[3][EX_TLB_SIZE / sizeof(u64)] __attribute__((aligned(0x80)));
|
||||
u64 exmc[8]; /* used for machine checks */
|
||||
u64 excrit[8]; /* used for crit interrupts */
|
||||
u64 exdbg[8]; /* used for debug interrupts */
|
||||
@ -125,7 +126,7 @@ struct paca_struct {
|
||||
struct task_struct *__current; /* Pointer to current */
|
||||
u64 kstack; /* Saved Kernel stack addr */
|
||||
u64 stab_rr; /* stab/slb round-robin counter */
|
||||
u64 saved_r1; /* r1 save for RTAS calls */
|
||||
u64 saved_r1; /* r1 save for RTAS calls or PM */
|
||||
u64 saved_msr; /* MSR saved here by enter_rtas */
|
||||
u16 trap_save; /* Used when bad stack is encountered */
|
||||
u8 soft_enabled; /* irq soft-enable flag */
|
||||
|
||||
@ -59,24 +59,7 @@ static __inline__ void clear_page(void *addr)
|
||||
: "ctr", "memory");
|
||||
}
|
||||
|
||||
extern void copy_4K_page(void *to, void *from);
|
||||
|
||||
#ifdef CONFIG_PPC_64K_PAGES
|
||||
static inline void copy_page(void *to, void *from)
|
||||
{
|
||||
unsigned int i;
|
||||
for (i=0; i < (1 << (PAGE_SHIFT - 12)); i++) {
|
||||
copy_4K_page(to, from);
|
||||
to += 4096;
|
||||
from += 4096;
|
||||
}
|
||||
}
|
||||
#else /* CONFIG_PPC_64K_PAGES */
|
||||
static inline void copy_page(void *to, void *from)
|
||||
{
|
||||
copy_4K_page(to, from);
|
||||
}
|
||||
#endif /* CONFIG_PPC_64K_PAGES */
|
||||
extern void copy_page(void *to, void *from);
|
||||
|
||||
/* Log 2 of page table size */
|
||||
extern u64 ppc64_pft_size;
|
||||
@ -130,7 +113,7 @@ extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
|
||||
extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
|
||||
unsigned long len, unsigned int psize);
|
||||
|
||||
#define slice_mm_new_context(mm) ((mm)->context.id == 0)
|
||||
#define slice_mm_new_context(mm) ((mm)->context.id == MMU_NO_CONTEXT)
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#else
|
||||
|
||||
@ -257,21 +257,20 @@ static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
|
||||
static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
|
||||
pte_t *ptep)
|
||||
{
|
||||
unsigned long old;
|
||||
|
||||
if ((pte_val(*ptep) & _PAGE_RW) == 0)
|
||||
return;
|
||||
old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
|
||||
if ((pte_val(*ptep) & _PAGE_RW) == 0)
|
||||
return;
|
||||
|
||||
pte_update(mm, addr, ptep, _PAGE_RW, 0);
|
||||
}
|
||||
|
||||
static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
|
||||
unsigned long addr, pte_t *ptep)
|
||||
{
|
||||
unsigned long old;
|
||||
|
||||
if ((pte_val(*ptep) & _PAGE_RW) == 0)
|
||||
return;
|
||||
old = pte_update(mm, addr, ptep, _PAGE_RW, 1);
|
||||
|
||||
pte_update(mm, addr, ptep, _PAGE_RW, 1);
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -41,6 +41,10 @@
|
||||
#define PPC_INST_RFCI 0x4c000066
|
||||
#define PPC_INST_RFDI 0x4c00004e
|
||||
#define PPC_INST_RFMCI 0x4c00004c
|
||||
#define PPC_INST_MFSPR_DSCR 0x7c1102a6
|
||||
#define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff
|
||||
#define PPC_INST_MTSPR_DSCR 0x7c1103a6
|
||||
#define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff
|
||||
|
||||
#define PPC_INST_STRING 0x7c00042a
|
||||
#define PPC_INST_STRING_MASK 0xfc0007fe
|
||||
@ -56,6 +60,17 @@
|
||||
#define PPC_INST_TLBSRX_DOT 0x7c0006a5
|
||||
#define PPC_INST_XXLOR 0xf0000510
|
||||
|
||||
#define PPC_INST_NAP 0x4c000364
|
||||
#define PPC_INST_SLEEP 0x4c0003a4
|
||||
|
||||
/* A2 specific instructions */
|
||||
#define PPC_INST_ERATWE 0x7c0001a6
|
||||
#define PPC_INST_ERATRE 0x7c000166
|
||||
#define PPC_INST_ERATILX 0x7c000066
|
||||
#define PPC_INST_ERATIVAX 0x7c000666
|
||||
#define PPC_INST_ERATSX 0x7c000126
|
||||
#define PPC_INST_ERATSX_DOT 0x7c000127
|
||||
|
||||
/* macros to insert fields into opcodes */
|
||||
#define __PPC_RA(a) (((a) & 0x1f) << 16)
|
||||
#define __PPC_RB(b) (((b) & 0x1f) << 11)
|
||||
@ -67,6 +82,8 @@
|
||||
#define __PPC_XT(s) __PPC_XS(s)
|
||||
#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
|
||||
#define __PPC_WC(w) (((w) & 0x3) << 21)
|
||||
#define __PPC_WS(w) (((w) & 0x1f) << 11)
|
||||
|
||||
/*
|
||||
* Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
|
||||
* larx with EH set as an illegal instruction.
|
||||
@ -113,6 +130,21 @@
|
||||
#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
|
||||
__PPC_RA(a) | __PPC_RB(b))
|
||||
|
||||
#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \
|
||||
__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
|
||||
#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \
|
||||
__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
|
||||
#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \
|
||||
__PPC_T_TLB(t) | __PPC_RA(a) | \
|
||||
__PPC_RB(b))
|
||||
#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \
|
||||
__PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
|
||||
#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \
|
||||
__PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
|
||||
#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
|
||||
__PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
|
||||
|
||||
|
||||
/*
|
||||
* Define what the VSX XX1 form instructions will look like, then add
|
||||
* the 128 bit load store instructions based on that.
|
||||
@ -126,4 +158,7 @@
|
||||
#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \
|
||||
VSX_XX3((t), (a), (b)))
|
||||
|
||||
#define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
|
||||
#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
|
||||
|
||||
#endif /* _ASM_POWERPC_PPC_OPCODE_H */
|
||||
|
||||
@ -170,6 +170,7 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
|
||||
#define HMT_MEDIUM or 2,2,2
|
||||
#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
|
||||
#define HMT_HIGH or 3,3,3
|
||||
#define HMT_EXTRA_HIGH or 7,7,7 # power7 only
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#ifdef CONFIG_PPC64
|
||||
|
||||
@ -238,6 +238,10 @@ struct thread_struct {
|
||||
#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
|
||||
void* kvm_shadow_vcpu; /* KVM internal data */
|
||||
#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
|
||||
#ifdef CONFIG_PPC64
|
||||
unsigned long dscr;
|
||||
int dscr_inherit;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define ARCH_MIN_TASKALIGN 16
|
||||
|
||||
@ -99,17 +99,23 @@
|
||||
#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
|
||||
|
||||
#if defined(CONFIG_PPC_BOOK3S_64)
|
||||
#define MSR_64BIT MSR_SF
|
||||
|
||||
/* Server variant */
|
||||
#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
|
||||
#define MSR_KERNEL MSR_ | MSR_SF
|
||||
#define MSR_KERNEL MSR_ | MSR_64BIT
|
||||
#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
|
||||
#define MSR_USER64 MSR_USER32 | MSR_SF
|
||||
#define MSR_USER64 MSR_USER32 | MSR_64BIT
|
||||
#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx)
|
||||
/* Default MSR for kernel mode. */
|
||||
#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
|
||||
#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
|
||||
#endif
|
||||
|
||||
#ifndef MSR_64BIT
|
||||
#define MSR_64BIT 0
|
||||
#endif
|
||||
|
||||
/* Floating Point Status and Control Register (FPSCR) Fields */
|
||||
#define FPSCR_FX 0x80000000 /* FPU exception summary */
|
||||
#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
|
||||
@ -182,6 +188,8 @@
|
||||
|
||||
#define SPRN_CTR 0x009 /* Count Register */
|
||||
#define SPRN_DSCR 0x11
|
||||
#define SPRN_CFAR 0x1c /* Come From Address Register */
|
||||
#define SPRN_ACOP 0x1F /* Available Coprocessor Register */
|
||||
#define SPRN_CTRLF 0x088
|
||||
#define SPRN_CTRLT 0x098
|
||||
#define CTRL_CT 0xc0000000 /* current thread */
|
||||
@ -210,8 +218,43 @@
|
||||
#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
|
||||
#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
|
||||
#define SPRN_SPURR 0x134 /* Scaled PURR */
|
||||
#define SPRN_HSPRG0 0x130 /* Hypervisor Scratch 0 */
|
||||
#define SPRN_HSPRG1 0x131 /* Hypervisor Scratch 1 */
|
||||
#define SPRN_HDSISR 0x132
|
||||
#define SPRN_HDAR 0x133
|
||||
#define SPRN_HDEC 0x136 /* Hypervisor Decrementer */
|
||||
#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
|
||||
#define SPRN_RMOR 0x138 /* Real mode offset register */
|
||||
#define SPRN_HRMOR 0x139 /* Real mode offset register */
|
||||
#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
|
||||
#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
|
||||
#define SPRN_LPCR 0x13E /* LPAR Control Register */
|
||||
#define LPCR_VPM0 (1ul << (63-0))
|
||||
#define LPCR_VPM1 (1ul << (63-1))
|
||||
#define LPCR_ISL (1ul << (63-2))
|
||||
#define LPCR_DPFD_SH (63-11)
|
||||
#define LPCR_VRMA_L (1ul << (63-12))
|
||||
#define LPCR_VRMA_LP0 (1ul << (63-15))
|
||||
#define LPCR_VRMA_LP1 (1ul << (63-16))
|
||||
#define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */
|
||||
#define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */
|
||||
#define LPCR_PECE 0x00007000 /* powersave exit cause enable */
|
||||
#define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */
|
||||
#define LPCR_PECE1 0x00002000 /* decrementer can cause exit */
|
||||
#define LPCR_PECE2 0x00001000 /* machine check etc can cause exit */
|
||||
#define LPCR_MER 0x00000800 /* Mediated External Exception */
|
||||
#define LPCR_LPES0 0x00000008 /* LPAR Env selector 0 */
|
||||
#define LPCR_LPES1 0x00000004 /* LPAR Env selector 1 */
|
||||
#define LPCR_RMI 0x00000002 /* real mode is cache inhibit */
|
||||
#define LPCR_HDICE 0x00000001 /* Hyp Decr enable (HV,PR,EE) */
|
||||
#define SPRN_LPID 0x13F /* Logical Partition Identifier */
|
||||
#define SPRN_HMER 0x150 /* Hardware m? error recovery */
|
||||
#define SPRN_HMEER 0x151 /* Hardware m? enable error recovery */
|
||||
#define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */
|
||||
#define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */
|
||||
#define SPRN_TLBVPNR 0x155 /* P7 TLB control register */
|
||||
#define SPRN_TLBRPNR 0x156 /* P7 TLB control register */
|
||||
#define SPRN_TLBLPIDR 0x157 /* P7 TLB control register */
|
||||
#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
|
||||
#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
|
||||
#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
|
||||
@ -434,16 +477,23 @@
|
||||
#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
|
||||
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
|
||||
#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */
|
||||
#define SRR1_WAKERESET 0x00380000 /* System reset */
|
||||
#define SRR1_WAKESYSERR 0x00300000 /* System error */
|
||||
#define SRR1_WAKEEE 0x00200000 /* External interrupt */
|
||||
#define SRR1_WAKEMT 0x00280000 /* mtctrl */
|
||||
#define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
|
||||
#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
|
||||
#define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */
|
||||
#define SRR1_WAKERESET 0x00100000 /* System reset */
|
||||
#define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask [46:47] */
|
||||
#define SRR1_WS_DEEPEST 0x00030000 /* Some resources not maintained,
|
||||
* may not be recoverable */
|
||||
#define SRR1_WS_DEEPER 0x00020000 /* Some resources not maintained */
|
||||
#define SRR1_WS_DEEP 0x00010000 /* All resources maintained */
|
||||
#define SRR1_PROGFPE 0x00100000 /* Floating Point Enabled */
|
||||
#define SRR1_PROGPRIV 0x00040000 /* Privileged instruction */
|
||||
#define SRR1_PROGTRAP 0x00020000 /* Trap */
|
||||
#define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */
|
||||
|
||||
#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */
|
||||
#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */
|
||||
|
||||
@ -673,12 +723,15 @@
|
||||
* SPRG usage:
|
||||
*
|
||||
* All 64-bit:
|
||||
* - SPRG1 stores PACA pointer
|
||||
* - SPRG1 stores PACA pointer except 64-bit server in
|
||||
* HV mode in which case it is HSPRG0
|
||||
*
|
||||
* 64-bit server:
|
||||
* - SPRG0 unused (reserved for HV on Power4)
|
||||
* - SPRG2 scratch for exception vectors
|
||||
* - SPRG3 unused (user visible)
|
||||
* - HSPRG0 stores PACA in HV mode
|
||||
* - HSPRG1 scratch for "HV" exceptions
|
||||
*
|
||||
* 64-bit embedded
|
||||
* - SPRG0 generic exception scratch
|
||||
@ -741,6 +794,41 @@
|
||||
|
||||
#ifdef CONFIG_PPC_BOOK3S_64
|
||||
#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2
|
||||
#define SPRN_SPRG_HPACA SPRN_HSPRG0
|
||||
#define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1
|
||||
|
||||
#define GET_PACA(rX) \
|
||||
BEGIN_FTR_SECTION_NESTED(66); \
|
||||
mfspr rX,SPRN_SPRG_PACA; \
|
||||
FTR_SECTION_ELSE_NESTED(66); \
|
||||
mfspr rX,SPRN_SPRG_HPACA; \
|
||||
ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE_206, 66)
|
||||
|
||||
#define SET_PACA(rX) \
|
||||
BEGIN_FTR_SECTION_NESTED(66); \
|
||||
mtspr SPRN_SPRG_PACA,rX; \
|
||||
FTR_SECTION_ELSE_NESTED(66); \
|
||||
mtspr SPRN_SPRG_HPACA,rX; \
|
||||
ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE_206, 66)
|
||||
|
||||
#define GET_SCRATCH0(rX) \
|
||||
BEGIN_FTR_SECTION_NESTED(66); \
|
||||
mfspr rX,SPRN_SPRG_SCRATCH0; \
|
||||
FTR_SECTION_ELSE_NESTED(66); \
|
||||
mfspr rX,SPRN_SPRG_HSCRATCH0; \
|
||||
ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE_206, 66)
|
||||
|
||||
#define SET_SCRATCH0(rX) \
|
||||
BEGIN_FTR_SECTION_NESTED(66); \
|
||||
mtspr SPRN_SPRG_SCRATCH0,rX; \
|
||||
FTR_SECTION_ELSE_NESTED(66); \
|
||||
mtspr SPRN_SPRG_HSCRATCH0,rX; \
|
||||
ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE_206, 66)
|
||||
|
||||
#else /* CONFIG_PPC_BOOK3S_64 */
|
||||
#define GET_SCRATCH0(rX) mfspr rX,SPRN_SPRG_SCRATCH0
|
||||
#define SET_SCRATCH0(rX) mtspr SPRN_SPRG_SCRATCH0,rX
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PPC_BOOK3E_64
|
||||
@ -750,6 +838,10 @@
|
||||
#define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2
|
||||
#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6
|
||||
#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0
|
||||
|
||||
#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX
|
||||
#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PPC_BOOK3S_32
|
||||
@ -800,6 +892,8 @@
|
||||
#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* An mtfsf instruction with the L bit set. On CPUs that support this a
|
||||
* full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
|
||||
@ -894,6 +988,8 @@
|
||||
#define PV_POWER5p 0x003B
|
||||
#define PV_POWER7 0x003F
|
||||
#define PV_970FX 0x003C
|
||||
#define PV_POWER6 0x003E
|
||||
#define PV_POWER7 0x003F
|
||||
#define PV_630 0x0040
|
||||
#define PV_630p 0x0041
|
||||
#define PV_970MP 0x0044
|
||||
|
||||
165
arch/powerpc/include/asm/reg_a2.h
Normal file
165
arch/powerpc/include/asm/reg_a2.h
Normal file
@ -0,0 +1,165 @@
|
||||
/*
|
||||
* Register definitions specific to the A2 core
|
||||
*
|
||||
* Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_POWERPC_REG_A2_H__
|
||||
#define __ASM_POWERPC_REG_A2_H__
|
||||
|
||||
#define SPRN_TENSR 0x1b5
|
||||
#define SPRN_TENS 0x1b6 /* Thread ENable Set */
|
||||
#define SPRN_TENC 0x1b7 /* Thread ENable Clear */
|
||||
|
||||
#define SPRN_A2_CCR0 0x3f0 /* Core Configuration Register 0 */
|
||||
#define SPRN_A2_CCR1 0x3f1 /* Core Configuration Register 1 */
|
||||
#define SPRN_A2_CCR2 0x3f2 /* Core Configuration Register 2 */
|
||||
#define SPRN_MMUCR0 0x3fc /* MMU Control Register 0 */
|
||||
#define SPRN_MMUCR1 0x3fd /* MMU Control Register 1 */
|
||||
#define SPRN_MMUCR2 0x3fe /* MMU Control Register 2 */
|
||||
#define SPRN_MMUCR3 0x3ff /* MMU Control Register 3 */
|
||||
|
||||
#define SPRN_IAR 0x372
|
||||
|
||||
#define SPRN_IUCR0 0x3f3
|
||||
#define IUCR0_ICBI_ACK 0x1000
|
||||
|
||||
#define SPRN_XUCR0 0x3f6 /* Execution Unit Config Register 0 */
|
||||
|
||||
#define A2_IERAT_SIZE 16
|
||||
#define A2_DERAT_SIZE 32
|
||||
|
||||
/* A2 MMUCR0 bits */
|
||||
#define MMUCR0_ECL 0x80000000 /* Extended Class for TLB fills */
|
||||
#define MMUCR0_TID_NZ 0x40000000 /* TID is non-zero */
|
||||
#define MMUCR0_TS 0x10000000 /* Translation space for TLB fills */
|
||||
#define MMUCR0_TGS 0x20000000 /* Guest space for TLB fills */
|
||||
#define MMUCR0_TLBSEL 0x0c000000 /* TLB or ERAT target for TLB fills */
|
||||
#define MMUCR0_TLBSEL_U 0x00000000 /* TLBSEL = UTLB */
|
||||
#define MMUCR0_TLBSEL_I 0x08000000 /* TLBSEL = I-ERAT */
|
||||
#define MMUCR0_TLBSEL_D 0x0c000000 /* TLBSEL = D-ERAT */
|
||||
#define MMUCR0_LOCKSRSH 0x02000000 /* Use TLB lock on tlbsx. */
|
||||
#define MMUCR0_TID_MASK 0x000000ff /* TID field */
|
||||
|
||||
/* A2 MMUCR1 bits */
|
||||
#define MMUCR1_IRRE 0x80000000 /* I-ERAT round robin enable */
|
||||
#define MMUCR1_DRRE 0x40000000 /* D-ERAT round robin enable */
|
||||
#define MMUCR1_REE 0x20000000 /* Reference Exception Enable*/
|
||||
#define MMUCR1_CEE 0x10000000 /* Change exception enable */
|
||||
#define MMUCR1_CSINV_ALL 0x00000000 /* Inval ERAT on all CS evts */
|
||||
#define MMUCR1_CSINV_NISYNC 0x04000000 /* Inval ERAT on all ex isync*/
|
||||
#define MMUCR1_CSINV_NEVER 0x0c000000 /* Don't inval ERAT on CS */
|
||||
#define MMUCR1_ICTID 0x00080000 /* IERAT class field as TID */
|
||||
#define MMUCR1_ITTID 0x00040000 /* IERAT thdid field as TID */
|
||||
#define MMUCR1_DCTID 0x00020000 /* DERAT class field as TID */
|
||||
#define MMUCR1_DTTID 0x00010000 /* DERAT thdid field as TID */
|
||||
#define MMUCR1_DCCD 0x00008000 /* DERAT class ignore */
|
||||
#define MMUCR1_TLBWE_BINV 0x00004000 /* back invalidate on tlbwe */
|
||||
|
||||
/* A2 MMUCR2 bits */
|
||||
#define MMUCR2_PSSEL_SHIFT 4
|
||||
|
||||
/* A2 MMUCR3 bits */
|
||||
#define MMUCR3_THID 0x0000000f /* Thread ID */
|
||||
|
||||
/* *** ERAT TLB bits definitions */
|
||||
#define TLB0_EPN_MASK ASM_CONST(0xfffffffffffff000)
|
||||
#define TLB0_CLASS_MASK ASM_CONST(0x0000000000000c00)
|
||||
#define TLB0_CLASS_00 ASM_CONST(0x0000000000000000)
|
||||
#define TLB0_CLASS_01 ASM_CONST(0x0000000000000400)
|
||||
#define TLB0_CLASS_10 ASM_CONST(0x0000000000000800)
|
||||
#define TLB0_CLASS_11 ASM_CONST(0x0000000000000c00)
|
||||
#define TLB0_V ASM_CONST(0x0000000000000200)
|
||||
#define TLB0_X ASM_CONST(0x0000000000000100)
|
||||
#define TLB0_SIZE_MASK ASM_CONST(0x00000000000000f0)
|
||||
#define TLB0_SIZE_4K ASM_CONST(0x0000000000000010)
|
||||
#define TLB0_SIZE_64K ASM_CONST(0x0000000000000030)
|
||||
#define TLB0_SIZE_1M ASM_CONST(0x0000000000000050)
|
||||
#define TLB0_SIZE_16M ASM_CONST(0x0000000000000070)
|
||||
#define TLB0_SIZE_1G ASM_CONST(0x00000000000000a0)
|
||||
#define TLB0_THDID_MASK ASM_CONST(0x000000000000000f)
|
||||
#define TLB0_THDID_0 ASM_CONST(0x0000000000000001)
|
||||
#define TLB0_THDID_1 ASM_CONST(0x0000000000000002)
|
||||
#define TLB0_THDID_2 ASM_CONST(0x0000000000000004)
|
||||
#define TLB0_THDID_3 ASM_CONST(0x0000000000000008)
|
||||
#define TLB0_THDID_ALL ASM_CONST(0x000000000000000f)
|
||||
|
||||
#define TLB1_RESVATTR ASM_CONST(0x00f0000000000000)
|
||||
#define TLB1_U0 ASM_CONST(0x0008000000000000)
|
||||
#define TLB1_U1 ASM_CONST(0x0004000000000000)
|
||||
#define TLB1_U2 ASM_CONST(0x0002000000000000)
|
||||
#define TLB1_U3 ASM_CONST(0x0001000000000000)
|
||||
#define TLB1_R ASM_CONST(0x0000800000000000)
|
||||
#define TLB1_C ASM_CONST(0x0000400000000000)
|
||||
#define TLB1_RPN_MASK ASM_CONST(0x000003fffffff000)
|
||||
#define TLB1_W ASM_CONST(0x0000000000000800)
|
||||
#define TLB1_I ASM_CONST(0x0000000000000400)
|
||||
#define TLB1_M ASM_CONST(0x0000000000000200)
|
||||
#define TLB1_G ASM_CONST(0x0000000000000100)
|
||||
#define TLB1_E ASM_CONST(0x0000000000000080)
|
||||
#define TLB1_VF ASM_CONST(0x0000000000000040)
|
||||
#define TLB1_UX ASM_CONST(0x0000000000000020)
|
||||
#define TLB1_SX ASM_CONST(0x0000000000000010)
|
||||
#define TLB1_UW ASM_CONST(0x0000000000000008)
|
||||
#define TLB1_SW ASM_CONST(0x0000000000000004)
|
||||
#define TLB1_UR ASM_CONST(0x0000000000000002)
|
||||
#define TLB1_SR ASM_CONST(0x0000000000000001)
|
||||
|
||||
#ifdef CONFIG_PPC_EARLY_DEBUG_WSP
|
||||
#define WSP_UART_PHYS 0xffc000c000
|
||||
/* This needs to be careful chosen to hit a !0 congruence class
|
||||
* in the TLB since we bolt it in way 3, which is already occupied
|
||||
* by our linear mapping primary bolted entry in CC 0.
|
||||
*/
|
||||
#define WSP_UART_VIRT 0xf000000000001000
|
||||
#endif
|
||||
|
||||
/* A2 erativax attributes definitions */
|
||||
#define ERATIVAX_RS_IS_ALL 0x000
|
||||
#define ERATIVAX_RS_IS_TID 0x040
|
||||
#define ERATIVAX_RS_IS_CLASS 0x080
|
||||
#define ERATIVAX_RS_IS_FULLMATCH 0x0c0
|
||||
#define ERATIVAX_CLASS_00 0x000
|
||||
#define ERATIVAX_CLASS_01 0x010
|
||||
#define ERATIVAX_CLASS_10 0x020
|
||||
#define ERATIVAX_CLASS_11 0x030
|
||||
#define ERATIVAX_PSIZE_4K (TLB_PSIZE_4K >> 1)
|
||||
#define ERATIVAX_PSIZE_64K (TLB_PSIZE_64K >> 1)
|
||||
#define ERATIVAX_PSIZE_1M (TLB_PSIZE_1M >> 1)
|
||||
#define ERATIVAX_PSIZE_16M (TLB_PSIZE_16M >> 1)
|
||||
#define ERATIVAX_PSIZE_1G (TLB_PSIZE_1G >> 1)
|
||||
|
||||
/* A2 eratilx attributes definitions */
|
||||
#define ERATILX_T_ALL 0
|
||||
#define ERATILX_T_TID 1
|
||||
#define ERATILX_T_TGS 2
|
||||
#define ERATILX_T_FULLMATCH 3
|
||||
#define ERATILX_T_CLASS0 4
|
||||
#define ERATILX_T_CLASS1 5
|
||||
#define ERATILX_T_CLASS2 6
|
||||
#define ERATILX_T_CLASS3 7
|
||||
|
||||
/* XUCR0 bits */
|
||||
#define XUCR0_TRACE_UM_T0 0x40000000 /* Thread 0 */
|
||||
#define XUCR0_TRACE_UM_T1 0x20000000 /* Thread 1 */
|
||||
#define XUCR0_TRACE_UM_T2 0x10000000 /* Thread 2 */
|
||||
#define XUCR0_TRACE_UM_T3 0x08000000 /* Thread 3 */
|
||||
|
||||
/* A2 CCR0 register */
|
||||
#define A2_CCR0_PME_DISABLED 0x00000000
|
||||
#define A2_CCR0_PME_SLEEP 0x40000000
|
||||
#define A2_CCR0_PME_RVW 0x80000000
|
||||
#define A2_CCR0_PME_DISABLED2 0xc0000000
|
||||
|
||||
/* A2 CCR2 register */
|
||||
#define A2_CCR2_ERAT_ONLY_MODE 0x00000001
|
||||
#define A2_CCR2_ENABLE_ICSWX 0x00000002
|
||||
#define A2_CCR2_ENABLE_PC 0x20000000
|
||||
#define A2_CCR2_ENABLE_TRACE 0x40000000
|
||||
|
||||
#endif /* __ASM_POWERPC_REG_A2_H__ */
|
||||
@ -27,10 +27,12 @@
|
||||
#define MSR_CM (1<<31) /* Computation Mode (0=32-bit, 1=64-bit) */
|
||||
|
||||
#if defined(CONFIG_PPC_BOOK3E_64)
|
||||
#define MSR_64BIT MSR_CM
|
||||
|
||||
#define MSR_ MSR_ME | MSR_CE
|
||||
#define MSR_KERNEL MSR_ | MSR_CM
|
||||
#define MSR_KERNEL MSR_ | MSR_64BIT
|
||||
#define MSR_USER32 MSR_ | MSR_PR | MSR_EE | MSR_DE
|
||||
#define MSR_USER64 MSR_USER32 | MSR_CM | MSR_DE
|
||||
#define MSR_USER64 MSR_USER32 | MSR_64BIT
|
||||
#elif defined (CONFIG_40x)
|
||||
#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
|
||||
#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
|
||||
@ -81,6 +83,10 @@
|
||||
#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
|
||||
#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
|
||||
#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
|
||||
#define SPRN_IVOR38 0x1B0 /* Interrupt Vector Offset Register 38 */
|
||||
#define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 */
|
||||
#define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 */
|
||||
#define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 */
|
||||
#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
|
||||
#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
|
||||
#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
|
||||
|
||||
@ -158,7 +158,50 @@ struct rtas_error_log {
|
||||
unsigned long target:4; /* Target of failed operation */
|
||||
unsigned long type:8; /* General event or error*/
|
||||
unsigned long extended_log_length:32; /* length in bytes */
|
||||
unsigned char buffer[1];
|
||||
unsigned char buffer[1]; /* Start of extended log */
|
||||
/* Variable length. */
|
||||
};
|
||||
|
||||
#define RTAS_V6EXT_LOG_FORMAT_EVENT_LOG 14
|
||||
|
||||
#define RTAS_V6EXT_COMPANY_ID_IBM (('I' << 24) | ('B' << 16) | ('M' << 8))
|
||||
|
||||
/* RTAS general extended event log, Version 6. The extended log starts
|
||||
* from "buffer" field of struct rtas_error_log defined above.
|
||||
*/
|
||||
struct rtas_ext_event_log_v6 {
|
||||
/* Byte 0 */
|
||||
uint32_t log_valid:1; /* 1:Log valid */
|
||||
uint32_t unrecoverable_error:1; /* 1:Unrecoverable error */
|
||||
uint32_t recoverable_error:1; /* 1:recoverable (correctable */
|
||||
/* or successfully retried) */
|
||||
uint32_t degraded_operation:1; /* 1:Unrecoverable err, bypassed*/
|
||||
/* - degraded operation (e.g. */
|
||||
/* CPU or mem taken off-line) */
|
||||
uint32_t predictive_error:1;
|
||||
uint32_t new_log:1; /* 1:"New" log (Always 1 for */
|
||||
/* data returned from RTAS */
|
||||
uint32_t big_endian:1; /* 1: Big endian */
|
||||
uint32_t :1; /* reserved */
|
||||
/* Byte 1 */
|
||||
uint32_t :8; /* reserved */
|
||||
/* Byte 2 */
|
||||
uint32_t powerpc_format:1; /* Set to 1 (indicating log is */
|
||||
/* in PowerPC format */
|
||||
uint32_t :3; /* reserved */
|
||||
uint32_t log_format:4; /* Log format indicator. Define */
|
||||
/* format used for byte 12-2047 */
|
||||
/* Byte 3 */
|
||||
uint32_t :8; /* reserved */
|
||||
/* Byte 4-11 */
|
||||
uint8_t reserved[8]; /* reserved */
|
||||
/* Byte 12-15 */
|
||||
uint32_t company_id; /* Company ID of the company */
|
||||
/* that defines the format for */
|
||||
/* the vendor specific log type */
|
||||
/* Byte 16-end of log */
|
||||
uint8_t vendor_log[1]; /* Start of vendor specific log */
|
||||
/* Variable length. */
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
156
arch/powerpc/include/asm/scom.h
Normal file
156
arch/powerpc/include/asm/scom.h
Normal file
@ -0,0 +1,156 @@
|
||||
/*
|
||||
* Copyright 2010 Benjamin Herrenschmidt, IBM Corp
|
||||
* <benh@kernel.crashing.org>
|
||||
* and David Gibson, IBM Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
* the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _ASM_POWERPC_SCOM_H
|
||||
#define _ASM_POWERPC_SCOM_H
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef CONFIG_PPC_SCOM
|
||||
|
||||
/*
|
||||
* The SCOM bus is a sideband bus used for accessing various internal
|
||||
* registers of the processor or the chipset. The implementation details
|
||||
* differ between processors and platforms, and the access method as
|
||||
* well.
|
||||
*
|
||||
* This API allows to "map" ranges of SCOM register numbers associated
|
||||
* with a given SCOM controller. The later must be represented by a
|
||||
* device node, though some implementations might support NULL if there
|
||||
* is no possible ambiguity
|
||||
*
|
||||
* Then, scom_read/scom_write can be used to accesses registers inside
|
||||
* that range. The argument passed is a register number relative to
|
||||
* the beginning of the range mapped.
|
||||
*/
|
||||
|
||||
typedef void *scom_map_t;
|
||||
|
||||
/* Value for an invalid SCOM map */
|
||||
#define SCOM_MAP_INVALID (NULL)
|
||||
|
||||
/* The scom_controller data structure is what the platform passes
|
||||
* to the core code in scom_init, it provides the actual implementation
|
||||
* of all the SCOM functions
|
||||
*/
|
||||
struct scom_controller {
|
||||
scom_map_t (*map)(struct device_node *ctrl_dev, u64 reg, u64 count);
|
||||
void (*unmap)(scom_map_t map);
|
||||
|
||||
u64 (*read)(scom_map_t map, u32 reg);
|
||||
void (*write)(scom_map_t map, u32 reg, u64 value);
|
||||
};
|
||||
|
||||
extern const struct scom_controller *scom_controller;
|
||||
|
||||
/**
|
||||
* scom_init - Initialize the SCOM backend, called by the platform
|
||||
* @controller: The platform SCOM controller
|
||||
*/
|
||||
static inline void scom_init(const struct scom_controller *controller)
|
||||
{
|
||||
scom_controller = controller;
|
||||
}
|
||||
|
||||
/**
|
||||
* scom_map_ok - Test is a SCOM mapping is successful
|
||||
* @map: The result of scom_map to test
|
||||
*/
|
||||
static inline int scom_map_ok(scom_map_t map)
|
||||
{
|
||||
return map != SCOM_MAP_INVALID;
|
||||
}
|
||||
|
||||
/**
|
||||
* scom_map - Map a block of SCOM registers
|
||||
* @ctrl_dev: Device node of the SCOM controller
|
||||
* some implementations allow NULL here
|
||||
* @reg: first SCOM register to map
|
||||
* @count: Number of SCOM registers to map
|
||||
*/
|
||||
|
||||
static inline scom_map_t scom_map(struct device_node *ctrl_dev,
|
||||
u64 reg, u64 count)
|
||||
{
|
||||
return scom_controller->map(ctrl_dev, reg, count);
|
||||
}
|
||||
|
||||
/**
|
||||
* scom_find_parent - Find the SCOM controller for a device
|
||||
* @dev: OF node of the device
|
||||
*
|
||||
* This is not meant for general usage, but in combination with
|
||||
* scom_map() allows to map registers not represented by the
|
||||
* device own scom-reg property. Useful for applying HW workarounds
|
||||
* on things not properly represented in the device-tree for example.
|
||||
*/
|
||||
struct device_node *scom_find_parent(struct device_node *dev);
|
||||
|
||||
|
||||
/**
|
||||
* scom_map_device - Map a device's block of SCOM registers
|
||||
* @dev: OF node of the device
|
||||
* @index: Register bank index (index in "scom-reg" property)
|
||||
*
|
||||
* This function will use the device-tree binding for SCOM which
|
||||
* is to follow "scom-parent" properties until it finds a node with
|
||||
* a "scom-controller" property to find the controller. It will then
|
||||
* use the "scom-reg" property which is made of reg/count pairs,
|
||||
* each of them having a size defined by the controller's #scom-cells
|
||||
* property
|
||||
*/
|
||||
extern scom_map_t scom_map_device(struct device_node *dev, int index);
|
||||
|
||||
|
||||
/**
|
||||
* scom_unmap - Unmap a block of SCOM registers
|
||||
* @map: Result of scom_map is to be unmapped
|
||||
*/
|
||||
static inline void scom_unmap(scom_map_t map)
|
||||
{
|
||||
if (scom_map_ok(map))
|
||||
scom_controller->unmap(map);
|
||||
}
|
||||
|
||||
/**
|
||||
* scom_read - Read a SCOM register
|
||||
* @map: Result of scom_map
|
||||
* @reg: Register index within that map
|
||||
*/
|
||||
static inline u64 scom_read(scom_map_t map, u32 reg)
|
||||
{
|
||||
return scom_controller->read(map, reg);
|
||||
}
|
||||
|
||||
/**
|
||||
* scom_write - Write to a SCOM register
|
||||
* @map: Result of scom_map
|
||||
* @reg: Register index within that map
|
||||
* @value: Value to write
|
||||
*/
|
||||
static inline void scom_write(scom_map_t map, u32 reg, u64 value)
|
||||
{
|
||||
scom_controller->write(map, reg, value);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PPC_SCOM */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* _ASM_POWERPC_SCOM_H */
|
||||
@ -20,6 +20,7 @@
|
||||
#include <linux/threads.h>
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/irqreturn.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
@ -29,14 +30,32 @@
|
||||
#include <asm/percpu.h>
|
||||
|
||||
extern int boot_cpuid;
|
||||
extern int boot_cpu_count;
|
||||
|
||||
extern void cpu_die(void);
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
|
||||
extern void smp_send_debugger_break(int cpu);
|
||||
extern void smp_message_recv(int);
|
||||
struct smp_ops_t {
|
||||
void (*message_pass)(int cpu, int msg);
|
||||
#ifdef CONFIG_PPC_SMP_MUXED_IPI
|
||||
void (*cause_ipi)(int cpu, unsigned long data);
|
||||
#endif
|
||||
int (*probe)(void);
|
||||
int (*kick_cpu)(int nr);
|
||||
void (*setup_cpu)(int nr);
|
||||
void (*bringup_done)(void);
|
||||
void (*take_timebase)(void);
|
||||
void (*give_timebase)(void);
|
||||
int (*cpu_disable)(void);
|
||||
void (*cpu_die)(unsigned int nr);
|
||||
int (*cpu_bootable)(unsigned int nr);
|
||||
};
|
||||
|
||||
extern void smp_send_debugger_break(void);
|
||||
extern void start_secondary_resume(void);
|
||||
extern void __devinit smp_generic_give_timebase(void);
|
||||
extern void __devinit smp_generic_take_timebase(void);
|
||||
|
||||
DECLARE_PER_CPU(unsigned int, cpu_pvr);
|
||||
|
||||
@ -93,13 +112,16 @@ extern int cpu_to_core_id(int cpu);
|
||||
#define PPC_MSG_CALL_FUNC_SINGLE 2
|
||||
#define PPC_MSG_DEBUGGER_BREAK 3
|
||||
|
||||
/*
|
||||
* irq controllers that have dedicated ipis per message and don't
|
||||
* need additional code in the action handler may use this
|
||||
*/
|
||||
/* for irq controllers that have dedicated ipis per message (4) */
|
||||
extern int smp_request_message_ipi(int virq, int message);
|
||||
extern const char *smp_ipi_name[];
|
||||
|
||||
/* for irq controllers with only a single ipi */
|
||||
extern void smp_muxed_ipi_set_data(int cpu, unsigned long data);
|
||||
extern void smp_muxed_ipi_message_pass(int cpu, int msg);
|
||||
extern void smp_muxed_ipi_resend(void);
|
||||
extern irqreturn_t smp_ipi_demux(void);
|
||||
|
||||
void smp_init_iSeries(void);
|
||||
void smp_init_pSeries(void);
|
||||
void smp_init_cell(void);
|
||||
@ -149,7 +171,7 @@ extern int smt_enabled_at_boot;
|
||||
|
||||
extern int smp_mpic_probe(void);
|
||||
extern void smp_mpic_setup_cpu(int cpu);
|
||||
extern void smp_generic_kick_cpu(int nr);
|
||||
extern int smp_generic_kick_cpu(int nr);
|
||||
|
||||
extern void smp_generic_give_timebase(void);
|
||||
extern void smp_generic_take_timebase(void);
|
||||
@ -169,6 +191,8 @@ extern unsigned long __secondary_hold_spinloop;
|
||||
extern unsigned long __secondary_hold_acknowledge;
|
||||
extern char __secondary_hold;
|
||||
|
||||
extern irqreturn_t debug_ipi_action(int irq, void *data);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
@ -219,8 +219,6 @@ extern int mem_init_done; /* set on boot once kmalloc can be called */
|
||||
extern int init_bootmem_done; /* set once bootmem is available */
|
||||
extern phys_addr_t memory_limit;
|
||||
extern unsigned long klimit;
|
||||
|
||||
extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
|
||||
extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
|
||||
|
||||
extern int powersave_nap; /* set if nap mode can be used in idle loop */
|
||||
|
||||
@ -79,6 +79,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
|
||||
|
||||
#elif defined(CONFIG_PPC_STD_MMU_64)
|
||||
|
||||
#define MMU_NO_CONTEXT 0
|
||||
|
||||
/*
|
||||
* TLB flushing for 64-bit hash-MMU CPUs
|
||||
*/
|
||||
|
||||
@ -52,6 +52,7 @@ extern void __init udbg_init_44x_as1(void);
|
||||
extern void __init udbg_init_40x_realmode(void);
|
||||
extern void __init udbg_init_cpm(void);
|
||||
extern void __init udbg_init_usbgecko(void);
|
||||
extern void __init udbg_init_wsp(void);
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* _ASM_POWERPC_UDBG_H */
|
||||
|
||||
14
arch/powerpc/include/asm/wsp.h
Normal file
14
arch/powerpc/include/asm/wsp.h
Normal file
@ -0,0 +1,14 @@
|
||||
/*
|
||||
* Copyright 2011 Michael Ellerman, IBM Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
#ifndef __ASM_POWERPC_WSP_H
|
||||
#define __ASM_POWERPC_WSP_H
|
||||
|
||||
extern int wsp_get_chip_id(struct device_node *dn);
|
||||
|
||||
#endif /* __ASM_POWERPC_WSP_H */
|
||||
142
arch/powerpc/include/asm/xics.h
Normal file
142
arch/powerpc/include/asm/xics.h
Normal file
@ -0,0 +1,142 @@
|
||||
/*
|
||||
* Common definitions accross all variants of ICP and ICS interrupt
|
||||
* controllers.
|
||||
*/
|
||||
|
||||
#ifndef _XICS_H
|
||||
#define _XICS_H
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#define XICS_IPI 2
|
||||
#define XICS_IRQ_SPURIOUS 0
|
||||
|
||||
/* Want a priority other than 0. Various HW issues require this. */
|
||||
#define DEFAULT_PRIORITY 5
|
||||
|
||||
/*
|
||||
* Mark IPIs as higher priority so we can take them inside interrupts that
|
||||
* arent marked IRQF_DISABLED
|
||||
*/
|
||||
#define IPI_PRIORITY 4
|
||||
|
||||
/* The least favored priority */
|
||||
#define LOWEST_PRIORITY 0xFF
|
||||
|
||||
/* The number of priorities defined above */
|
||||
#define MAX_NUM_PRIORITIES 3
|
||||
|
||||
/* Native ICP */
|
||||
extern int icp_native_init(void);
|
||||
|
||||
/* PAPR ICP */
|
||||
extern int icp_hv_init(void);
|
||||
|
||||
/* ICP ops */
|
||||
struct icp_ops {
|
||||
unsigned int (*get_irq)(void);
|
||||
void (*eoi)(struct irq_data *d);
|
||||
void (*set_priority)(unsigned char prio);
|
||||
void (*teardown_cpu)(void);
|
||||
void (*flush_ipi)(void);
|
||||
#ifdef CONFIG_SMP
|
||||
void (*cause_ipi)(int cpu, unsigned long data);
|
||||
irq_handler_t ipi_action;
|
||||
#endif
|
||||
};
|
||||
|
||||
extern const struct icp_ops *icp_ops;
|
||||
|
||||
/* Native ICS */
|
||||
extern int ics_native_init(void);
|
||||
|
||||
/* RTAS ICS */
|
||||
extern int ics_rtas_init(void);
|
||||
|
||||
/* ICS instance, hooked up to chip_data of an irq */
|
||||
struct ics {
|
||||
struct list_head link;
|
||||
int (*map)(struct ics *ics, unsigned int virq);
|
||||
void (*mask_unknown)(struct ics *ics, unsigned long vec);
|
||||
long (*get_server)(struct ics *ics, unsigned long vec);
|
||||
int (*host_match)(struct ics *ics, struct device_node *node);
|
||||
char data[];
|
||||
};
|
||||
|
||||
/* Commons */
|
||||
extern unsigned int xics_default_server;
|
||||
extern unsigned int xics_default_distrib_server;
|
||||
extern unsigned int xics_interrupt_server_size;
|
||||
extern struct irq_host *xics_host;
|
||||
|
||||
struct xics_cppr {
|
||||
unsigned char stack[MAX_NUM_PRIORITIES];
|
||||
int index;
|
||||
};
|
||||
|
||||
DECLARE_PER_CPU(struct xics_cppr, xics_cppr);
|
||||
|
||||
static inline void xics_push_cppr(unsigned int vec)
|
||||
{
|
||||
struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
|
||||
|
||||
if (WARN_ON(os_cppr->index >= MAX_NUM_PRIORITIES - 1))
|
||||
return;
|
||||
|
||||
if (vec == XICS_IPI)
|
||||
os_cppr->stack[++os_cppr->index] = IPI_PRIORITY;
|
||||
else
|
||||
os_cppr->stack[++os_cppr->index] = DEFAULT_PRIORITY;
|
||||
}
|
||||
|
||||
static inline unsigned char xics_pop_cppr(void)
|
||||
{
|
||||
struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
|
||||
|
||||
if (WARN_ON(os_cppr->index < 1))
|
||||
return LOWEST_PRIORITY;
|
||||
|
||||
return os_cppr->stack[--os_cppr->index];
|
||||
}
|
||||
|
||||
static inline void xics_set_base_cppr(unsigned char cppr)
|
||||
{
|
||||
struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
|
||||
|
||||
/* we only really want to set the priority when there's
|
||||
* just one cppr value on the stack
|
||||
*/
|
||||
WARN_ON(os_cppr->index != 0);
|
||||
|
||||
os_cppr->stack[0] = cppr;
|
||||
}
|
||||
|
||||
static inline unsigned char xics_cppr_top(void)
|
||||
{
|
||||
struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
|
||||
|
||||
return os_cppr->stack[os_cppr->index];
|
||||
}
|
||||
|
||||
DECLARE_PER_CPU_SHARED_ALIGNED(unsigned long, xics_ipi_message);
|
||||
|
||||
extern void xics_init(void);
|
||||
extern void xics_setup_cpu(void);
|
||||
extern void xics_update_irq_servers(void);
|
||||
extern void xics_set_cpu_giq(unsigned int gserver, unsigned int join);
|
||||
extern void xics_mask_unknown_vec(unsigned int vec);
|
||||
extern irqreturn_t xics_ipi_dispatch(int cpu);
|
||||
extern int xics_smp_probe(void);
|
||||
extern void xics_register_ics(struct ics *ics);
|
||||
extern void xics_teardown_cpu(void);
|
||||
extern void xics_kexec_teardown_cpu(int secondary);
|
||||
extern void xics_migrate_irqs_away(void);
|
||||
#ifdef CONFIG_SMP
|
||||
extern int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
|
||||
unsigned int strict_check);
|
||||
#else
|
||||
#define xics_get_irq_server(virq, cpumask, strict_check) (xics_default_server)
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _XICS_H */
|
||||
@ -38,11 +38,14 @@ obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \
|
||||
paca.o nvram_64.o firmware.o
|
||||
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
|
||||
obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o
|
||||
obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power7.o
|
||||
obj64-$(CONFIG_RELOCATABLE) += reloc_64.o
|
||||
obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_book3e.o
|
||||
obj-$(CONFIG_PPC_A2) += cpu_setup_a2.o
|
||||
obj-$(CONFIG_PPC64) += vdso64/
|
||||
obj-$(CONFIG_ALTIVEC) += vecemu.o
|
||||
obj-$(CONFIG_PPC_970_NAP) += idle_power4.o
|
||||
obj-$(CONFIG_PPC_P7_NAP) += idle_power7.o
|
||||
obj-$(CONFIG_PPC_OF) += of_platform.o prom_parse.o
|
||||
obj-$(CONFIG_PPC_CLOCK) += clock.o
|
||||
procfs-y := proc_powerpc.o
|
||||
@ -75,7 +78,6 @@ obj-$(CONFIG_PPC_FSL_BOOK3E) += cpu_setup_fsl_booke.o dbell.o
|
||||
obj-$(CONFIG_PPC_BOOK3E_64) += dbell.o
|
||||
|
||||
extra-y := head_$(CONFIG_WORD_SIZE).o
|
||||
extra-$(CONFIG_PPC_BOOK3E_32) := head_new_booke.o
|
||||
extra-$(CONFIG_40x) := head_40x.o
|
||||
extra-$(CONFIG_44x) := head_44x.o
|
||||
extra-$(CONFIG_FSL_BOOKE) := head_fsl_booke.o
|
||||
@ -103,6 +105,8 @@ obj-$(CONFIG_KEXEC) += machine_kexec.o crash.o \
|
||||
obj-$(CONFIG_AUDIT) += audit.o
|
||||
obj64-$(CONFIG_AUDIT) += compat_audit.o
|
||||
|
||||
obj-$(CONFIG_PPC_IO_WORKAROUNDS) += io-workarounds.o
|
||||
|
||||
obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
|
||||
obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
|
||||
obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o
|
||||
|
||||
@ -74,6 +74,7 @@ int main(void)
|
||||
DEFINE(AUDITCONTEXT, offsetof(struct task_struct, audit_context));
|
||||
DEFINE(SIGSEGV, SIGSEGV);
|
||||
DEFINE(NMI_MASK, NMI_MASK);
|
||||
DEFINE(THREAD_DSCR, offsetof(struct thread_struct, dscr));
|
||||
#else
|
||||
DEFINE(THREAD_INFO, offsetof(struct task_struct, stack));
|
||||
#endif /* CONFIG_PPC64 */
|
||||
|
||||
114
arch/powerpc/kernel/cpu_setup_a2.S
Normal file
114
arch/powerpc/kernel/cpu_setup_a2.S
Normal file
@ -0,0 +1,114 @@
|
||||
/*
|
||||
* A2 specific assembly support code
|
||||
*
|
||||
* Copyright 2009 Ben Herrenschmidt, IBM Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/ppc_asm.h>
|
||||
#include <asm/ppc-opcode.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/reg_a2.h>
|
||||
#include <asm/reg.h>
|
||||
#include <asm/thread_info.h>
|
||||
|
||||
/*
|
||||
* Disable thdid and class fields in ERATs to bump PID to full 14 bits capacity.
|
||||
* This also prevents external LPID accesses but that isn't a problem when not a
|
||||
* guest. Under PV, this setting will be ignored and MMUCR will return the right
|
||||
* number of PID bits we can use.
|
||||
*/
|
||||
#define MMUCR1_EXTEND_PID \
|
||||
(MMUCR1_ICTID | MMUCR1_ITTID | MMUCR1_DCTID | \
|
||||
MMUCR1_DTTID | MMUCR1_DCCD)
|
||||
|
||||
/*
|
||||
* Use extended PIDs if enabled.
|
||||
* Don't clear the ERATs on context sync events and enable I & D LRU.
|
||||
* Enable ERAT back invalidate when tlbwe overwrites an entry.
|
||||
*/
|
||||
#define INITIAL_MMUCR1 \
|
||||
(MMUCR1_EXTEND_PID | MMUCR1_CSINV_NEVER | MMUCR1_IRRE | \
|
||||
MMUCR1_DRRE | MMUCR1_TLBWE_BINV)
|
||||
|
||||
_GLOBAL(__setup_cpu_a2)
|
||||
/* Some of these are actually thread local and some are
|
||||
* core local but doing it always won't hurt
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_PPC_WSP_COPRO
|
||||
/* Make sure ACOP starts out as zero */
|
||||
li r3,0
|
||||
mtspr SPRN_ACOP,r3
|
||||
|
||||
/* Enable icswx instruction */
|
||||
mfspr r3,SPRN_A2_CCR2
|
||||
ori r3,r3,A2_CCR2_ENABLE_ICSWX
|
||||
mtspr SPRN_A2_CCR2,r3
|
||||
|
||||
/* Unmask all CTs in HACOP */
|
||||
li r3,-1
|
||||
mtspr SPRN_HACOP,r3
|
||||
#endif /* CONFIG_PPC_WSP_COPRO */
|
||||
|
||||
/* Enable doorbell */
|
||||
mfspr r3,SPRN_A2_CCR2
|
||||
oris r3,r3,A2_CCR2_ENABLE_PC@h
|
||||
mtspr SPRN_A2_CCR2,r3
|
||||
isync
|
||||
|
||||
/* Setup CCR0 to disable power saving for now as it's busted
|
||||
* in the current implementations. Setup CCR1 to wake on
|
||||
* interrupts normally (we write the default value but who
|
||||
* knows what FW may have clobbered...)
|
||||
*/
|
||||
li r3,0
|
||||
mtspr SPRN_A2_CCR0, r3
|
||||
LOAD_REG_IMMEDIATE(r3,0x0f0f0f0f)
|
||||
mtspr SPRN_A2_CCR1, r3
|
||||
|
||||
/* Initialise MMUCR1 */
|
||||
lis r3,INITIAL_MMUCR1@h
|
||||
ori r3,r3,INITIAL_MMUCR1@l
|
||||
mtspr SPRN_MMUCR1,r3
|
||||
|
||||
/* Set MMUCR2 to enable 4K, 64K, 1M, 16M and 1G pages */
|
||||
LOAD_REG_IMMEDIATE(r3, 0x000a7531)
|
||||
mtspr SPRN_MMUCR2,r3
|
||||
|
||||
/* Set MMUCR3 to write all thids bit to the TLB */
|
||||
LOAD_REG_IMMEDIATE(r3, 0x0000000f)
|
||||
mtspr SPRN_MMUCR3,r3
|
||||
|
||||
/* Don't do ERAT stuff if running guest mode */
|
||||
mfmsr r3
|
||||
andis. r0,r3,MSR_GS@h
|
||||
bne 1f
|
||||
|
||||
/* Now set the I-ERAT watermark to 15 */
|
||||
lis r4,(MMUCR0_TLBSEL_I|MMUCR0_ECL)@h
|
||||
mtspr SPRN_MMUCR0, r4
|
||||
li r4,A2_IERAT_SIZE-1
|
||||
PPC_ERATWE(r4,r4,3)
|
||||
|
||||
/* Now set the D-ERAT watermark to 31 */
|
||||
lis r4,(MMUCR0_TLBSEL_D|MMUCR0_ECL)@h
|
||||
mtspr SPRN_MMUCR0, r4
|
||||
li r4,A2_DERAT_SIZE-1
|
||||
PPC_ERATWE(r4,r4,3)
|
||||
|
||||
/* And invalidate the beast just in case. That won't get rid of
|
||||
* a bolted entry though it will be in LRU and so will go away eventually
|
||||
* but let's not bother for now
|
||||
*/
|
||||
PPC_ERATILX(0,0,0)
|
||||
1:
|
||||
blr
|
||||
|
||||
_GLOBAL(__restore_cpu_a2)
|
||||
b __setup_cpu_a2
|
||||
@ -88,6 +88,9 @@ _GLOBAL(__setup_cpu_e5500)
|
||||
bl __e500_dcache_setup
|
||||
#ifdef CONFIG_PPC_BOOK3E_64
|
||||
bl .__setup_base_ivors
|
||||
bl .setup_perfmon_ivor
|
||||
bl .setup_doorbell_ivors
|
||||
bl .setup_ehv_ivors
|
||||
#else
|
||||
bl __setup_e500mc_ivors
|
||||
#endif
|
||||
|
||||
91
arch/powerpc/kernel/cpu_setup_power7.S
Normal file
91
arch/powerpc/kernel/cpu_setup_power7.S
Normal file
@ -0,0 +1,91 @@
|
||||
/*
|
||||
* This file contains low level CPU setup functions.
|
||||
* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/cputable.h>
|
||||
#include <asm/ppc_asm.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/cache.h>
|
||||
|
||||
/* Entry: r3 = crap, r4 = ptr to cputable entry
|
||||
*
|
||||
* Note that we can be called twice for pseudo-PVRs
|
||||
*/
|
||||
_GLOBAL(__setup_cpu_power7)
|
||||
mflr r11
|
||||
bl __init_hvmode_206
|
||||
mtlr r11
|
||||
beqlr
|
||||
li r0,0
|
||||
mtspr SPRN_LPID,r0
|
||||
bl __init_LPCR
|
||||
bl __init_TLB
|
||||
mtlr r11
|
||||
blr
|
||||
|
||||
_GLOBAL(__restore_cpu_power7)
|
||||
mflr r11
|
||||
mfmsr r3
|
||||
rldicl. r0,r3,4,63
|
||||
beqlr
|
||||
li r0,0
|
||||
mtspr SPRN_LPID,r0
|
||||
bl __init_LPCR
|
||||
bl __init_TLB
|
||||
mtlr r11
|
||||
blr
|
||||
|
||||
__init_hvmode_206:
|
||||
/* Disable CPU_FTR_HVMODE_206 and exit if MSR:HV is not set */
|
||||
mfmsr r3
|
||||
rldicl. r0,r3,4,63
|
||||
bnelr
|
||||
ld r5,CPU_SPEC_FEATURES(r4)
|
||||
LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE_206)
|
||||
xor r5,r5,r6
|
||||
std r5,CPU_SPEC_FEATURES(r4)
|
||||
blr
|
||||
|
||||
__init_LPCR:
|
||||
/* Setup a sane LPCR:
|
||||
*
|
||||
* LPES = 0b01 (HSRR0/1 used for 0x500)
|
||||
* PECE = 0b111
|
||||
* DPFD = 4
|
||||
*
|
||||
* Other bits untouched for now
|
||||
*/
|
||||
mfspr r3,SPRN_LPCR
|
||||
ori r3,r3,(LPCR_LPES0|LPCR_LPES1)
|
||||
xori r3,r3, LPCR_LPES0
|
||||
ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
|
||||
li r5,7
|
||||
sldi r5,r5,LPCR_DPFD_SH
|
||||
andc r3,r3,r5
|
||||
li r5,4
|
||||
sldi r5,r5,LPCR_DPFD_SH
|
||||
or r3,r3,r5
|
||||
mtspr SPRN_LPCR,r3
|
||||
isync
|
||||
blr
|
||||
|
||||
__init_TLB:
|
||||
/* Clear the TLB */
|
||||
li r6,128
|
||||
mtctr r6
|
||||
li r7,0xc00 /* IS field = 0b11 */
|
||||
ptesync
|
||||
2: tlbiel r7
|
||||
addi r7,r7,0x1000
|
||||
bdnz 2b
|
||||
ptesync
|
||||
1: blr
|
||||
@ -62,10 +62,12 @@ extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __setup_cpu_a2(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __restore_cpu_pa6t(void);
|
||||
extern void __restore_cpu_ppc970(void);
|
||||
extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __restore_cpu_power7(void);
|
||||
extern void __restore_cpu_a2(void);
|
||||
#endif /* CONFIG_PPC64 */
|
||||
#if defined(CONFIG_E500)
|
||||
extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
|
||||
@ -199,7 +201,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_name = "POWER4 (gp)",
|
||||
.cpu_features = CPU_FTRS_POWER4,
|
||||
.cpu_user_features = COMMON_USER_POWER4,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE,
|
||||
.mmu_features = MMU_FTRS_POWER4,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
@ -214,7 +216,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_name = "POWER4+ (gq)",
|
||||
.cpu_features = CPU_FTRS_POWER4,
|
||||
.cpu_user_features = COMMON_USER_POWER4,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE,
|
||||
.mmu_features = MMU_FTRS_POWER4,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
@ -230,7 +232,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_features = CPU_FTRS_PPC970,
|
||||
.cpu_user_features = COMMON_USER_POWER4 |
|
||||
PPC_FEATURE_HAS_ALTIVEC_COMP,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE,
|
||||
.mmu_features = MMU_FTRS_PPC970,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
@ -248,7 +250,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_features = CPU_FTRS_PPC970,
|
||||
.cpu_user_features = COMMON_USER_POWER4 |
|
||||
PPC_FEATURE_HAS_ALTIVEC_COMP,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE,
|
||||
.mmu_features = MMU_FTRS_PPC970,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
@ -284,7 +286,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_features = CPU_FTRS_PPC970,
|
||||
.cpu_user_features = COMMON_USER_POWER4 |
|
||||
PPC_FEATURE_HAS_ALTIVEC_COMP,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE,
|
||||
.mmu_features = MMU_FTRS_PPC970,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
@ -302,7 +304,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_features = CPU_FTRS_PPC970,
|
||||
.cpu_user_features = COMMON_USER_POWER4 |
|
||||
PPC_FEATURE_HAS_ALTIVEC_COMP,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE,
|
||||
.mmu_features = MMU_FTRS_PPC970,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
@ -318,7 +320,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_name = "POWER5 (gr)",
|
||||
.cpu_features = CPU_FTRS_POWER5,
|
||||
.cpu_user_features = COMMON_USER_POWER5,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE,
|
||||
.mmu_features = MMU_FTRS_POWER5,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 6,
|
||||
@ -338,7 +340,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_name = "POWER5+ (gs)",
|
||||
.cpu_features = CPU_FTRS_POWER5,
|
||||
.cpu_user_features = COMMON_USER_POWER5_PLUS,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE,
|
||||
.mmu_features = MMU_FTRS_POWER5,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 6,
|
||||
@ -354,7 +356,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_name = "POWER5+ (gs)",
|
||||
.cpu_features = CPU_FTRS_POWER5,
|
||||
.cpu_user_features = COMMON_USER_POWER5_PLUS,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE,
|
||||
.mmu_features = MMU_FTRS_POWER5,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 6,
|
||||
@ -371,7 +373,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_name = "POWER5+",
|
||||
.cpu_features = CPU_FTRS_POWER5,
|
||||
.cpu_user_features = COMMON_USER_POWER5_PLUS,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE,
|
||||
.mmu_features = MMU_FTRS_POWER5,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.oprofile_cpu_type = "ppc64/ibm-compat-v1",
|
||||
@ -385,7 +387,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_features = CPU_FTRS_POWER6,
|
||||
.cpu_user_features = COMMON_USER_POWER6 |
|
||||
PPC_FEATURE_POWER6_EXT,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE,
|
||||
.mmu_features = MMU_FTRS_POWER6,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 6,
|
||||
@ -404,7 +406,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_name = "POWER6 (architected)",
|
||||
.cpu_features = CPU_FTRS_POWER6,
|
||||
.cpu_user_features = COMMON_USER_POWER6,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE,
|
||||
.mmu_features = MMU_FTRS_POWER6,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.oprofile_cpu_type = "ppc64/ibm-compat-v1",
|
||||
@ -417,12 +419,13 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_name = "POWER7 (architected)",
|
||||
.cpu_features = CPU_FTRS_POWER7,
|
||||
.cpu_user_features = COMMON_USER_POWER7,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE |
|
||||
MMU_FTR_TLBIE_206,
|
||||
.mmu_features = MMU_FTRS_POWER7,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.oprofile_type = PPC_OPROFILE_POWER4,
|
||||
.oprofile_cpu_type = "ppc64/ibm-compat-v1",
|
||||
.cpu_setup = __setup_cpu_power7,
|
||||
.cpu_restore = __restore_cpu_power7,
|
||||
.platform = "power7",
|
||||
},
|
||||
{ /* Power7 */
|
||||
@ -431,14 +434,15 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_name = "POWER7 (raw)",
|
||||
.cpu_features = CPU_FTRS_POWER7,
|
||||
.cpu_user_features = COMMON_USER_POWER7,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE |
|
||||
MMU_FTR_TLBIE_206,
|
||||
.mmu_features = MMU_FTRS_POWER7,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 6,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.oprofile_cpu_type = "ppc64/power7",
|
||||
.oprofile_type = PPC_OPROFILE_POWER4,
|
||||
.cpu_setup = __setup_cpu_power7,
|
||||
.cpu_restore = __restore_cpu_power7,
|
||||
.platform = "power7",
|
||||
},
|
||||
{ /* Power7+ */
|
||||
@ -447,14 +451,15 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_name = "POWER7+ (raw)",
|
||||
.cpu_features = CPU_FTRS_POWER7,
|
||||
.cpu_user_features = COMMON_USER_POWER7,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE |
|
||||
MMU_FTR_TLBIE_206,
|
||||
.mmu_features = MMU_FTRS_POWER7,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 6,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.oprofile_cpu_type = "ppc64/power7",
|
||||
.oprofile_type = PPC_OPROFILE_POWER4,
|
||||
.cpu_setup = __setup_cpu_power7,
|
||||
.cpu_restore = __restore_cpu_power7,
|
||||
.platform = "power7+",
|
||||
},
|
||||
{ /* Cell Broadband Engine */
|
||||
@ -465,7 +470,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_user_features = COMMON_USER_PPC64 |
|
||||
PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
|
||||
PPC_FEATURE_SMT,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE,
|
||||
.mmu_features = MMU_FTRS_CELL,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 4,
|
||||
@ -480,7 +485,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_name = "PA6T",
|
||||
.cpu_features = CPU_FTRS_PA6T,
|
||||
.cpu_user_features = COMMON_USER_PA6T,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE,
|
||||
.mmu_features = MMU_FTRS_PA6T,
|
||||
.icache_bsize = 64,
|
||||
.dcache_bsize = 64,
|
||||
.num_pmcs = 6,
|
||||
@ -497,7 +502,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.cpu_name = "POWER4 (compatible)",
|
||||
.cpu_features = CPU_FTRS_COMPATIBLE,
|
||||
.cpu_user_features = COMMON_USER_PPC64,
|
||||
.mmu_features = MMU_FTR_HPTE_TABLE,
|
||||
.mmu_features = MMU_FTRS_DEFAULT_HPTE_ARCH_V2,
|
||||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 6,
|
||||
@ -2005,7 +2010,22 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
#endif /* CONFIG_PPC32 */
|
||||
#endif /* CONFIG_E500 */
|
||||
|
||||
#ifdef CONFIG_PPC_BOOK3E_64
|
||||
#ifdef CONFIG_PPC_A2
|
||||
{ /* Standard A2 (>= DD2) + FPU core */
|
||||
.pvr_mask = 0xffff0000,
|
||||
.pvr_value = 0x00480000,
|
||||
.cpu_name = "A2 (>= DD2)",
|
||||
.cpu_features = CPU_FTRS_A2,
|
||||
.cpu_user_features = COMMON_USER_PPC64,
|
||||
.mmu_features = MMU_FTRS_A2,
|
||||
.icache_bsize = 64,
|
||||
.dcache_bsize = 64,
|
||||
.num_pmcs = 0,
|
||||
.cpu_setup = __setup_cpu_a2,
|
||||
.cpu_restore = __restore_cpu_a2,
|
||||
.machine_check = machine_check_generic,
|
||||
.platform = "ppca2",
|
||||
},
|
||||
{ /* This is a default entry to get going, to be replaced by
|
||||
* a real one at some stage
|
||||
*/
|
||||
@ -2026,7 +2046,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.machine_check = machine_check_generic,
|
||||
.platform = "power6",
|
||||
},
|
||||
#endif
|
||||
#endif /* CONFIG_PPC_A2 */
|
||||
};
|
||||
|
||||
static struct cpu_spec the_cpu_spec;
|
||||
|
||||
@ -64,9 +64,9 @@ void crash_ipi_callback(struct pt_regs *regs)
|
||||
return;
|
||||
|
||||
hard_irq_disable();
|
||||
if (!cpu_isset(cpu, cpus_in_crash))
|
||||
if (!cpumask_test_cpu(cpu, &cpus_in_crash))
|
||||
crash_save_cpu(regs, cpu);
|
||||
cpu_set(cpu, cpus_in_crash);
|
||||
cpumask_set_cpu(cpu, &cpus_in_crash);
|
||||
|
||||
/*
|
||||
* Entered via soft-reset - could be the kdump
|
||||
@ -77,8 +77,8 @@ void crash_ipi_callback(struct pt_regs *regs)
|
||||
* Tell the kexec CPU that entered via soft-reset and ready
|
||||
* to go down.
|
||||
*/
|
||||
if (cpu_isset(cpu, cpus_in_sr)) {
|
||||
cpu_clear(cpu, cpus_in_sr);
|
||||
if (cpumask_test_cpu(cpu, &cpus_in_sr)) {
|
||||
cpumask_clear_cpu(cpu, &cpus_in_sr);
|
||||
atomic_inc(&enter_on_soft_reset);
|
||||
}
|
||||
|
||||
@ -87,7 +87,7 @@ void crash_ipi_callback(struct pt_regs *regs)
|
||||
* This barrier is needed to make sure that all CPUs are stopped.
|
||||
* If not, soft-reset will be invoked to bring other CPUs.
|
||||
*/
|
||||
while (!cpu_isset(crashing_cpu, cpus_in_crash))
|
||||
while (!cpumask_test_cpu(crashing_cpu, &cpus_in_crash))
|
||||
cpu_relax();
|
||||
|
||||
if (ppc_md.kexec_cpu_down)
|
||||
@ -109,7 +109,7 @@ static void crash_soft_reset_check(int cpu)
|
||||
{
|
||||
unsigned int ncpus = num_online_cpus() - 1;/* Excluding the panic cpu */
|
||||
|
||||
cpu_clear(cpu, cpus_in_sr);
|
||||
cpumask_clear_cpu(cpu, &cpus_in_sr);
|
||||
while (atomic_read(&enter_on_soft_reset) != ncpus)
|
||||
cpu_relax();
|
||||
}
|
||||
@ -132,7 +132,7 @@ static void crash_kexec_prepare_cpus(int cpu)
|
||||
*/
|
||||
printk(KERN_EMERG "Sending IPI to other cpus...\n");
|
||||
msecs = 10000;
|
||||
while ((cpus_weight(cpus_in_crash) < ncpus) && (--msecs > 0)) {
|
||||
while ((cpumask_weight(&cpus_in_crash) < ncpus) && (--msecs > 0)) {
|
||||
cpu_relax();
|
||||
mdelay(1);
|
||||
}
|
||||
@ -144,52 +144,24 @@ static void crash_kexec_prepare_cpus(int cpu)
|
||||
* user to do soft reset such that we get all.
|
||||
* Soft-reset will be used until better mechanism is implemented.
|
||||
*/
|
||||
if (cpus_weight(cpus_in_crash) < ncpus) {
|
||||
if (cpumask_weight(&cpus_in_crash) < ncpus) {
|
||||
printk(KERN_EMERG "done waiting: %d cpu(s) not responding\n",
|
||||
ncpus - cpus_weight(cpus_in_crash));
|
||||
ncpus - cpumask_weight(&cpus_in_crash));
|
||||
printk(KERN_EMERG "Activate soft-reset to stop other cpu(s)\n");
|
||||
cpus_in_sr = CPU_MASK_NONE;
|
||||
cpumask_clear(&cpus_in_sr);
|
||||
atomic_set(&enter_on_soft_reset, 0);
|
||||
while (cpus_weight(cpus_in_crash) < ncpus)
|
||||
while (cpumask_weight(&cpus_in_crash) < ncpus)
|
||||
cpu_relax();
|
||||
}
|
||||
/*
|
||||
* Make sure all CPUs are entered via soft-reset if the kdump is
|
||||
* invoked using soft-reset.
|
||||
*/
|
||||
if (cpu_isset(cpu, cpus_in_sr))
|
||||
if (cpumask_test_cpu(cpu, &cpus_in_sr))
|
||||
crash_soft_reset_check(cpu);
|
||||
/* Leave the IPI callback set */
|
||||
}
|
||||
|
||||
/* wait for all the CPUs to hit real mode but timeout if they don't come in */
|
||||
#ifdef CONFIG_PPC_STD_MMU_64
|
||||
static void crash_kexec_wait_realmode(int cpu)
|
||||
{
|
||||
unsigned int msecs;
|
||||
int i;
|
||||
|
||||
msecs = 10000;
|
||||
for (i=0; i < NR_CPUS && msecs > 0; i++) {
|
||||
if (i == cpu)
|
||||
continue;
|
||||
|
||||
while (paca[i].kexec_state < KEXEC_STATE_REAL_MODE) {
|
||||
barrier();
|
||||
if (!cpu_possible(i)) {
|
||||
break;
|
||||
}
|
||||
if (!cpu_online(i)) {
|
||||
break;
|
||||
}
|
||||
msecs--;
|
||||
mdelay(1);
|
||||
}
|
||||
}
|
||||
mb();
|
||||
}
|
||||
#endif /* CONFIG_PPC_STD_MMU_64 */
|
||||
|
||||
/*
|
||||
* This function will be called by secondary cpus or by kexec cpu
|
||||
* if soft-reset is activated to stop some CPUs.
|
||||
@ -210,7 +182,7 @@ void crash_kexec_secondary(struct pt_regs *regs)
|
||||
* exited using 'x'(exit and recover) or
|
||||
* kexec_should_crash() failed for all running tasks.
|
||||
*/
|
||||
cpu_clear(cpu, cpus_in_sr);
|
||||
cpumask_clear_cpu(cpu, &cpus_in_sr);
|
||||
local_irq_restore(flags);
|
||||
return;
|
||||
}
|
||||
@ -224,7 +196,7 @@ void crash_kexec_secondary(struct pt_regs *regs)
|
||||
* then start kexec boot.
|
||||
*/
|
||||
crash_soft_reset_check(cpu);
|
||||
cpu_set(crashing_cpu, cpus_in_crash);
|
||||
cpumask_set_cpu(crashing_cpu, &cpus_in_crash);
|
||||
if (ppc_md.kexec_cpu_down)
|
||||
ppc_md.kexec_cpu_down(1, 0);
|
||||
machine_kexec(kexec_crash_image);
|
||||
@ -234,7 +206,6 @@ void crash_kexec_secondary(struct pt_regs *regs)
|
||||
}
|
||||
|
||||
#else /* ! CONFIG_SMP */
|
||||
static inline void crash_kexec_wait_realmode(int cpu) {}
|
||||
|
||||
static void crash_kexec_prepare_cpus(int cpu)
|
||||
{
|
||||
@ -253,10 +224,40 @@ static void crash_kexec_prepare_cpus(int cpu)
|
||||
|
||||
void crash_kexec_secondary(struct pt_regs *regs)
|
||||
{
|
||||
cpus_in_sr = CPU_MASK_NONE;
|
||||
cpumask_clear(&cpus_in_sr);
|
||||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
/* wait for all the CPUs to hit real mode but timeout if they don't come in */
|
||||
#if defined(CONFIG_SMP) && defined(CONFIG_PPC_STD_MMU_64)
|
||||
static void crash_kexec_wait_realmode(int cpu)
|
||||
{
|
||||
unsigned int msecs;
|
||||
int i;
|
||||
|
||||
msecs = 10000;
|
||||
for (i=0; i < nr_cpu_ids && msecs > 0; i++) {
|
||||
if (i == cpu)
|
||||
continue;
|
||||
|
||||
while (paca[i].kexec_state < KEXEC_STATE_REAL_MODE) {
|
||||
barrier();
|
||||
if (!cpu_possible(i)) {
|
||||
break;
|
||||
}
|
||||
if (!cpu_online(i)) {
|
||||
break;
|
||||
}
|
||||
msecs--;
|
||||
mdelay(1);
|
||||
}
|
||||
}
|
||||
mb();
|
||||
}
|
||||
#else
|
||||
static inline void crash_kexec_wait_realmode(int cpu) {}
|
||||
#endif /* CONFIG_SMP && CONFIG_PPC_STD_MMU_64 */
|
||||
|
||||
/*
|
||||
* Register a function to be called on shutdown. Only use this if you
|
||||
* can't reset your device in the second kernel.
|
||||
@ -345,7 +346,7 @@ void default_machine_crash_shutdown(struct pt_regs *regs)
|
||||
crashing_cpu = smp_processor_id();
|
||||
crash_save_cpu(regs, crashing_cpu);
|
||||
crash_kexec_prepare_cpus(crashing_cpu);
|
||||
cpu_set(crashing_cpu, cpus_in_crash);
|
||||
cpumask_set_cpu(crashing_cpu, &cpus_in_crash);
|
||||
crash_kexec_wait_realmode(crashing_cpu);
|
||||
|
||||
machine_kexec_mask_interrupts();
|
||||
|
||||
@ -13,84 +13,35 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/threads.h>
|
||||
#include <linux/percpu.h>
|
||||
#include <linux/hardirq.h>
|
||||
|
||||
#include <asm/dbell.h>
|
||||
#include <asm/irq_regs.h>
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
struct doorbell_cpu_info {
|
||||
unsigned long messages; /* current messages bits */
|
||||
unsigned int tag; /* tag value */
|
||||
};
|
||||
|
||||
static DEFINE_PER_CPU(struct doorbell_cpu_info, doorbell_cpu_info);
|
||||
|
||||
void doorbell_setup_this_cpu(void)
|
||||
{
|
||||
struct doorbell_cpu_info *info = &__get_cpu_var(doorbell_cpu_info);
|
||||
unsigned long tag = mfspr(SPRN_PIR) & 0x3fff;
|
||||
|
||||
info->messages = 0;
|
||||
info->tag = mfspr(SPRN_PIR) & 0x3fff;
|
||||
smp_muxed_ipi_set_data(smp_processor_id(), tag);
|
||||
}
|
||||
|
||||
void doorbell_message_pass(int target, int msg)
|
||||
void doorbell_cause_ipi(int cpu, unsigned long data)
|
||||
{
|
||||
struct doorbell_cpu_info *info;
|
||||
int i;
|
||||
|
||||
if (target < NR_CPUS) {
|
||||
info = &per_cpu(doorbell_cpu_info, target);
|
||||
set_bit(msg, &info->messages);
|
||||
ppc_msgsnd(PPC_DBELL, 0, info->tag);
|
||||
}
|
||||
else if (target == MSG_ALL_BUT_SELF) {
|
||||
for_each_online_cpu(i) {
|
||||
if (i == smp_processor_id())
|
||||
continue;
|
||||
info = &per_cpu(doorbell_cpu_info, i);
|
||||
set_bit(msg, &info->messages);
|
||||
ppc_msgsnd(PPC_DBELL, 0, info->tag);
|
||||
}
|
||||
}
|
||||
else { /* target == MSG_ALL */
|
||||
for_each_online_cpu(i) {
|
||||
info = &per_cpu(doorbell_cpu_info, i);
|
||||
set_bit(msg, &info->messages);
|
||||
}
|
||||
ppc_msgsnd(PPC_DBELL, PPC_DBELL_MSG_BRDCAST, 0);
|
||||
}
|
||||
ppc_msgsnd(PPC_DBELL, 0, data);
|
||||
}
|
||||
|
||||
void doorbell_exception(struct pt_regs *regs)
|
||||
{
|
||||
struct pt_regs *old_regs = set_irq_regs(regs);
|
||||
struct doorbell_cpu_info *info = &__get_cpu_var(doorbell_cpu_info);
|
||||
int msg;
|
||||
|
||||
/* Warning: regs can be NULL when called from irq enable */
|
||||
irq_enter();
|
||||
|
||||
if (!info->messages || (num_online_cpus() < 2))
|
||||
goto out;
|
||||
smp_ipi_demux();
|
||||
|
||||
for (msg = 0; msg < 4; msg++)
|
||||
if (test_and_clear_bit(msg, &info->messages))
|
||||
smp_message_recv(msg);
|
||||
|
||||
out:
|
||||
irq_exit();
|
||||
set_irq_regs(old_regs);
|
||||
}
|
||||
|
||||
void doorbell_check_self(void)
|
||||
{
|
||||
struct doorbell_cpu_info *info = &__get_cpu_var(doorbell_cpu_info);
|
||||
|
||||
if (!info->messages)
|
||||
return;
|
||||
|
||||
ppc_msgsnd(PPC_DBELL, 0, info->tag);
|
||||
}
|
||||
|
||||
#else /* CONFIG_SMP */
|
||||
void doorbell_exception(struct pt_regs *regs)
|
||||
{
|
||||
|
||||
@ -421,6 +421,12 @@ BEGIN_FTR_SECTION
|
||||
std r24,THREAD_VRSAVE(r3)
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
||||
#endif /* CONFIG_ALTIVEC */
|
||||
#ifdef CONFIG_PPC64
|
||||
BEGIN_FTR_SECTION
|
||||
mfspr r25,SPRN_DSCR
|
||||
std r25,THREAD_DSCR(r3)
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
|
||||
#endif
|
||||
and. r0,r0,r22
|
||||
beq+ 1f
|
||||
andc r22,r22,r0
|
||||
@ -462,10 +468,10 @@ BEGIN_FTR_SECTION
|
||||
FTR_SECTION_ELSE_NESTED(95)
|
||||
clrrdi r6,r8,40 /* get its 1T ESID */
|
||||
clrrdi r9,r1,40 /* get current sp 1T ESID */
|
||||
ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_1T_SEGMENT, 95)
|
||||
ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
|
||||
FTR_SECTION_ELSE
|
||||
b 2f
|
||||
ALT_FTR_SECTION_END_IFSET(CPU_FTR_SLB)
|
||||
ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
|
||||
clrldi. r0,r6,2 /* is new ESID c00000000? */
|
||||
cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
|
||||
cror eq,4*cr1+eq,eq
|
||||
@ -479,7 +485,7 @@ BEGIN_FTR_SECTION
|
||||
li r9,MMU_SEGSIZE_1T /* insert B field */
|
||||
oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
|
||||
rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
|
||||
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
|
||||
|
||||
/* Update the last bolted SLB. No write barriers are needed
|
||||
* here, provided we only update the current CPU's SLB shadow
|
||||
@ -491,7 +497,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
|
||||
std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
|
||||
std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
|
||||
|
||||
/* No need to check for CPU_FTR_NO_SLBIE_B here, since when
|
||||
/* No need to check for MMU_FTR_NO_SLBIE_B here, since when
|
||||
* we have 1TB segments, the only CPUs known to have the errata
|
||||
* only support less than 1TB of system memory and we'll never
|
||||
* actually hit this code path.
|
||||
@ -522,6 +528,15 @@ BEGIN_FTR_SECTION
|
||||
mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
||||
#endif /* CONFIG_ALTIVEC */
|
||||
#ifdef CONFIG_PPC64
|
||||
BEGIN_FTR_SECTION
|
||||
ld r0,THREAD_DSCR(r4)
|
||||
cmpd r0,r25
|
||||
beq 1f
|
||||
mtspr SPRN_DSCR,r0
|
||||
1:
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
|
||||
#endif
|
||||
|
||||
/* r3-r13 are destroyed -- Cort */
|
||||
REST_8GPRS(14, r1)
|
||||
@ -838,7 +853,7 @@ _GLOBAL(enter_rtas)
|
||||
|
||||
_STATIC(rtas_return_loc)
|
||||
/* relocation is off at this point */
|
||||
mfspr r4,SPRN_SPRG_PACA /* Get PACA */
|
||||
GET_PACA(r4)
|
||||
clrldi r4,r4,2 /* convert to realmode address */
|
||||
|
||||
bcl 20,31,$+4
|
||||
@ -869,7 +884,7 @@ _STATIC(rtas_restore_regs)
|
||||
REST_8GPRS(14, r1) /* Restore the non-volatiles */
|
||||
REST_10GPRS(22, r1) /* ditto */
|
||||
|
||||
mfspr r13,SPRN_SPRG_PACA
|
||||
GET_PACA(r13)
|
||||
|
||||
ld r4,_CCR(r1)
|
||||
mtcr r4
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
#include <asm/cputable.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/thread_info.h>
|
||||
#include <asm/reg_a2.h>
|
||||
#include <asm/exception-64e.h>
|
||||
#include <asm/bug.h>
|
||||
#include <asm/irqflags.h>
|
||||
@ -252,9 +253,6 @@ exception_marker:
|
||||
.balign 0x1000
|
||||
.globl interrupt_base_book3e
|
||||
interrupt_base_book3e: /* fake trap */
|
||||
/* Note: If real debug exceptions are supported by the HW, the vector
|
||||
* below will have to be patched up to point to an appropriate handler
|
||||
*/
|
||||
EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */
|
||||
EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */
|
||||
EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
|
||||
@ -271,8 +269,13 @@ interrupt_base_book3e: /* fake trap */
|
||||
EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
|
||||
EXCEPTION_STUB(0x1c0, data_tlb_miss)
|
||||
EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
|
||||
EXCEPTION_STUB(0x260, perfmon)
|
||||
EXCEPTION_STUB(0x280, doorbell)
|
||||
EXCEPTION_STUB(0x2a0, doorbell_crit)
|
||||
EXCEPTION_STUB(0x2c0, guest_doorbell)
|
||||
EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
|
||||
EXCEPTION_STUB(0x300, hypercall)
|
||||
EXCEPTION_STUB(0x320, ehpriv)
|
||||
|
||||
.globl interrupt_end_book3e
|
||||
interrupt_end_book3e:
|
||||
@ -454,6 +457,70 @@ interrupt_end_book3e:
|
||||
kernel_dbg_exc:
|
||||
b . /* NYI */
|
||||
|
||||
/* Debug exception as a debug interrupt*/
|
||||
START_EXCEPTION(debug_debug);
|
||||
DBG_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
|
||||
|
||||
/*
|
||||
* If there is a single step or branch-taken exception in an
|
||||
* exception entry sequence, it was probably meant to apply to
|
||||
* the code where the exception occurred (since exception entry
|
||||
* doesn't turn off DE automatically). We simulate the effect
|
||||
* of turning off DE on entry to an exception handler by turning
|
||||
* off DE in the DSRR1 value and clearing the debug status.
|
||||
*/
|
||||
|
||||
mfspr r14,SPRN_DBSR /* check single-step/branch taken */
|
||||
andis. r15,r14,DBSR_IC@h
|
||||
beq+ 1f
|
||||
|
||||
LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
|
||||
LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
|
||||
cmpld cr0,r10,r14
|
||||
cmpld cr1,r10,r15
|
||||
blt+ cr0,1f
|
||||
bge+ cr1,1f
|
||||
|
||||
/* here it looks like we got an inappropriate debug exception. */
|
||||
lis r14,DBSR_IC@h /* clear the IC event */
|
||||
rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
|
||||
mtspr SPRN_DBSR,r14
|
||||
mtspr SPRN_DSRR1,r11
|
||||
lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
|
||||
ld r1,PACA_EXDBG+EX_R1(r13)
|
||||
ld r14,PACA_EXDBG+EX_R14(r13)
|
||||
ld r15,PACA_EXDBG+EX_R15(r13)
|
||||
mtcr r10
|
||||
ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
|
||||
ld r11,PACA_EXDBG+EX_R11(r13)
|
||||
mfspr r13,SPRN_SPRG_DBG_SCRATCH
|
||||
rfdi
|
||||
|
||||
/* Normal debug exception */
|
||||
/* XXX We only handle coming from userspace for now since we can't
|
||||
* quite save properly an interrupted kernel state yet
|
||||
*/
|
||||
1: andi. r14,r11,MSR_PR; /* check for userspace again */
|
||||
beq kernel_dbg_exc; /* if from kernel mode */
|
||||
|
||||
/* Now we mash up things to make it look like we are coming on a
|
||||
* normal exception
|
||||
*/
|
||||
mfspr r15,SPRN_SPRG_DBG_SCRATCH
|
||||
mtspr SPRN_SPRG_GEN_SCRATCH,r15
|
||||
mfspr r14,SPRN_DBSR
|
||||
EXCEPTION_COMMON(0xd00, PACA_EXDBG, INTS_DISABLE_ALL)
|
||||
std r14,_DSISR(r1)
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
mr r4,r14
|
||||
ld r14,PACA_EXDBG+EX_R14(r13)
|
||||
ld r15,PACA_EXDBG+EX_R15(r13)
|
||||
bl .save_nvgprs
|
||||
bl .DebugException
|
||||
b .ret_from_except
|
||||
|
||||
MASKABLE_EXCEPTION(0x260, perfmon, .performance_monitor_exception, ACK_NONE)
|
||||
|
||||
/* Doorbell interrupt */
|
||||
MASKABLE_EXCEPTION(0x2070, doorbell, .doorbell_exception, ACK_NONE)
|
||||
|
||||
@ -468,6 +535,11 @@ kernel_dbg_exc:
|
||||
// b ret_from_crit_except
|
||||
b .
|
||||
|
||||
MASKABLE_EXCEPTION(0x2c0, guest_doorbell, .unknown_exception, ACK_NONE)
|
||||
MASKABLE_EXCEPTION(0x2e0, guest_doorbell_crit, .unknown_exception, ACK_NONE)
|
||||
MASKABLE_EXCEPTION(0x310, hypercall, .unknown_exception, ACK_NONE)
|
||||
MASKABLE_EXCEPTION(0x320, ehpriv, .unknown_exception, ACK_NONE)
|
||||
|
||||
|
||||
/*
|
||||
* An interrupt came in while soft-disabled; clear EE in SRR1,
|
||||
@ -587,7 +659,12 @@ fast_exception_return:
|
||||
BAD_STACK_TRAMPOLINE(0x000)
|
||||
BAD_STACK_TRAMPOLINE(0x100)
|
||||
BAD_STACK_TRAMPOLINE(0x200)
|
||||
BAD_STACK_TRAMPOLINE(0x260)
|
||||
BAD_STACK_TRAMPOLINE(0x2c0)
|
||||
BAD_STACK_TRAMPOLINE(0x2e0)
|
||||
BAD_STACK_TRAMPOLINE(0x300)
|
||||
BAD_STACK_TRAMPOLINE(0x310)
|
||||
BAD_STACK_TRAMPOLINE(0x320)
|
||||
BAD_STACK_TRAMPOLINE(0x400)
|
||||
BAD_STACK_TRAMPOLINE(0x500)
|
||||
BAD_STACK_TRAMPOLINE(0x600)
|
||||
@ -864,8 +941,23 @@ have_hes:
|
||||
* that will have to be made dependent on whether we are running under
|
||||
* a hypervisor I suppose.
|
||||
*/
|
||||
ori r3,r3,MAS0_HES | MAS0_WQ_ALLWAYS
|
||||
mtspr SPRN_MAS0,r3
|
||||
|
||||
/* BEWARE, MAGIC
|
||||
* This code is called as an ordinary function on the boot CPU. But to
|
||||
* avoid duplication, this code is also used in SCOM bringup of
|
||||
* secondary CPUs. We read the code between the initial_tlb_code_start
|
||||
* and initial_tlb_code_end labels one instruction at a time and RAM it
|
||||
* into the new core via SCOM. That doesn't process branches, so there
|
||||
* must be none between those two labels. It also means if this code
|
||||
* ever takes any parameters, the SCOM code must also be updated to
|
||||
* provide them.
|
||||
*/
|
||||
.globl a2_tlbinit_code_start
|
||||
a2_tlbinit_code_start:
|
||||
|
||||
ori r11,r3,MAS0_WQ_ALLWAYS
|
||||
oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
|
||||
mtspr SPRN_MAS0,r11
|
||||
lis r3,(MAS1_VALID | MAS1_IPROT)@h
|
||||
ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
|
||||
mtspr SPRN_MAS1,r3
|
||||
@ -879,18 +971,86 @@ have_hes:
|
||||
/* Write the TLB entry */
|
||||
tlbwe
|
||||
|
||||
.globl a2_tlbinit_after_linear_map
|
||||
a2_tlbinit_after_linear_map:
|
||||
|
||||
/* Now we branch the new virtual address mapped by this entry */
|
||||
LOAD_REG_IMMEDIATE(r3,1f)
|
||||
mtctr r3
|
||||
bctr
|
||||
|
||||
1: /* We are now running at PAGE_OFFSET, clean the TLB of everything
|
||||
* else (XXX we should scan for bolted crap from the firmware too)
|
||||
* else (including IPROTed things left by firmware)
|
||||
* r4 = TLBnCFG
|
||||
* r3 = current address (more or less)
|
||||
*/
|
||||
|
||||
li r5,0
|
||||
mtspr SPRN_MAS6,r5
|
||||
tlbsx 0,r3
|
||||
|
||||
rlwinm r9,r4,0,TLBnCFG_N_ENTRY
|
||||
rlwinm r10,r4,8,0xff
|
||||
addi r10,r10,-1 /* Get inner loop mask */
|
||||
|
||||
li r3,1
|
||||
|
||||
mfspr r5,SPRN_MAS1
|
||||
rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
|
||||
|
||||
mfspr r6,SPRN_MAS2
|
||||
rldicr r6,r6,0,51 /* Extract EPN */
|
||||
|
||||
mfspr r7,SPRN_MAS0
|
||||
rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
|
||||
|
||||
rlwinm r8,r7,16,0xfff /* Extract ESEL */
|
||||
|
||||
2: add r4,r3,r8
|
||||
and r4,r4,r10
|
||||
|
||||
rlwimi r7,r4,16,MAS0_ESEL_MASK
|
||||
|
||||
mtspr SPRN_MAS0,r7
|
||||
mtspr SPRN_MAS1,r5
|
||||
mtspr SPRN_MAS2,r6
|
||||
tlbwe
|
||||
|
||||
addi r3,r3,1
|
||||
and. r4,r3,r10
|
||||
|
||||
bne 3f
|
||||
addis r6,r6,(1<<30)@h
|
||||
3:
|
||||
cmpw r3,r9
|
||||
blt 2b
|
||||
|
||||
.globl a2_tlbinit_after_iprot_flush
|
||||
a2_tlbinit_after_iprot_flush:
|
||||
|
||||
#ifdef CONFIG_PPC_EARLY_DEBUG_WSP
|
||||
/* Now establish early debug mappings if applicable */
|
||||
/* Restore the MAS0 we used for linear mapping load */
|
||||
mtspr SPRN_MAS0,r11
|
||||
|
||||
lis r3,(MAS1_VALID | MAS1_IPROT)@h
|
||||
ori r3,r3,(BOOK3E_PAGESZ_4K << MAS1_TSIZE_SHIFT)
|
||||
mtspr SPRN_MAS1,r3
|
||||
LOAD_REG_IMMEDIATE(r3, WSP_UART_VIRT | MAS2_I | MAS2_G)
|
||||
mtspr SPRN_MAS2,r3
|
||||
LOAD_REG_IMMEDIATE(r3, WSP_UART_PHYS | MAS3_SR | MAS3_SW)
|
||||
mtspr SPRN_MAS7_MAS3,r3
|
||||
/* re-use the MAS8 value from the linear mapping */
|
||||
tlbwe
|
||||
#endif /* CONFIG_PPC_EARLY_DEBUG_WSP */
|
||||
|
||||
PPC_TLBILX(0,0,0)
|
||||
sync
|
||||
isync
|
||||
|
||||
.globl a2_tlbinit_code_end
|
||||
a2_tlbinit_code_end:
|
||||
|
||||
/* We translate LR and return */
|
||||
mflr r3
|
||||
tovirt(r3,r3)
|
||||
@ -1040,3 +1200,33 @@ _GLOBAL(__setup_base_ivors)
|
||||
sync
|
||||
|
||||
blr
|
||||
|
||||
_GLOBAL(setup_perfmon_ivor)
|
||||
SET_IVOR(35, 0x260) /* Performance Monitor */
|
||||
blr
|
||||
|
||||
_GLOBAL(setup_doorbell_ivors)
|
||||
SET_IVOR(36, 0x280) /* Processor Doorbell */
|
||||
SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
|
||||
|
||||
/* Check MMUCFG[LPIDSIZE] to determine if we have category E.HV */
|
||||
mfspr r10,SPRN_MMUCFG
|
||||
rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
|
||||
beqlr
|
||||
|
||||
SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
|
||||
SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
|
||||
blr
|
||||
|
||||
_GLOBAL(setup_ehv_ivors)
|
||||
/*
|
||||
* We may be running as a guest and lack E.HV even on a chip
|
||||
* that normally has it.
|
||||
*/
|
||||
mfspr r10,SPRN_MMUCFG
|
||||
rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
|
||||
beqlr
|
||||
|
||||
SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
|
||||
SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
|
||||
blr
|
||||
|
||||
@ -37,23 +37,51 @@
|
||||
.globl __start_interrupts
|
||||
__start_interrupts:
|
||||
|
||||
STD_EXCEPTION_PSERIES(0x100, system_reset)
|
||||
.globl system_reset_pSeries;
|
||||
system_reset_pSeries:
|
||||
HMT_MEDIUM;
|
||||
DO_KVM 0x100;
|
||||
SET_SCRATCH0(r13)
|
||||
#ifdef CONFIG_PPC_P7_NAP
|
||||
BEGIN_FTR_SECTION
|
||||
/* Running native on arch 2.06 or later, check if we are
|
||||
* waking up from nap. We only handle no state loss and
|
||||
* supervisor state loss. We do -not- handle hypervisor
|
||||
* state loss at this time.
|
||||
*/
|
||||
mfspr r13,SPRN_SRR1
|
||||
rlwinm r13,r13,47-31,30,31
|
||||
cmpwi cr0,r13,1
|
||||
bne 1f
|
||||
b .power7_wakeup_noloss
|
||||
1: cmpwi cr0,r13,2
|
||||
bne 1f
|
||||
b .power7_wakeup_loss
|
||||
/* Total loss of HV state is fatal, we could try to use the
|
||||
* PIR to locate a PACA, then use an emergency stack etc...
|
||||
* but for now, let's just stay stuck here
|
||||
*/
|
||||
1: cmpwi cr0,r13,3
|
||||
beq .
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE_206)
|
||||
#endif /* CONFIG_PPC_P7_NAP */
|
||||
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD)
|
||||
|
||||
. = 0x200
|
||||
_machine_check_pSeries:
|
||||
HMT_MEDIUM
|
||||
DO_KVM 0x200
|
||||
mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */
|
||||
EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
|
||||
SET_SCRATCH0(r13)
|
||||
EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common, EXC_STD)
|
||||
|
||||
. = 0x300
|
||||
.globl data_access_pSeries
|
||||
data_access_pSeries:
|
||||
HMT_MEDIUM
|
||||
DO_KVM 0x300
|
||||
mtspr SPRN_SPRG_SCRATCH0,r13
|
||||
SET_SCRATCH0(r13)
|
||||
BEGIN_FTR_SECTION
|
||||
mfspr r13,SPRN_SPRG_PACA
|
||||
GET_PACA(r13)
|
||||
std r9,PACA_EXSLB+EX_R9(r13)
|
||||
std r10,PACA_EXSLB+EX_R10(r13)
|
||||
mfspr r10,SPRN_DAR
|
||||
@ -67,22 +95,22 @@ BEGIN_FTR_SECTION
|
||||
std r11,PACA_EXGEN+EX_R11(r13)
|
||||
ld r11,PACA_EXSLB+EX_R9(r13)
|
||||
std r12,PACA_EXGEN+EX_R12(r13)
|
||||
mfspr r12,SPRN_SPRG_SCRATCH0
|
||||
GET_SCRATCH0(r12)
|
||||
std r10,PACA_EXGEN+EX_R10(r13)
|
||||
std r11,PACA_EXGEN+EX_R9(r13)
|
||||
std r12,PACA_EXGEN+EX_R13(r13)
|
||||
EXCEPTION_PROLOG_PSERIES_1(data_access_common)
|
||||
EXCEPTION_PROLOG_PSERIES_1(data_access_common, EXC_STD)
|
||||
FTR_SECTION_ELSE
|
||||
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
|
||||
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
|
||||
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD)
|
||||
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_SLB)
|
||||
|
||||
. = 0x380
|
||||
.globl data_access_slb_pSeries
|
||||
data_access_slb_pSeries:
|
||||
HMT_MEDIUM
|
||||
DO_KVM 0x380
|
||||
mtspr SPRN_SPRG_SCRATCH0,r13
|
||||
mfspr r13,SPRN_SPRG_PACA /* get paca address into r13 */
|
||||
SET_SCRATCH0(r13)
|
||||
GET_PACA(r13)
|
||||
std r3,PACA_EXSLB+EX_R3(r13)
|
||||
mfspr r3,SPRN_DAR
|
||||
std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
|
||||
@ -95,7 +123,7 @@ data_access_slb_pSeries:
|
||||
std r10,PACA_EXSLB+EX_R10(r13)
|
||||
std r11,PACA_EXSLB+EX_R11(r13)
|
||||
std r12,PACA_EXSLB+EX_R12(r13)
|
||||
mfspr r10,SPRN_SPRG_SCRATCH0
|
||||
GET_SCRATCH0(r10)
|
||||
std r10,PACA_EXSLB+EX_R13(r13)
|
||||
mfspr r12,SPRN_SRR1 /* and SRR1 */
|
||||
#ifndef CONFIG_RELOCATABLE
|
||||
@ -113,15 +141,15 @@ data_access_slb_pSeries:
|
||||
bctr
|
||||
#endif
|
||||
|
||||
STD_EXCEPTION_PSERIES(0x400, instruction_access)
|
||||
STD_EXCEPTION_PSERIES(0x400, 0x400, instruction_access)
|
||||
|
||||
. = 0x480
|
||||
.globl instruction_access_slb_pSeries
|
||||
instruction_access_slb_pSeries:
|
||||
HMT_MEDIUM
|
||||
DO_KVM 0x480
|
||||
mtspr SPRN_SPRG_SCRATCH0,r13
|
||||
mfspr r13,SPRN_SPRG_PACA /* get paca address into r13 */
|
||||
SET_SCRATCH0(r13)
|
||||
GET_PACA(r13)
|
||||
std r3,PACA_EXSLB+EX_R3(r13)
|
||||
mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
|
||||
std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
|
||||
@ -134,7 +162,7 @@ instruction_access_slb_pSeries:
|
||||
std r10,PACA_EXSLB+EX_R10(r13)
|
||||
std r11,PACA_EXSLB+EX_R11(r13)
|
||||
std r12,PACA_EXSLB+EX_R12(r13)
|
||||
mfspr r10,SPRN_SPRG_SCRATCH0
|
||||
GET_SCRATCH0(r10)
|
||||
std r10,PACA_EXSLB+EX_R13(r13)
|
||||
mfspr r12,SPRN_SRR1 /* and SRR1 */
|
||||
#ifndef CONFIG_RELOCATABLE
|
||||
@ -147,13 +175,29 @@ instruction_access_slb_pSeries:
|
||||
bctr
|
||||
#endif
|
||||
|
||||
MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt)
|
||||
STD_EXCEPTION_PSERIES(0x600, alignment)
|
||||
STD_EXCEPTION_PSERIES(0x700, program_check)
|
||||
STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
|
||||
MASKABLE_EXCEPTION_PSERIES(0x900, decrementer)
|
||||
STD_EXCEPTION_PSERIES(0xa00, trap_0a)
|
||||
STD_EXCEPTION_PSERIES(0xb00, trap_0b)
|
||||
/* We open code these as we can't have a ". = x" (even with
|
||||
* x = "." within a feature section
|
||||
*/
|
||||
. = 0x500;
|
||||
.globl hardware_interrupt_pSeries;
|
||||
.globl hardware_interrupt_hv;
|
||||
hardware_interrupt_pSeries:
|
||||
hardware_interrupt_hv:
|
||||
BEGIN_FTR_SECTION
|
||||
_MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt, EXC_STD)
|
||||
FTR_SECTION_ELSE
|
||||
_MASKABLE_EXCEPTION_PSERIES(0x502, hardware_interrupt, EXC_HV)
|
||||
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_HVMODE_206)
|
||||
|
||||
STD_EXCEPTION_PSERIES(0x600, 0x600, alignment)
|
||||
STD_EXCEPTION_PSERIES(0x700, 0x700, program_check)
|
||||
STD_EXCEPTION_PSERIES(0x800, 0x800, fp_unavailable)
|
||||
|
||||
MASKABLE_EXCEPTION_PSERIES(0x900, 0x900, decrementer)
|
||||
MASKABLE_EXCEPTION_HV(0x980, 0x980, decrementer)
|
||||
|
||||
STD_EXCEPTION_PSERIES(0xa00, 0xa00, trap_0a)
|
||||
STD_EXCEPTION_PSERIES(0xb00, 0xb00, trap_0b)
|
||||
|
||||
. = 0xc00
|
||||
.globl system_call_pSeries
|
||||
@ -165,13 +209,13 @@ BEGIN_FTR_SECTION
|
||||
beq- 1f
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
|
||||
mr r9,r13
|
||||
mfspr r13,SPRN_SPRG_PACA
|
||||
GET_PACA(r13)
|
||||
mfspr r11,SPRN_SRR0
|
||||
ld r12,PACAKBASE(r13)
|
||||
ld r10,PACAKMSR(r13)
|
||||
LOAD_HANDLER(r12, system_call_entry)
|
||||
mtspr SPRN_SRR0,r12
|
||||
mfspr r12,SPRN_SRR1
|
||||
ld r10,PACAKBASE(r13)
|
||||
LOAD_HANDLER(r10, system_call_entry)
|
||||
mtspr SPRN_SRR0,r10
|
||||
ld r10,PACAKMSR(r13)
|
||||
mtspr SPRN_SRR1,r10
|
||||
rfid
|
||||
b . /* prevent speculative execution */
|
||||
@ -183,8 +227,21 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
|
||||
rfid /* return to userspace */
|
||||
b .
|
||||
|
||||
STD_EXCEPTION_PSERIES(0xd00, single_step)
|
||||
STD_EXCEPTION_PSERIES(0xe00, trap_0e)
|
||||
STD_EXCEPTION_PSERIES(0xd00, 0xd00, single_step)
|
||||
|
||||
/* At 0xe??? we have a bunch of hypervisor exceptions, we branch
|
||||
* out of line to handle them
|
||||
*/
|
||||
. = 0xe00
|
||||
b h_data_storage_hv
|
||||
. = 0xe20
|
||||
b h_instr_storage_hv
|
||||
. = 0xe40
|
||||
b emulation_assist_hv
|
||||
. = 0xe50
|
||||
b hmi_exception_hv
|
||||
. = 0xe60
|
||||
b hmi_exception_hv
|
||||
|
||||
/* We need to deal with the Altivec unavailable exception
|
||||
* here which is at 0xf20, thus in the middle of the
|
||||
@ -193,39 +250,42 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
|
||||
*/
|
||||
performance_monitor_pSeries_1:
|
||||
. = 0xf00
|
||||
DO_KVM 0xf00
|
||||
b performance_monitor_pSeries
|
||||
|
||||
altivec_unavailable_pSeries_1:
|
||||
. = 0xf20
|
||||
DO_KVM 0xf20
|
||||
b altivec_unavailable_pSeries
|
||||
|
||||
vsx_unavailable_pSeries_1:
|
||||
. = 0xf40
|
||||
DO_KVM 0xf40
|
||||
b vsx_unavailable_pSeries
|
||||
|
||||
#ifdef CONFIG_CBE_RAS
|
||||
HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
|
||||
STD_EXCEPTION_HV(0x1200, 0x1202, cbe_system_error)
|
||||
#endif /* CONFIG_CBE_RAS */
|
||||
STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
|
||||
STD_EXCEPTION_PSERIES(0x1300, 0x1300, instruction_breakpoint)
|
||||
#ifdef CONFIG_CBE_RAS
|
||||
HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
|
||||
STD_EXCEPTION_HV(0x1600, 0x1602, cbe_maintenance)
|
||||
#endif /* CONFIG_CBE_RAS */
|
||||
STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
|
||||
STD_EXCEPTION_PSERIES(0x1700, 0x1700, altivec_assist)
|
||||
#ifdef CONFIG_CBE_RAS
|
||||
HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
|
||||
STD_EXCEPTION_HV(0x1800, 0x1802, cbe_thermal)
|
||||
#endif /* CONFIG_CBE_RAS */
|
||||
|
||||
. = 0x3000
|
||||
|
||||
/*** pSeries interrupt support ***/
|
||||
/*** Out of line interrupts support ***/
|
||||
|
||||
/* moved from 0xe00 */
|
||||
STD_EXCEPTION_HV(., 0xe00, h_data_storage)
|
||||
STD_EXCEPTION_HV(., 0xe20, h_instr_storage)
|
||||
STD_EXCEPTION_HV(., 0xe40, emulation_assist)
|
||||
STD_EXCEPTION_HV(., 0xe60, hmi_exception) /* need to flush cache ? */
|
||||
|
||||
/* moved from 0xf00 */
|
||||
STD_EXCEPTION_PSERIES(., performance_monitor)
|
||||
STD_EXCEPTION_PSERIES(., altivec_unavailable)
|
||||
STD_EXCEPTION_PSERIES(., vsx_unavailable)
|
||||
STD_EXCEPTION_PSERIES(., 0xf00, performance_monitor)
|
||||
STD_EXCEPTION_PSERIES(., 0xf20, altivec_unavailable)
|
||||
STD_EXCEPTION_PSERIES(., 0xf40, vsx_unavailable)
|
||||
|
||||
/*
|
||||
* An interrupt came in while soft-disabled; clear EE in SRR1,
|
||||
@ -240,17 +300,30 @@ masked_interrupt:
|
||||
rotldi r10,r10,16
|
||||
mtspr SPRN_SRR1,r10
|
||||
ld r10,PACA_EXGEN+EX_R10(r13)
|
||||
mfspr r13,SPRN_SPRG_SCRATCH0
|
||||
GET_SCRATCH0(r13)
|
||||
rfid
|
||||
b .
|
||||
|
||||
masked_Hinterrupt:
|
||||
stb r10,PACAHARDIRQEN(r13)
|
||||
mtcrf 0x80,r9
|
||||
ld r9,PACA_EXGEN+EX_R9(r13)
|
||||
mfspr r10,SPRN_HSRR1
|
||||
rldicl r10,r10,48,1 /* clear MSR_EE */
|
||||
rotldi r10,r10,16
|
||||
mtspr SPRN_HSRR1,r10
|
||||
ld r10,PACA_EXGEN+EX_R10(r13)
|
||||
GET_SCRATCH0(r13)
|
||||
hrfid
|
||||
b .
|
||||
|
||||
.align 7
|
||||
do_stab_bolted_pSeries:
|
||||
std r11,PACA_EXSLB+EX_R11(r13)
|
||||
std r12,PACA_EXSLB+EX_R12(r13)
|
||||
mfspr r10,SPRN_SPRG_SCRATCH0
|
||||
GET_SCRATCH0(r10)
|
||||
std r10,PACA_EXSLB+EX_R13(r13)
|
||||
EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted)
|
||||
EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted, EXC_STD)
|
||||
|
||||
#ifdef CONFIG_PPC_PSERIES
|
||||
/*
|
||||
@ -260,15 +333,15 @@ do_stab_bolted_pSeries:
|
||||
.align 7
|
||||
system_reset_fwnmi:
|
||||
HMT_MEDIUM
|
||||
mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */
|
||||
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
|
||||
SET_SCRATCH0(r13) /* save r13 */
|
||||
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD)
|
||||
|
||||
.globl machine_check_fwnmi
|
||||
.align 7
|
||||
machine_check_fwnmi:
|
||||
HMT_MEDIUM
|
||||
mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */
|
||||
EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
|
||||
SET_SCRATCH0(r13) /* save r13 */
|
||||
EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common, EXC_STD)
|
||||
|
||||
#endif /* CONFIG_PPC_PSERIES */
|
||||
|
||||
@ -282,7 +355,7 @@ slb_miss_user_pseries:
|
||||
std r10,PACA_EXGEN+EX_R10(r13)
|
||||
std r11,PACA_EXGEN+EX_R11(r13)
|
||||
std r12,PACA_EXGEN+EX_R12(r13)
|
||||
mfspr r10,SPRG_SCRATCH0
|
||||
GET_SCRATCH0(r10)
|
||||
ld r11,PACA_EXSLB+EX_R9(r13)
|
||||
ld r12,PACA_EXSLB+EX_R3(r13)
|
||||
std r10,PACA_EXGEN+EX_R13(r13)
|
||||
@ -342,6 +415,8 @@ machine_check_common:
|
||||
STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
|
||||
STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
|
||||
STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
|
||||
STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception)
|
||||
STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception)
|
||||
STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
|
||||
STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
|
||||
#ifdef CONFIG_ALTIVEC
|
||||
@ -386,9 +461,24 @@ bad_stack:
|
||||
std r12,_XER(r1)
|
||||
SAVE_GPR(0,r1)
|
||||
SAVE_GPR(2,r1)
|
||||
SAVE_4GPRS(3,r1)
|
||||
SAVE_2GPRS(7,r1)
|
||||
SAVE_10GPRS(12,r1)
|
||||
ld r10,EX_R3(r3)
|
||||
std r10,GPR3(r1)
|
||||
SAVE_GPR(4,r1)
|
||||
SAVE_4GPRS(5,r1)
|
||||
ld r9,EX_R9(r3)
|
||||
ld r10,EX_R10(r3)
|
||||
SAVE_2GPRS(9,r1)
|
||||
ld r9,EX_R11(r3)
|
||||
ld r10,EX_R12(r3)
|
||||
ld r11,EX_R13(r3)
|
||||
std r9,GPR11(r1)
|
||||
std r10,GPR12(r1)
|
||||
std r11,GPR13(r1)
|
||||
BEGIN_FTR_SECTION
|
||||
ld r10,EX_CFAR(r3)
|
||||
std r10,ORIG_GPR3(r1)
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
|
||||
SAVE_8GPRS(14,r1)
|
||||
SAVE_10GPRS(22,r1)
|
||||
lhz r12,PACA_TRAP_SAVE(r13)
|
||||
std r12,_TRAP(r1)
|
||||
@ -397,6 +487,9 @@ bad_stack:
|
||||
li r12,0
|
||||
std r12,0(r11)
|
||||
ld r2,PACATOC(r13)
|
||||
ld r11,exception_marker@toc(r2)
|
||||
std r12,RESULT(r1)
|
||||
std r11,STACK_FRAME_OVERHEAD-16(r1)
|
||||
1: addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
bl .kernel_bad_stack
|
||||
b 1b
|
||||
@ -419,6 +512,19 @@ data_access_common:
|
||||
li r5,0x300
|
||||
b .do_hash_page /* Try to handle as hpte fault */
|
||||
|
||||
.align 7
|
||||
.globl h_data_storage_common
|
||||
h_data_storage_common:
|
||||
mfspr r10,SPRN_HDAR
|
||||
std r10,PACA_EXGEN+EX_DAR(r13)
|
||||
mfspr r10,SPRN_HDSISR
|
||||
stw r10,PACA_EXGEN+EX_DSISR(r13)
|
||||
EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
|
||||
bl .save_nvgprs
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
bl .unknown_exception
|
||||
b .ret_from_except
|
||||
|
||||
.align 7
|
||||
.globl instruction_access_common
|
||||
instruction_access_common:
|
||||
@ -428,6 +534,8 @@ instruction_access_common:
|
||||
li r5,0x400
|
||||
b .do_hash_page /* Try to handle as hpte fault */
|
||||
|
||||
STD_EXCEPTION_COMMON(0xe20, h_instr_storage, .unknown_exception)
|
||||
|
||||
/*
|
||||
* Here is the common SLB miss user that is used when going to virtual
|
||||
* mode for SLB misses, that is currently not used
|
||||
@ -750,7 +858,7 @@ _STATIC(do_hash_page)
|
||||
BEGIN_FTR_SECTION
|
||||
andis. r0,r4,0x0020 /* Is it a segment table fault? */
|
||||
bne- do_ste_alloc /* If so handle it */
|
||||
END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
|
||||
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
|
||||
|
||||
clrrdi r11,r1,THREAD_SHIFT
|
||||
lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
|
||||
|
||||
@ -805,19 +805,6 @@ _ENTRY(copy_and_flush)
|
||||
blr
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#ifdef CONFIG_GEMINI
|
||||
.globl __secondary_start_gemini
|
||||
__secondary_start_gemini:
|
||||
mfspr r4,SPRN_HID0
|
||||
ori r4,r4,HID0_ICFI
|
||||
li r3,0
|
||||
ori r3,r3,HID0_ICE
|
||||
andc r4,r4,r3
|
||||
mtspr SPRN_HID0,r4
|
||||
sync
|
||||
b __secondary_start
|
||||
#endif /* CONFIG_GEMINI */
|
||||
|
||||
.globl __secondary_start_mpc86xx
|
||||
__secondary_start_mpc86xx:
|
||||
mfspr r3, SPRN_PIR
|
||||
@ -890,15 +877,6 @@ __secondary_start:
|
||||
mtspr SPRN_SRR1,r4
|
||||
SYNC
|
||||
RFI
|
||||
|
||||
_GLOBAL(start_secondary_resume)
|
||||
/* Reset stack */
|
||||
rlwinm r1,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
|
||||
addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
|
||||
li r3,0
|
||||
std r3,0(r1) /* Zero the stack frame pointer */
|
||||
bl start_secondary
|
||||
b .
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
#ifdef CONFIG_KVM_BOOK3S_HANDLER
|
||||
|
||||
@ -147,6 +147,8 @@ __secondary_hold:
|
||||
mtctr r4
|
||||
mr r3,r24
|
||||
li r4,0
|
||||
/* Make sure that patched code is visible */
|
||||
isync
|
||||
bctr
|
||||
#else
|
||||
BUG_OPCODE
|
||||
@ -216,19 +218,25 @@ generic_secondary_common_init:
|
||||
*/
|
||||
LOAD_REG_ADDR(r13, paca) /* Load paca pointer */
|
||||
ld r13,0(r13) /* Get base vaddr of paca array */
|
||||
#ifndef CONFIG_SMP
|
||||
addi r13,r13,PACA_SIZE /* know r13 if used accidentally */
|
||||
b .kexec_wait /* wait for next kernel if !SMP */
|
||||
#else
|
||||
LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
|
||||
lwz r7,0(r7) /* also the max paca allocated */
|
||||
li r5,0 /* logical cpu id */
|
||||
1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
|
||||
cmpw r6,r24 /* Compare to our id */
|
||||
beq 2f
|
||||
addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
|
||||
addi r5,r5,1
|
||||
cmpwi r5,NR_CPUS
|
||||
cmpw r5,r7 /* Check if more pacas exist */
|
||||
blt 1b
|
||||
|
||||
mr r3,r24 /* not found, copy phys to r3 */
|
||||
b .kexec_wait /* next kernel might do better */
|
||||
|
||||
2: mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG */
|
||||
2: SET_PACA(r13)
|
||||
#ifdef CONFIG_PPC_BOOK3E
|
||||
addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
|
||||
mtspr SPRN_SPRG_TLB_EXFRAME,r12
|
||||
@ -236,34 +244,39 @@ generic_secondary_common_init:
|
||||
|
||||
/* From now on, r24 is expected to be logical cpuid */
|
||||
mr r24,r5
|
||||
3: HMT_LOW
|
||||
lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
|
||||
/* start. */
|
||||
|
||||
#ifndef CONFIG_SMP
|
||||
b 3b /* Never go on non-SMP */
|
||||
#else
|
||||
cmpwi 0,r23,0
|
||||
beq 3b /* Loop until told to go */
|
||||
|
||||
sync /* order paca.run and cur_cpu_spec */
|
||||
|
||||
/* See if we need to call a cpu state restore handler */
|
||||
LOAD_REG_ADDR(r23, cur_cpu_spec)
|
||||
ld r23,0(r23)
|
||||
ld r23,CPU_SPEC_RESTORE(r23)
|
||||
cmpdi 0,r23,0
|
||||
beq 4f
|
||||
beq 3f
|
||||
ld r23,0(r23)
|
||||
mtctr r23
|
||||
bctrl
|
||||
|
||||
4: /* Create a temp kernel stack for use before relocation is on. */
|
||||
3: LOAD_REG_ADDR(r3, boot_cpu_count) /* Decrement boot_cpu_count */
|
||||
lwarx r4,0,r3
|
||||
subi r4,r4,1
|
||||
stwcx. r4,0,r3
|
||||
bne 3b
|
||||
isync
|
||||
|
||||
4: HMT_LOW
|
||||
lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
|
||||
/* start. */
|
||||
cmpwi 0,r23,0
|
||||
beq 4b /* Loop until told to go */
|
||||
|
||||
sync /* order paca.run and cur_cpu_spec */
|
||||
isync /* In case code patching happened */
|
||||
|
||||
/* Create a temp kernel stack for use before relocation is on. */
|
||||
ld r1,PACAEMERGSP(r13)
|
||||
subi r1,r1,STACK_FRAME_OVERHEAD
|
||||
|
||||
b __secondary_start
|
||||
#endif
|
||||
#endif /* SMP */
|
||||
|
||||
/*
|
||||
* Turn the MMU off.
|
||||
@ -534,7 +547,7 @@ _GLOBAL(pmac_secondary_start)
|
||||
ld r4,0(r4) /* Get base vaddr of paca array */
|
||||
mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
|
||||
add r13,r13,r4 /* for this processor. */
|
||||
mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG*/
|
||||
SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
|
||||
|
||||
/* Mark interrupts soft and hard disabled (they might be enabled
|
||||
* in the PACA when doing hotplug)
|
||||
@ -645,7 +658,7 @@ _GLOBAL(enable_64b_mode)
|
||||
oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
|
||||
mtmsr r11
|
||||
#else /* CONFIG_PPC_BOOK3E */
|
||||
li r12,(MSR_SF | MSR_ISF)@highest
|
||||
li r12,(MSR_64BIT | MSR_ISF)@highest
|
||||
sldi r12,r12,48
|
||||
or r11,r11,r12
|
||||
mtmsrd r11
|
||||
|
||||
97
arch/powerpc/kernel/idle_power7.S
Normal file
97
arch/powerpc/kernel/idle_power7.S
Normal file
@ -0,0 +1,97 @@
|
||||
/*
|
||||
* This file contains the power_save function for 970-family CPUs.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/threads.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/cputable.h>
|
||||
#include <asm/thread_info.h>
|
||||
#include <asm/ppc_asm.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/ppc-opcode.h>
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
.text
|
||||
|
||||
_GLOBAL(power7_idle)
|
||||
/* Now check if user or arch enabled NAP mode */
|
||||
LOAD_REG_ADDRBASE(r3,powersave_nap)
|
||||
lwz r4,ADDROFF(powersave_nap)(r3)
|
||||
cmpwi 0,r4,0
|
||||
beqlr
|
||||
|
||||
/* NAP is a state loss, we create a regs frame on the
|
||||
* stack, fill it up with the state we care about and
|
||||
* stick a pointer to it in PACAR1. We really only
|
||||
* need to save PC, some CR bits and the NV GPRs,
|
||||
* but for now an interrupt frame will do.
|
||||
*/
|
||||
mflr r0
|
||||
std r0,16(r1)
|
||||
stdu r1,-INT_FRAME_SIZE(r1)
|
||||
std r0,_LINK(r1)
|
||||
std r0,_NIP(r1)
|
||||
|
||||
#ifndef CONFIG_SMP
|
||||
/* Make sure FPU, VSX etc... are flushed as we may lose
|
||||
* state when going to nap mode
|
||||
*/
|
||||
bl .discard_lazy_cpu_state
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
/* Hard disable interrupts */
|
||||
mfmsr r9
|
||||
rldicl r9,r9,48,1
|
||||
rotldi r9,r9,16
|
||||
mtmsrd r9,1 /* hard-disable interrupts */
|
||||
li r0,0
|
||||
stb r0,PACASOFTIRQEN(r13) /* we'll hard-enable shortly */
|
||||
stb r0,PACAHARDIRQEN(r13)
|
||||
|
||||
/* Continue saving state */
|
||||
SAVE_GPR(2, r1)
|
||||
SAVE_NVGPRS(r1)
|
||||
mfcr r3
|
||||
std r3,_CCR(r1)
|
||||
std r9,_MSR(r1)
|
||||
std r1,PACAR1(r13)
|
||||
|
||||
/* Magic NAP mode enter sequence */
|
||||
std r0,0(r1)
|
||||
ptesync
|
||||
ld r0,0(r1)
|
||||
1: cmp cr0,r0,r0
|
||||
bne 1b
|
||||
PPC_NAP
|
||||
b .
|
||||
|
||||
_GLOBAL(power7_wakeup_loss)
|
||||
GET_PACA(r13)
|
||||
ld r1,PACAR1(r13)
|
||||
REST_NVGPRS(r1)
|
||||
REST_GPR(2, r1)
|
||||
ld r3,_CCR(r1)
|
||||
ld r4,_MSR(r1)
|
||||
ld r5,_NIP(r1)
|
||||
addi r1,r1,INT_FRAME_SIZE
|
||||
mtcr r3
|
||||
mtspr SPRN_SRR1,r4
|
||||
mtspr SPRN_SRR0,r5
|
||||
rfid
|
||||
|
||||
_GLOBAL(power7_wakeup_noloss)
|
||||
GET_PACA(r13)
|
||||
ld r1,PACAR1(r13)
|
||||
ld r4,_MSR(r1)
|
||||
ld r5,_NIP(r1)
|
||||
addi r1,r1,INT_FRAME_SIZE
|
||||
mtspr SPRN_SRR1,r4
|
||||
mtspr SPRN_SRR0,r5
|
||||
rfid
|
||||
@ -17,8 +17,7 @@
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/ppc-pci.h>
|
||||
|
||||
#include "io-workarounds.h"
|
||||
#include <asm/io-workarounds.h>
|
||||
|
||||
#define IOWA_MAX_BUS 8
|
||||
|
||||
@ -145,7 +144,19 @@ static void __iomem *iowa_ioremap(phys_addr_t addr, unsigned long size,
|
||||
return res;
|
||||
}
|
||||
|
||||
/* Regist new bus to support workaround */
|
||||
/* Enable IO workaround */
|
||||
static void __devinit io_workaround_init(void)
|
||||
{
|
||||
static int io_workaround_inited;
|
||||
|
||||
if (io_workaround_inited)
|
||||
return;
|
||||
ppc_pci_io = iowa_pci_io;
|
||||
ppc_md.ioremap = iowa_ioremap;
|
||||
io_workaround_inited = 1;
|
||||
}
|
||||
|
||||
/* Register new bus to support workaround */
|
||||
void __devinit iowa_register_bus(struct pci_controller *phb,
|
||||
struct ppc_pci_io *ops,
|
||||
int (*initfunc)(struct iowa_bus *, void *), void *data)
|
||||
@ -153,6 +164,8 @@ void __devinit iowa_register_bus(struct pci_controller *phb,
|
||||
struct iowa_bus *bus;
|
||||
struct device_node *np = phb->dn;
|
||||
|
||||
io_workaround_init();
|
||||
|
||||
if (iowa_bus_count >= IOWA_MAX_BUS) {
|
||||
pr_err("IOWA:Too many pci bridges, "
|
||||
"workarounds disabled for %s\n", np->full_name);
|
||||
@ -162,6 +175,7 @@ void __devinit iowa_register_bus(struct pci_controller *phb,
|
||||
bus = &iowa_busses[iowa_bus_count];
|
||||
bus->phb = phb;
|
||||
bus->ops = ops;
|
||||
bus->private = data;
|
||||
|
||||
if (initfunc)
|
||||
if ((*initfunc)(bus, data))
|
||||
@ -172,14 +186,3 @@ void __devinit iowa_register_bus(struct pci_controller *phb,
|
||||
pr_debug("IOWA:[%d]Add bus, %s.\n", iowa_bus_count-1, np->full_name);
|
||||
}
|
||||
|
||||
/* enable IO workaround */
|
||||
void __devinit io_workaround_init(void)
|
||||
{
|
||||
static int io_workaround_inited;
|
||||
|
||||
if (io_workaround_inited)
|
||||
return;
|
||||
ppc_pci_io = iowa_pci_io;
|
||||
ppc_md.ioremap = iowa_ioremap;
|
||||
io_workaround_inited = 1;
|
||||
}
|
||||
@ -66,7 +66,6 @@
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/dbell.h>
|
||||
#include <asm/smp.h>
|
||||
|
||||
#ifdef CONFIG_PPC64
|
||||
@ -160,7 +159,8 @@ notrace void arch_local_irq_restore(unsigned long en)
|
||||
|
||||
#if defined(CONFIG_BOOKE) && defined(CONFIG_SMP)
|
||||
/* Check for pending doorbell interrupts and resend to ourself */
|
||||
doorbell_check_self();
|
||||
if (cpu_has_feature(CPU_FTR_DBELL))
|
||||
smp_muxed_ipi_resend();
|
||||
#endif
|
||||
|
||||
/*
|
||||
@ -397,24 +397,28 @@ struct thread_info *mcheckirq_ctx[NR_CPUS] __read_mostly;
|
||||
void exc_lvl_ctx_init(void)
|
||||
{
|
||||
struct thread_info *tp;
|
||||
int i, hw_cpu;
|
||||
int i, cpu_nr;
|
||||
|
||||
for_each_possible_cpu(i) {
|
||||
hw_cpu = get_hard_smp_processor_id(i);
|
||||
memset((void *)critirq_ctx[hw_cpu], 0, THREAD_SIZE);
|
||||
tp = critirq_ctx[hw_cpu];
|
||||
tp->cpu = i;
|
||||
#ifdef CONFIG_PPC64
|
||||
cpu_nr = i;
|
||||
#else
|
||||
cpu_nr = get_hard_smp_processor_id(i);
|
||||
#endif
|
||||
memset((void *)critirq_ctx[cpu_nr], 0, THREAD_SIZE);
|
||||
tp = critirq_ctx[cpu_nr];
|
||||
tp->cpu = cpu_nr;
|
||||
tp->preempt_count = 0;
|
||||
|
||||
#ifdef CONFIG_BOOKE
|
||||
memset((void *)dbgirq_ctx[hw_cpu], 0, THREAD_SIZE);
|
||||
tp = dbgirq_ctx[hw_cpu];
|
||||
tp->cpu = i;
|
||||
memset((void *)dbgirq_ctx[cpu_nr], 0, THREAD_SIZE);
|
||||
tp = dbgirq_ctx[cpu_nr];
|
||||
tp->cpu = cpu_nr;
|
||||
tp->preempt_count = 0;
|
||||
|
||||
memset((void *)mcheckirq_ctx[hw_cpu], 0, THREAD_SIZE);
|
||||
tp = mcheckirq_ctx[hw_cpu];
|
||||
tp->cpu = i;
|
||||
memset((void *)mcheckirq_ctx[cpu_nr], 0, THREAD_SIZE);
|
||||
tp = mcheckirq_ctx[cpu_nr];
|
||||
tp->cpu = cpu_nr;
|
||||
tp->preempt_count = HARDIRQ_OFFSET;
|
||||
#endif
|
||||
}
|
||||
@ -477,20 +481,41 @@ void do_softirq(void)
|
||||
* IRQ controller and virtual interrupts
|
||||
*/
|
||||
|
||||
/* The main irq map itself is an array of NR_IRQ entries containing the
|
||||
* associate host and irq number. An entry with a host of NULL is free.
|
||||
* An entry can be allocated if it's free, the allocator always then sets
|
||||
* hwirq first to the host's invalid irq number and then fills ops.
|
||||
*/
|
||||
struct irq_map_entry {
|
||||
irq_hw_number_t hwirq;
|
||||
struct irq_host *host;
|
||||
};
|
||||
|
||||
static LIST_HEAD(irq_hosts);
|
||||
static DEFINE_RAW_SPINLOCK(irq_big_lock);
|
||||
static unsigned int revmap_trees_allocated;
|
||||
static DEFINE_MUTEX(revmap_trees_mutex);
|
||||
struct irq_map_entry irq_map[NR_IRQS];
|
||||
static struct irq_map_entry irq_map[NR_IRQS];
|
||||
static unsigned int irq_virq_count = NR_IRQS;
|
||||
static struct irq_host *irq_default_host;
|
||||
|
||||
irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
|
||||
{
|
||||
return irq_map[d->irq].hwirq;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(irqd_to_hwirq);
|
||||
|
||||
irq_hw_number_t virq_to_hw(unsigned int virq)
|
||||
{
|
||||
return irq_map[virq].hwirq;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(virq_to_hw);
|
||||
|
||||
bool virq_is_host(unsigned int virq, struct irq_host *host)
|
||||
{
|
||||
return irq_map[virq].host == host;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(virq_is_host);
|
||||
|
||||
static int default_irq_host_match(struct irq_host *h, struct device_node *np)
|
||||
{
|
||||
return h->of_node != NULL && h->of_node == np;
|
||||
@ -511,7 +536,7 @@ struct irq_host *irq_alloc_host(struct device_node *of_node,
|
||||
/* Allocate structure and revmap table if using linear mapping */
|
||||
if (revmap_type == IRQ_HOST_MAP_LINEAR)
|
||||
size += revmap_arg * sizeof(unsigned int);
|
||||
host = zalloc_maybe_bootmem(size, GFP_KERNEL);
|
||||
host = kzalloc(size, GFP_KERNEL);
|
||||
if (host == NULL)
|
||||
return NULL;
|
||||
|
||||
@ -561,14 +586,14 @@ struct irq_host *irq_alloc_host(struct device_node *of_node,
|
||||
irq_map[i].host = host;
|
||||
smp_wmb();
|
||||
|
||||
/* Clear norequest flags */
|
||||
irq_clear_status_flags(i, IRQ_NOREQUEST);
|
||||
|
||||
/* Legacy flags are left to default at this point,
|
||||
* one can then use irq_create_mapping() to
|
||||
* explicitly change them
|
||||
*/
|
||||
ops->map(host, i, i);
|
||||
|
||||
/* Clear norequest flags */
|
||||
irq_clear_status_flags(i, IRQ_NOREQUEST);
|
||||
}
|
||||
break;
|
||||
case IRQ_HOST_MAP_LINEAR:
|
||||
@ -579,6 +604,9 @@ struct irq_host *irq_alloc_host(struct device_node *of_node,
|
||||
smp_wmb();
|
||||
host->revmap_data.linear.revmap = rmap;
|
||||
break;
|
||||
case IRQ_HOST_MAP_TREE:
|
||||
INIT_RADIX_TREE(&host->revmap_data.tree, GFP_KERNEL);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
@ -636,8 +664,6 @@ static int irq_setup_virq(struct irq_host *host, unsigned int virq,
|
||||
goto error;
|
||||
}
|
||||
|
||||
irq_clear_status_flags(virq, IRQ_NOREQUEST);
|
||||
|
||||
/* map it */
|
||||
smp_wmb();
|
||||
irq_map[virq].hwirq = hwirq;
|
||||
@ -648,6 +674,8 @@ static int irq_setup_virq(struct irq_host *host, unsigned int virq,
|
||||
goto errdesc;
|
||||
}
|
||||
|
||||
irq_clear_status_flags(virq, IRQ_NOREQUEST);
|
||||
|
||||
return 0;
|
||||
|
||||
errdesc:
|
||||
@ -704,8 +732,6 @@ unsigned int irq_create_mapping(struct irq_host *host,
|
||||
*/
|
||||
virq = irq_find_mapping(host, hwirq);
|
||||
if (virq != NO_IRQ) {
|
||||
if (host->ops->remap)
|
||||
host->ops->remap(host, virq, hwirq);
|
||||
pr_debug("irq: -> existing mapping on virq %d\n", virq);
|
||||
return virq;
|
||||
}
|
||||
@ -786,14 +812,15 @@ void irq_dispose_mapping(unsigned int virq)
|
||||
return;
|
||||
|
||||
host = irq_map[virq].host;
|
||||
WARN_ON (host == NULL);
|
||||
if (host == NULL)
|
||||
if (WARN_ON(host == NULL))
|
||||
return;
|
||||
|
||||
/* Never unmap legacy interrupts */
|
||||
if (host->revmap_type == IRQ_HOST_MAP_LEGACY)
|
||||
return;
|
||||
|
||||
irq_set_status_flags(virq, IRQ_NOREQUEST);
|
||||
|
||||
/* remove chip and handler */
|
||||
irq_set_chip_and_handler(virq, NULL, NULL);
|
||||
|
||||
@ -813,13 +840,6 @@ void irq_dispose_mapping(unsigned int virq)
|
||||
host->revmap_data.linear.revmap[hwirq] = NO_IRQ;
|
||||
break;
|
||||
case IRQ_HOST_MAP_TREE:
|
||||
/*
|
||||
* Check if radix tree allocated yet, if not then nothing to
|
||||
* remove.
|
||||
*/
|
||||
smp_rmb();
|
||||
if (revmap_trees_allocated < 1)
|
||||
break;
|
||||
mutex_lock(&revmap_trees_mutex);
|
||||
radix_tree_delete(&host->revmap_data.tree, hwirq);
|
||||
mutex_unlock(&revmap_trees_mutex);
|
||||
@ -830,8 +850,6 @@ void irq_dispose_mapping(unsigned int virq)
|
||||
smp_mb();
|
||||
irq_map[virq].hwirq = host->inval_irq;
|
||||
|
||||
irq_set_status_flags(virq, IRQ_NOREQUEST);
|
||||
|
||||
irq_free_descs(virq, 1);
|
||||
/* Free it */
|
||||
irq_free_virt(virq, 1);
|
||||
@ -877,16 +895,9 @@ unsigned int irq_radix_revmap_lookup(struct irq_host *host,
|
||||
struct irq_map_entry *ptr;
|
||||
unsigned int virq;
|
||||
|
||||
WARN_ON(host->revmap_type != IRQ_HOST_MAP_TREE);
|
||||
|
||||
/*
|
||||
* Check if the radix tree exists and has bee initialized.
|
||||
* If not, we fallback to slow mode
|
||||
*/
|
||||
if (revmap_trees_allocated < 2)
|
||||
if (WARN_ON_ONCE(host->revmap_type != IRQ_HOST_MAP_TREE))
|
||||
return irq_find_mapping(host, hwirq);
|
||||
|
||||
/* Now try to resolve */
|
||||
/*
|
||||
* No rcu_read_lock(ing) needed, the ptr returned can't go under us
|
||||
* as it's referencing an entry in the static irq_map table.
|
||||
@ -909,16 +920,7 @@ unsigned int irq_radix_revmap_lookup(struct irq_host *host,
|
||||
void irq_radix_revmap_insert(struct irq_host *host, unsigned int virq,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
|
||||
WARN_ON(host->revmap_type != IRQ_HOST_MAP_TREE);
|
||||
|
||||
/*
|
||||
* Check if the radix tree exists yet.
|
||||
* If not, then the irq will be inserted into the tree when it gets
|
||||
* initialized.
|
||||
*/
|
||||
smp_rmb();
|
||||
if (revmap_trees_allocated < 1)
|
||||
if (WARN_ON(host->revmap_type != IRQ_HOST_MAP_TREE))
|
||||
return;
|
||||
|
||||
if (virq != NO_IRQ) {
|
||||
@ -934,7 +936,8 @@ unsigned int irq_linear_revmap(struct irq_host *host,
|
||||
{
|
||||
unsigned int *revmap;
|
||||
|
||||
WARN_ON(host->revmap_type != IRQ_HOST_MAP_LINEAR);
|
||||
if (WARN_ON_ONCE(host->revmap_type != IRQ_HOST_MAP_LINEAR))
|
||||
return irq_find_mapping(host, hwirq);
|
||||
|
||||
/* Check revmap bounds */
|
||||
if (unlikely(hwirq >= host->revmap_data.linear.size))
|
||||
@ -1028,53 +1031,6 @@ int arch_early_irq_init(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* We need to create the radix trees late */
|
||||
static int irq_late_init(void)
|
||||
{
|
||||
struct irq_host *h;
|
||||
unsigned int i;
|
||||
|
||||
/*
|
||||
* No mutual exclusion with respect to accessors of the tree is needed
|
||||
* here as the synchronization is done via the state variable
|
||||
* revmap_trees_allocated.
|
||||
*/
|
||||
list_for_each_entry(h, &irq_hosts, link) {
|
||||
if (h->revmap_type == IRQ_HOST_MAP_TREE)
|
||||
INIT_RADIX_TREE(&h->revmap_data.tree, GFP_KERNEL);
|
||||
}
|
||||
|
||||
/*
|
||||
* Make sure the radix trees inits are visible before setting
|
||||
* the flag
|
||||
*/
|
||||
smp_wmb();
|
||||
revmap_trees_allocated = 1;
|
||||
|
||||
/*
|
||||
* Insert the reverse mapping for those interrupts already present
|
||||
* in irq_map[].
|
||||
*/
|
||||
mutex_lock(&revmap_trees_mutex);
|
||||
for (i = 0; i < irq_virq_count; i++) {
|
||||
if (irq_map[i].host &&
|
||||
(irq_map[i].host->revmap_type == IRQ_HOST_MAP_TREE))
|
||||
radix_tree_insert(&irq_map[i].host->revmap_data.tree,
|
||||
irq_map[i].hwirq, &irq_map[i]);
|
||||
}
|
||||
mutex_unlock(&revmap_trees_mutex);
|
||||
|
||||
/*
|
||||
* Make sure the radix trees insertions are visible before setting
|
||||
* the flag
|
||||
*/
|
||||
smp_wmb();
|
||||
revmap_trees_allocated = 2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(irq_late_init);
|
||||
|
||||
#ifdef CONFIG_VIRQ_DEBUG
|
||||
static int virq_debug_show(struct seq_file *m, void *private)
|
||||
{
|
||||
@ -1082,10 +1038,11 @@ static int virq_debug_show(struct seq_file *m, void *private)
|
||||
struct irq_desc *desc;
|
||||
const char *p;
|
||||
static const char none[] = "none";
|
||||
void *data;
|
||||
int i;
|
||||
|
||||
seq_printf(m, "%-5s %-7s %-15s %s\n", "virq", "hwirq",
|
||||
"chip name", "host name");
|
||||
seq_printf(m, "%-5s %-7s %-15s %-18s %s\n", "virq", "hwirq",
|
||||
"chip name", "chip data", "host name");
|
||||
|
||||
for (i = 1; i < nr_irqs; i++) {
|
||||
desc = irq_to_desc(i);
|
||||
@ -1098,7 +1055,7 @@ static int virq_debug_show(struct seq_file *m, void *private)
|
||||
struct irq_chip *chip;
|
||||
|
||||
seq_printf(m, "%5d ", i);
|
||||
seq_printf(m, "0x%05lx ", virq_to_hw(i));
|
||||
seq_printf(m, "0x%05lx ", irq_map[i].hwirq);
|
||||
|
||||
chip = irq_desc_get_chip(desc);
|
||||
if (chip && chip->name)
|
||||
@ -1107,6 +1064,9 @@ static int virq_debug_show(struct seq_file *m, void *private)
|
||||
p = none;
|
||||
seq_printf(m, "%-15s ", p);
|
||||
|
||||
data = irq_desc_get_chip_data(desc);
|
||||
seq_printf(m, "0x%16p ", data);
|
||||
|
||||
if (irq_map[i].host && irq_map[i].host->of_node)
|
||||
p = irq_map[i].host->of_node->full_name;
|
||||
else
|
||||
|
||||
@ -109,7 +109,7 @@ static int kgdb_call_nmi_hook(struct pt_regs *regs)
|
||||
#ifdef CONFIG_SMP
|
||||
void kgdb_roundup_cpus(unsigned long flags)
|
||||
{
|
||||
smp_send_debugger_break(MSG_ALL_BUT_SELF);
|
||||
smp_send_debugger_break();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -132,34 +132,6 @@ static int iseries_lparcfg_data(struct seq_file *m, void *v)
|
||||
/*
|
||||
* Methods used to fetch LPAR data when running on a pSeries platform.
|
||||
*/
|
||||
/**
|
||||
* h_get_mpp
|
||||
* H_GET_MPP hcall returns info in 7 parms
|
||||
*/
|
||||
int h_get_mpp(struct hvcall_mpp_data *mpp_data)
|
||||
{
|
||||
int rc;
|
||||
unsigned long retbuf[PLPAR_HCALL9_BUFSIZE];
|
||||
|
||||
rc = plpar_hcall9(H_GET_MPP, retbuf);
|
||||
|
||||
mpp_data->entitled_mem = retbuf[0];
|
||||
mpp_data->mapped_mem = retbuf[1];
|
||||
|
||||
mpp_data->group_num = (retbuf[2] >> 2 * 8) & 0xffff;
|
||||
mpp_data->pool_num = retbuf[2] & 0xffff;
|
||||
|
||||
mpp_data->mem_weight = (retbuf[3] >> 7 * 8) & 0xff;
|
||||
mpp_data->unallocated_mem_weight = (retbuf[3] >> 6 * 8) & 0xff;
|
||||
mpp_data->unallocated_entitlement = retbuf[3] & 0xffffffffffff;
|
||||
|
||||
mpp_data->pool_size = retbuf[4];
|
||||
mpp_data->loan_request = retbuf[5];
|
||||
mpp_data->backing_mem = retbuf[6];
|
||||
|
||||
return rc;
|
||||
}
|
||||
EXPORT_SYMBOL(h_get_mpp);
|
||||
|
||||
struct hvcall_ppp_data {
|
||||
u64 entitlement;
|
||||
@ -345,6 +317,30 @@ static void parse_mpp_data(struct seq_file *m)
|
||||
seq_printf(m, "backing_memory=%ld bytes\n", mpp_data.backing_mem);
|
||||
}
|
||||
|
||||
/**
|
||||
* parse_mpp_x_data
|
||||
* Parse out data returned from h_get_mpp_x
|
||||
*/
|
||||
static void parse_mpp_x_data(struct seq_file *m)
|
||||
{
|
||||
struct hvcall_mpp_x_data mpp_x_data;
|
||||
|
||||
if (!firmware_has_feature(FW_FEATURE_XCMO))
|
||||
return;
|
||||
if (h_get_mpp_x(&mpp_x_data))
|
||||
return;
|
||||
|
||||
seq_printf(m, "coalesced_bytes=%ld\n", mpp_x_data.coalesced_bytes);
|
||||
|
||||
if (mpp_x_data.pool_coalesced_bytes)
|
||||
seq_printf(m, "pool_coalesced_bytes=%ld\n",
|
||||
mpp_x_data.pool_coalesced_bytes);
|
||||
if (mpp_x_data.pool_purr_cycles)
|
||||
seq_printf(m, "coalesce_pool_purr=%ld\n", mpp_x_data.pool_purr_cycles);
|
||||
if (mpp_x_data.pool_spurr_cycles)
|
||||
seq_printf(m, "coalesce_pool_spurr=%ld\n", mpp_x_data.pool_spurr_cycles);
|
||||
}
|
||||
|
||||
#define SPLPAR_CHARACTERISTICS_TOKEN 20
|
||||
#define SPLPAR_MAXLENGTH 1026*(sizeof(char))
|
||||
|
||||
@ -520,6 +516,7 @@ static int pseries_lparcfg_data(struct seq_file *m, void *v)
|
||||
parse_system_parameter_string(m);
|
||||
parse_ppp_data(m);
|
||||
parse_mpp_data(m);
|
||||
parse_mpp_x_data(m);
|
||||
pseries_cmo_data(m);
|
||||
splpar_dispatch_data(m);
|
||||
|
||||
|
||||
@ -694,6 +694,17 @@ _GLOBAL(kernel_thread)
|
||||
addi r1,r1,16
|
||||
blr
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
_GLOBAL(start_secondary_resume)
|
||||
/* Reset stack */
|
||||
rlwinm r1,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
|
||||
addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
|
||||
li r3,0
|
||||
std r3,0(r1) /* Zero the stack frame pointer */
|
||||
bl start_secondary
|
||||
b .
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
/*
|
||||
* This routine is just here to keep GCC happy - sigh...
|
||||
*/
|
||||
|
||||
@ -462,7 +462,8 @@ _GLOBAL(disable_kernel_fp)
|
||||
* wait for the flag to change, indicating this kernel is going away but
|
||||
* the slave code for the next one is at addresses 0 to 100.
|
||||
*
|
||||
* This is used by all slaves.
|
||||
* This is used by all slaves, even those that did not find a matching
|
||||
* paca in the secondary startup code.
|
||||
*
|
||||
* Physical (hardware) cpu id should be in r3.
|
||||
*/
|
||||
@ -471,10 +472,6 @@ _GLOBAL(kexec_wait)
|
||||
1: mflr r5
|
||||
addi r5,r5,kexec_flag-1b
|
||||
|
||||
li r4,KEXEC_STATE_REAL_MODE
|
||||
stb r4,PACAKEXECSTATE(r13)
|
||||
SYNC
|
||||
|
||||
99: HMT_LOW
|
||||
#ifdef CONFIG_KEXEC /* use no memory without kexec */
|
||||
lwz r4,0(r5)
|
||||
@ -499,11 +496,17 @@ kexec_flag:
|
||||
*
|
||||
* get phys id from paca
|
||||
* switch to real mode
|
||||
* mark the paca as no longer used
|
||||
* join other cpus in kexec_wait(phys_id)
|
||||
*/
|
||||
_GLOBAL(kexec_smp_wait)
|
||||
lhz r3,PACAHWCPUID(r13)
|
||||
bl real_mode
|
||||
|
||||
li r4,KEXEC_STATE_REAL_MODE
|
||||
stb r4,PACAKEXECSTATE(r13)
|
||||
SYNC
|
||||
|
||||
b .kexec_wait
|
||||
|
||||
/*
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/threads.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/memblock.h>
|
||||
|
||||
@ -156,18 +156,29 @@ void __init initialise_paca(struct paca_struct *new_paca, int cpu)
|
||||
/* Put the paca pointer into r13 and SPRG_PACA */
|
||||
void setup_paca(struct paca_struct *new_paca)
|
||||
{
|
||||
/* Setup r13 */
|
||||
local_paca = new_paca;
|
||||
mtspr(SPRN_SPRG_PACA, local_paca);
|
||||
|
||||
#ifdef CONFIG_PPC_BOOK3E
|
||||
/* On Book3E, initialize the TLB miss exception frames */
|
||||
mtspr(SPRN_SPRG_TLB_EXFRAME, local_paca->extlb);
|
||||
#else
|
||||
/* In HV mode, we setup both HPACA and PACA to avoid problems
|
||||
* if we do a GET_PACA() before the feature fixups have been
|
||||
* applied
|
||||
*/
|
||||
if (cpu_has_feature(CPU_FTR_HVMODE_206))
|
||||
mtspr(SPRN_SPRG_HPACA, local_paca);
|
||||
#endif
|
||||
mtspr(SPRN_SPRG_PACA, local_paca);
|
||||
|
||||
}
|
||||
|
||||
static int __initdata paca_size;
|
||||
|
||||
void __init allocate_pacas(void)
|
||||
{
|
||||
int nr_cpus, cpu, limit;
|
||||
int cpu, limit;
|
||||
|
||||
/*
|
||||
* We can't take SLB misses on the paca, and we want to access them
|
||||
@ -179,23 +190,18 @@ void __init allocate_pacas(void)
|
||||
if (firmware_has_feature(FW_FEATURE_ISERIES))
|
||||
limit = min(limit, HvPagesToMap * HVPAGESIZE);
|
||||
|
||||
nr_cpus = NR_CPUS;
|
||||
/* On iSeries we know we can never have more than 64 cpus */
|
||||
if (firmware_has_feature(FW_FEATURE_ISERIES))
|
||||
nr_cpus = min(64, nr_cpus);
|
||||
|
||||
paca_size = PAGE_ALIGN(sizeof(struct paca_struct) * nr_cpus);
|
||||
paca_size = PAGE_ALIGN(sizeof(struct paca_struct) * nr_cpu_ids);
|
||||
|
||||
paca = __va(memblock_alloc_base(paca_size, PAGE_SIZE, limit));
|
||||
memset(paca, 0, paca_size);
|
||||
|
||||
printk(KERN_DEBUG "Allocated %u bytes for %d pacas at %p\n",
|
||||
paca_size, nr_cpus, paca);
|
||||
paca_size, nr_cpu_ids, paca);
|
||||
|
||||
allocate_lppacas(nr_cpus, limit);
|
||||
allocate_lppacas(nr_cpu_ids, limit);
|
||||
|
||||
/* Can't use for_each_*_cpu, as they aren't functional yet */
|
||||
for (cpu = 0; cpu < nr_cpus; cpu++)
|
||||
for (cpu = 0; cpu < nr_cpu_ids; cpu++)
|
||||
initialise_paca(&paca[cpu], cpu);
|
||||
}
|
||||
|
||||
|
||||
@ -43,10 +43,9 @@ void * __devinit update_dn_pci_info(struct device_node *dn, void *data)
|
||||
const u32 *regs;
|
||||
struct pci_dn *pdn;
|
||||
|
||||
pdn = alloc_maybe_bootmem(sizeof(*pdn), GFP_KERNEL);
|
||||
pdn = zalloc_maybe_bootmem(sizeof(*pdn), GFP_KERNEL);
|
||||
if (pdn == NULL)
|
||||
return NULL;
|
||||
memset(pdn, 0, sizeof(*pdn));
|
||||
dn->data = pdn;
|
||||
pdn->node = dn;
|
||||
pdn->phb = phb;
|
||||
|
||||
@ -54,7 +54,6 @@ extern void single_step_exception(struct pt_regs *regs);
|
||||
extern int sys_sigreturn(struct pt_regs *regs);
|
||||
|
||||
EXPORT_SYMBOL(clear_pages);
|
||||
EXPORT_SYMBOL(copy_page);
|
||||
EXPORT_SYMBOL(ISA_DMA_THRESHOLD);
|
||||
EXPORT_SYMBOL(DMA_MODE_READ);
|
||||
EXPORT_SYMBOL(DMA_MODE_WRITE);
|
||||
@ -88,9 +87,7 @@ EXPORT_SYMBOL(__copy_tofrom_user);
|
||||
EXPORT_SYMBOL(__clear_user);
|
||||
EXPORT_SYMBOL(__strncpy_from_user);
|
||||
EXPORT_SYMBOL(__strnlen_user);
|
||||
#ifdef CONFIG_PPC64
|
||||
EXPORT_SYMBOL(copy_4K_page);
|
||||
#endif
|
||||
EXPORT_SYMBOL(copy_page);
|
||||
|
||||
#if defined(CONFIG_PCI) && defined(CONFIG_PPC32)
|
||||
EXPORT_SYMBOL(isa_io_base);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user