libata: make SCR access ops per-link
Logically, SCR access ops should take @link; however, there was no compelling reason to convert all SCR access ops when adding @link abstraction as there's one-to-one mapping between a port and a non-PMP link. However, that assumption won't hold anymore with the scheduled addition of slave link. Make SCR access ops per-link. Signed-off-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This commit is contained in:
parent
6ef190cc92
commit
82ef04fb4c
@ -267,8 +267,8 @@ struct ahci_port_priv {
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* per PM slot */
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};
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static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
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static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
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static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
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static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
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static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
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static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
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@ -820,10 +820,10 @@ static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
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return 0;
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}
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static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
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static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
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{
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void __iomem *port_mmio = ahci_port_base(ap);
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int offset = ahci_scr_offset(ap, sc_reg);
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void __iomem *port_mmio = ahci_port_base(link->ap);
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int offset = ahci_scr_offset(link->ap, sc_reg);
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if (offset) {
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*val = readl(port_mmio + offset);
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@ -832,10 +832,10 @@ static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
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return -EINVAL;
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}
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static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
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static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
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{
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void __iomem *port_mmio = ahci_port_base(ap);
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int offset = ahci_scr_offset(ap, sc_reg);
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void __iomem *port_mmio = ahci_port_base(link->ap);
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int offset = ahci_scr_offset(link->ap, sc_reg);
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if (offset) {
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writel(val, port_mmio + offset);
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@ -973,7 +973,7 @@ static void ahci_disable_alpm(struct ata_port *ap)
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writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
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/* go ahead and clean out PhyRdy Change from Serror too */
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ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
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ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
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/*
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* Clear flag to indicate that we should ignore all PhyRdy
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@ -1937,8 +1937,8 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
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ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
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/* AHCI needs SError cleared; otherwise, it might lock up */
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ahci_scr_read(ap, SCR_ERROR, &serror);
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ahci_scr_write(ap, SCR_ERROR, serror);
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ahci_scr_read(&ap->link, SCR_ERROR, &serror);
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ahci_scr_write(&ap->link, SCR_ERROR, serror);
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host_ehi->serror |= serror;
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/* some controllers set IRQ_IF_ERR on device errors, ignore it */
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@ -2027,7 +2027,7 @@ static void ahci_port_intr(struct ata_port *ap)
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if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
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(status & PORT_IRQ_PHYRDY)) {
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status &= ~PORT_IRQ_PHYRDY;
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ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
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ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
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}
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if (unlikely(status & PORT_IRQ_ERROR)) {
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@ -165,8 +165,10 @@ static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
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static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
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static int ich_pata_cable_detect(struct ata_port *ap);
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static u8 piix_vmw_bmdma_status(struct ata_port *ap);
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static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val);
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static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val);
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static int piix_sidpr_scr_read(struct ata_link *link,
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unsigned int reg, u32 *val);
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static int piix_sidpr_scr_write(struct ata_link *link,
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unsigned int reg, u32 val);
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#ifdef CONFIG_PM
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static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
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static int piix_pci_device_resume(struct pci_dev *pdev);
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@ -971,8 +973,10 @@ static u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl)
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return val;
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}
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static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val)
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static int piix_sidpr_scr_read(struct ata_link *link,
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unsigned int reg, u32 *val)
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{
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struct ata_port *ap = link->ap;
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const int * const sstatus_merge_tbl[] = {
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/* DET */ (const int []){ 1, 3, 0, 4, 3, -1 },
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/* SPD */ (const int []){ 2, 1, 0, -1 },
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@ -1013,8 +1017,11 @@ static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val)
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return 0;
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}
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static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val)
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static int piix_sidpr_scr_write(struct ata_link *link,
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unsigned int reg, u32 val)
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{
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struct ata_port *ap = link->ap;
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if (reg >= ARRAY_SIZE(piix_sidx_map))
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return -EINVAL;
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@ -4868,10 +4868,8 @@ int sata_scr_valid(struct ata_link *link)
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int sata_scr_read(struct ata_link *link, int reg, u32 *val)
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{
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if (ata_is_host_link(link)) {
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struct ata_port *ap = link->ap;
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if (sata_scr_valid(link))
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return ap->ops->scr_read(ap, reg, val);
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return link->ap->ops->scr_read(link, reg, val);
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return -EOPNOTSUPP;
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}
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@ -4897,10 +4895,8 @@ int sata_scr_read(struct ata_link *link, int reg, u32 *val)
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int sata_scr_write(struct ata_link *link, int reg, u32 val)
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{
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if (ata_is_host_link(link)) {
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struct ata_port *ap = link->ap;
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if (sata_scr_valid(link))
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return ap->ops->scr_write(ap, reg, val);
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return link->ap->ops->scr_write(link, reg, val);
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return -EOPNOTSUPP;
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}
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@ -4925,13 +4921,12 @@ int sata_scr_write(struct ata_link *link, int reg, u32 val)
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int sata_scr_write_flush(struct ata_link *link, int reg, u32 val)
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{
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if (ata_is_host_link(link)) {
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struct ata_port *ap = link->ap;
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int rc;
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if (sata_scr_valid(link)) {
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rc = ap->ops->scr_write(ap, reg, val);
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rc = link->ap->ops->scr_write(link, reg, val);
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if (rc == 0)
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rc = ap->ops->scr_read(ap, reg, &val);
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rc = link->ap->ops->scr_read(link, reg, &val);
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return rc;
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}
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return -EOPNOTSUPP;
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@ -469,10 +469,10 @@ static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
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return true;
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}
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static int sata_fsl_scr_write(struct ata_port *ap, unsigned int sc_reg_in,
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u32 val)
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static int sata_fsl_scr_write(struct ata_link *link,
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unsigned int sc_reg_in, u32 val)
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{
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struct sata_fsl_host_priv *host_priv = ap->host->private_data;
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struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
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void __iomem *ssr_base = host_priv->ssr_base;
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unsigned int sc_reg;
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@ -493,10 +493,10 @@ static int sata_fsl_scr_write(struct ata_port *ap, unsigned int sc_reg_in,
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return 0;
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}
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static int sata_fsl_scr_read(struct ata_port *ap, unsigned int sc_reg_in,
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u32 *val)
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static int sata_fsl_scr_read(struct ata_link *link,
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unsigned int sc_reg_in, u32 *val)
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{
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struct sata_fsl_host_priv *host_priv = ap->host->private_data;
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struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
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void __iomem *ssr_base = host_priv->ssr_base;
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unsigned int sc_reg;
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@ -645,12 +645,12 @@ static int sata_fsl_port_start(struct ata_port *ap)
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* Workaround for 8315DS board 3gbps link-up issue,
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* currently limit SATA port to GEN1 speed
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*/
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sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
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sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
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temp &= ~(0xF << 4);
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temp |= (0x1 << 4);
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sata_fsl_scr_write(ap, SCR_CONTROL, temp);
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sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp);
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sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
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sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
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dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n",
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temp);
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#endif
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@ -868,7 +868,7 @@ issue_srst:
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ioread32(CQ + hcr_base),
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ioread32(CA + hcr_base), ioread32(CC + hcr_base));
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sata_fsl_scr_read(ap, SCR_ERROR, &Serror);
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sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
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DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
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DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
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@ -972,9 +972,9 @@ static void sata_fsl_error_intr(struct ata_port *ap)
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* Handle & Clear SError
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*/
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sata_fsl_scr_read(ap, SCR_ERROR, &SError);
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sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
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if (unlikely(SError & 0xFFFF0000)) {
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sata_fsl_scr_write(ap, SCR_ERROR, SError);
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sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
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}
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DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
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@ -1091,7 +1091,7 @@ static void sata_fsl_host_intr(struct ata_port *ap)
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hstatus = ioread32(hcr_base + HSTATUS);
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sata_fsl_scr_read(ap, SCR_ERROR, &SError);
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sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
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if (unlikely(SError & 0xFFFF0000)) {
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DPRINTK("serror @host_intr : 0x%x\n", SError);
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@ -269,9 +269,9 @@ static void inic_reset_port(void __iomem *port_base)
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writeb(0xff, port_base + PORT_IRQ_STAT);
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}
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static int inic_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
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static int inic_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
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{
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void __iomem *scr_addr = inic_port_base(ap) + PORT_SCR;
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void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
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void __iomem *addr;
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if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
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@ -286,9 +286,9 @@ static int inic_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
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return 0;
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}
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static int inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
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static int inic_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
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{
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void __iomem *scr_addr = inic_port_base(ap) + PORT_SCR;
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void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
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if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
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return -EINVAL;
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@ -493,10 +493,10 @@ struct mv_hw_ops {
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void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
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};
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static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
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static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
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static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
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static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
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static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
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static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
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static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
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static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
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static int mv_port_start(struct ata_port *ap);
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static void mv_port_stop(struct ata_port *ap);
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static int mv_qc_defer(struct ata_queued_cmd *qc);
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@ -1070,23 +1070,23 @@ static unsigned int mv_scr_offset(unsigned int sc_reg_in)
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return ofs;
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}
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static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
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static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
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{
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unsigned int ofs = mv_scr_offset(sc_reg_in);
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if (ofs != 0xffffffffU) {
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*val = readl(mv_ap_base(ap) + ofs);
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*val = readl(mv_ap_base(link->ap) + ofs);
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return 0;
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} else
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return -EINVAL;
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}
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static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
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static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
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{
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unsigned int ofs = mv_scr_offset(sc_reg_in);
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if (ofs != 0xffffffffU) {
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writelfl(val, mv_ap_base(ap) + ofs);
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writelfl(val, mv_ap_base(link->ap) + ofs);
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return 0;
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} else
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return -EINVAL;
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@ -2251,11 +2251,11 @@ static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
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return ofs;
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}
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static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
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static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
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{
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struct mv_host_priv *hpriv = ap->host->private_data;
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struct mv_host_priv *hpriv = link->ap->host->private_data;
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void __iomem *mmio = hpriv->base;
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void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
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void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
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unsigned int ofs = mv5_scr_offset(sc_reg_in);
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if (ofs != 0xffffffffU) {
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@ -2265,11 +2265,11 @@ static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
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return -EINVAL;
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}
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static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
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static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
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{
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struct mv_host_priv *hpriv = ap->host->private_data;
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struct mv_host_priv *hpriv = link->ap->host->private_data;
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void __iomem *mmio = hpriv->base;
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void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
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void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
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unsigned int ofs = mv5_scr_offset(sc_reg_in);
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if (ofs != 0xffffffffU) {
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@ -302,8 +302,8 @@ static void nv_ck804_host_stop(struct ata_host *host);
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static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance);
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static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance);
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static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance);
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static int nv_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
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static int nv_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
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static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
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static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
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static void nv_nf2_freeze(struct ata_port *ap);
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static void nv_nf2_thaw(struct ata_port *ap);
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@ -1492,21 +1492,21 @@ static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance)
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return ret;
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}
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static int nv_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
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static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
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{
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if (sc_reg > SCR_CONTROL)
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return -EINVAL;
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*val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
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*val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg * 4));
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return 0;
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}
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static int nv_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
|
||||
{
|
||||
if (sc_reg > SCR_CONTROL)
|
||||
return -EINVAL;
|
||||
|
||||
iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -2184,9 +2184,9 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
|
||||
if (!pp->qc_active)
|
||||
return;
|
||||
|
||||
if (ap->ops->scr_read(ap, SCR_ERROR, &serror))
|
||||
if (ap->ops->scr_read(&ap->link, SCR_ERROR, &serror))
|
||||
return;
|
||||
ap->ops->scr_write(ap, SCR_ERROR, serror);
|
||||
ap->ops->scr_write(&ap->link, SCR_ERROR, serror);
|
||||
|
||||
if (ata_stat & ATA_ERR) {
|
||||
ata_ehi_clear_desc(ehi);
|
||||
|
@ -137,8 +137,8 @@ struct pdc_port_priv {
|
||||
dma_addr_t pkt_dma;
|
||||
};
|
||||
|
||||
static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
|
||||
static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
|
||||
static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
|
||||
static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
|
||||
static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int pdc_common_port_start(struct ata_port *ap);
|
||||
static int pdc_sata_port_start(struct ata_port *ap);
|
||||
@ -386,19 +386,21 @@ static int pdc_sata_cable_detect(struct ata_port *ap)
|
||||
return ATA_CBL_SATA;
|
||||
}
|
||||
|
||||
static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
static int pdc_sata_scr_read(struct ata_link *link,
|
||||
unsigned int sc_reg, u32 *val)
|
||||
{
|
||||
if (sc_reg > SCR_CONTROL)
|
||||
return -EINVAL;
|
||||
*val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
static int pdc_sata_scr_write(struct ata_link *link,
|
||||
unsigned int sc_reg, u32 val)
|
||||
{
|
||||
if (sc_reg > SCR_CONTROL)
|
||||
return -EINVAL;
|
||||
writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -731,7 +733,7 @@ static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
|
||||
if (sata_scr_valid(&ap->link)) {
|
||||
u32 serror;
|
||||
|
||||
pdc_sata_scr_read(ap, SCR_ERROR, &serror);
|
||||
pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror);
|
||||
ehi->serror |= serror;
|
||||
}
|
||||
|
||||
|
@ -111,8 +111,8 @@ struct qs_port_priv {
|
||||
qs_state_t state;
|
||||
};
|
||||
|
||||
static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
|
||||
static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
|
||||
static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
|
||||
static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
|
||||
static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int qs_port_start(struct ata_port *ap);
|
||||
static void qs_host_stop(struct ata_host *host);
|
||||
@ -242,11 +242,11 @@ static int qs_prereset(struct ata_link *link, unsigned long deadline)
|
||||
return ata_sff_prereset(link, deadline);
|
||||
}
|
||||
|
||||
static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
|
||||
{
|
||||
if (sc_reg > SCR_CONTROL)
|
||||
return -EINVAL;
|
||||
*val = readl(ap->ioaddr.scr_addr + (sc_reg * 8));
|
||||
*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 8));
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -256,11 +256,11 @@ static void qs_error_handler(struct ata_port *ap)
|
||||
ata_std_error_handler(ap);
|
||||
}
|
||||
|
||||
static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
|
||||
{
|
||||
if (sc_reg > SCR_CONTROL)
|
||||
return -EINVAL;
|
||||
writel(val, ap->ioaddr.scr_addr + (sc_reg * 8));
|
||||
writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 8));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -115,8 +115,8 @@ static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int sil_pci_device_resume(struct pci_dev *pdev);
|
||||
#endif
|
||||
static void sil_dev_config(struct ata_device *dev);
|
||||
static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
|
||||
static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
|
||||
static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
|
||||
static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
|
||||
static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed);
|
||||
static void sil_freeze(struct ata_port *ap);
|
||||
static void sil_thaw(struct ata_port *ap);
|
||||
@ -317,9 +317,9 @@ static inline void __iomem *sil_scr_addr(struct ata_port *ap,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
|
||||
{
|
||||
void __iomem *mmio = sil_scr_addr(ap, sc_reg);
|
||||
void __iomem *mmio = sil_scr_addr(link->ap, sc_reg);
|
||||
|
||||
if (mmio) {
|
||||
*val = readl(mmio);
|
||||
@ -328,9 +328,9 @@ static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
|
||||
{
|
||||
void __iomem *mmio = sil_scr_addr(ap, sc_reg);
|
||||
void __iomem *mmio = sil_scr_addr(link->ap, sc_reg);
|
||||
|
||||
if (mmio) {
|
||||
writel(val, mmio);
|
||||
@ -352,8 +352,8 @@ static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
|
||||
* controllers continue to assert IRQ as long as
|
||||
* SError bits are pending. Clear SError immediately.
|
||||
*/
|
||||
sil_scr_read(ap, SCR_ERROR, &serror);
|
||||
sil_scr_write(ap, SCR_ERROR, serror);
|
||||
sil_scr_read(&ap->link, SCR_ERROR, &serror);
|
||||
sil_scr_write(&ap->link, SCR_ERROR, serror);
|
||||
|
||||
/* Sometimes spurious interrupts occur, double check
|
||||
* it's PHYRDY CHG.
|
||||
|
@ -340,8 +340,8 @@ struct sil24_port_priv {
|
||||
};
|
||||
|
||||
static void sil24_dev_config(struct ata_device *dev);
|
||||
static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
|
||||
static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
|
||||
static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val);
|
||||
static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val);
|
||||
static int sil24_qc_defer(struct ata_queued_cmd *qc);
|
||||
static void sil24_qc_prep(struct ata_queued_cmd *qc);
|
||||
static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
|
||||
@ -504,9 +504,9 @@ static int sil24_scr_map[] = {
|
||||
[SCR_ACTIVE] = 3,
|
||||
};
|
||||
|
||||
static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
|
||||
static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
|
||||
{
|
||||
void __iomem *scr_addr = sil24_port_base(ap) + PORT_SCONTROL;
|
||||
void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
|
||||
|
||||
if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
|
||||
void __iomem *addr;
|
||||
@ -517,9 +517,9 @@ static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
|
||||
static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
|
||||
{
|
||||
void __iomem *scr_addr = sil24_port_base(ap) + PORT_SCONTROL;
|
||||
void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
|
||||
|
||||
if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
|
||||
void __iomem *addr;
|
||||
|
@ -64,8 +64,8 @@ enum {
|
||||
};
|
||||
|
||||
static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int sis_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
|
||||
static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
|
||||
static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
|
||||
static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
|
||||
|
||||
static const struct pci_device_id sis_pci_tbl[] = {
|
||||
{ PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
|
||||
@ -134,10 +134,11 @@ static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
|
||||
return addr;
|
||||
}
|
||||
|
||||
static u32 sis_scr_cfg_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
static u32 sis_scr_cfg_read(struct ata_link *link,
|
||||
unsigned int sc_reg, u32 *val)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
||||
unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
|
||||
struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
|
||||
unsigned int cfg_addr = get_scr_cfg_addr(link->ap, sc_reg);
|
||||
u32 val2 = 0;
|
||||
u8 pmr;
|
||||
|
||||
@ -158,10 +159,11 @@ static u32 sis_scr_cfg_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sis_scr_cfg_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
static int sis_scr_cfg_write(struct ata_link *link,
|
||||
unsigned int sc_reg, u32 val)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
||||
unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
|
||||
struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
|
||||
unsigned int cfg_addr = get_scr_cfg_addr(link->ap, sc_reg);
|
||||
u8 pmr;
|
||||
|
||||
if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
|
||||
@ -178,8 +180,9 @@ static int sis_scr_cfg_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sis_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
|
||||
{
|
||||
struct ata_port *ap = link->ap;
|
||||
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
||||
u8 pmr;
|
||||
|
||||
@ -187,7 +190,7 @@ static int sis_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
return -EINVAL;
|
||||
|
||||
if (ap->flags & SIS_FLAG_CFGSCR)
|
||||
return sis_scr_cfg_read(ap, sc_reg, val);
|
||||
return sis_scr_cfg_read(link, sc_reg, val);
|
||||
|
||||
pci_read_config_byte(pdev, SIS_PMR, &pmr);
|
||||
|
||||
@ -202,8 +205,9 @@ static int sis_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
|
||||
{
|
||||
struct ata_port *ap = link->ap;
|
||||
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
||||
u8 pmr;
|
||||
|
||||
@ -213,7 +217,7 @@ static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
pci_read_config_byte(pdev, SIS_PMR, &pmr);
|
||||
|
||||
if (ap->flags & SIS_FLAG_CFGSCR)
|
||||
return sis_scr_cfg_write(ap, sc_reg, val);
|
||||
return sis_scr_cfg_write(link, sc_reg, val);
|
||||
else {
|
||||
iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
|
||||
|
@ -123,20 +123,22 @@ static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
|
||||
}
|
||||
}
|
||||
|
||||
static int k2_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
static int k2_sata_scr_read(struct ata_link *link,
|
||||
unsigned int sc_reg, u32 *val)
|
||||
{
|
||||
if (sc_reg > SCR_CONTROL)
|
||||
return -EINVAL;
|
||||
*val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int k2_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
static int k2_sata_scr_write(struct ata_link *link,
|
||||
unsigned int sc_reg, u32 val)
|
||||
{
|
||||
if (sc_reg > SCR_CONTROL)
|
||||
return -EINVAL;
|
||||
writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -57,8 +57,8 @@ struct uli_priv {
|
||||
};
|
||||
|
||||
static int uli_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int uli_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
|
||||
static int uli_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
|
||||
static int uli_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
|
||||
static int uli_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
|
||||
|
||||
static const struct pci_device_id uli_pci_tbl[] = {
|
||||
{ PCI_VDEVICE(AL, 0x5289), uli_5289 },
|
||||
@ -107,39 +107,39 @@ static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
|
||||
return hpriv->scr_cfg_addr[ap->port_no] + (4 * sc_reg);
|
||||
}
|
||||
|
||||
static u32 uli_scr_cfg_read(struct ata_port *ap, unsigned int sc_reg)
|
||||
static u32 uli_scr_cfg_read(struct ata_link *link, unsigned int sc_reg)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
||||
unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
|
||||
struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
|
||||
unsigned int cfg_addr = get_scr_cfg_addr(link->ap, sc_reg);
|
||||
u32 val;
|
||||
|
||||
pci_read_config_dword(pdev, cfg_addr, &val);
|
||||
return val;
|
||||
}
|
||||
|
||||
static void uli_scr_cfg_write(struct ata_port *ap, unsigned int scr, u32 val)
|
||||
static void uli_scr_cfg_write(struct ata_link *link, unsigned int scr, u32 val)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
||||
unsigned int cfg_addr = get_scr_cfg_addr(ap, scr);
|
||||
struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
|
||||
unsigned int cfg_addr = get_scr_cfg_addr(link->ap, scr);
|
||||
|
||||
pci_write_config_dword(pdev, cfg_addr, val);
|
||||
}
|
||||
|
||||
static int uli_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
static int uli_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
|
||||
{
|
||||
if (sc_reg > SCR_CONTROL)
|
||||
return -EINVAL;
|
||||
|
||||
*val = uli_scr_cfg_read(ap, sc_reg);
|
||||
*val = uli_scr_cfg_read(link, sc_reg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int uli_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
static int uli_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
|
||||
{
|
||||
if (sc_reg > SCR_CONTROL) //SCR_CONTROL=2, SCR_ERROR=1, SCR_STATUS=0
|
||||
return -EINVAL;
|
||||
|
||||
uli_scr_cfg_write(ap, sc_reg, val);
|
||||
uli_scr_cfg_write(link, sc_reg, val);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -68,8 +68,8 @@ enum {
|
||||
};
|
||||
|
||||
static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static int svia_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
|
||||
static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
|
||||
static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
|
||||
static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
|
||||
static void svia_noop_freeze(struct ata_port *ap);
|
||||
static int vt6420_prereset(struct ata_link *link, unsigned long deadline);
|
||||
static int vt6421_pata_cable_detect(struct ata_port *ap);
|
||||
@ -152,19 +152,19 @@ MODULE_LICENSE("GPL");
|
||||
MODULE_DEVICE_TABLE(pci, svia_pci_tbl);
|
||||
MODULE_VERSION(DRV_VERSION);
|
||||
|
||||
static int svia_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
|
||||
{
|
||||
if (sc_reg > SCR_CONTROL)
|
||||
return -EINVAL;
|
||||
*val = ioread32(ap->ioaddr.scr_addr + (4 * sc_reg));
|
||||
*val = ioread32(link->ap->ioaddr.scr_addr + (4 * sc_reg));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
|
||||
{
|
||||
if (sc_reg > SCR_CONTROL)
|
||||
return -EINVAL;
|
||||
iowrite32(val, ap->ioaddr.scr_addr + (4 * sc_reg));
|
||||
iowrite32(val, link->ap->ioaddr.scr_addr + (4 * sc_reg));
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -210,20 +210,20 @@ static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
|
||||
goto skip_scr;
|
||||
|
||||
/* Resume phy. This is the old SATA resume sequence */
|
||||
svia_scr_write(ap, SCR_CONTROL, 0x300);
|
||||
svia_scr_read(ap, SCR_CONTROL, &scontrol); /* flush */
|
||||
svia_scr_write(link, SCR_CONTROL, 0x300);
|
||||
svia_scr_read(link, SCR_CONTROL, &scontrol); /* flush */
|
||||
|
||||
/* wait for phy to become ready, if necessary */
|
||||
do {
|
||||
msleep(200);
|
||||
svia_scr_read(ap, SCR_STATUS, &sstatus);
|
||||
svia_scr_read(link, SCR_STATUS, &sstatus);
|
||||
if ((sstatus & 0xf) != 1)
|
||||
break;
|
||||
} while (time_before(jiffies, timeout));
|
||||
|
||||
/* open code sata_print_link_status() */
|
||||
svia_scr_read(ap, SCR_STATUS, &sstatus);
|
||||
svia_scr_read(ap, SCR_CONTROL, &scontrol);
|
||||
svia_scr_read(link, SCR_STATUS, &sstatus);
|
||||
svia_scr_read(link, SCR_CONTROL, &scontrol);
|
||||
|
||||
online = (sstatus & 0xf) == 0x3;
|
||||
|
||||
@ -232,7 +232,7 @@ static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
|
||||
online ? "up" : "down", sstatus, scontrol);
|
||||
|
||||
/* SStatus is read one more time */
|
||||
svia_scr_read(ap, SCR_STATUS, &sstatus);
|
||||
svia_scr_read(link, SCR_STATUS, &sstatus);
|
||||
|
||||
if (!online) {
|
||||
/* tell EH to bail */
|
||||
|
@ -98,20 +98,22 @@ enum {
|
||||
VSC_SATA_INT_PHY_CHANGE),
|
||||
};
|
||||
|
||||
static int vsc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
||||
static int vsc_sata_scr_read(struct ata_link *link,
|
||||
unsigned int sc_reg, u32 *val)
|
||||
{
|
||||
if (sc_reg > SCR_CONTROL)
|
||||
return -EINVAL;
|
||||
*val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int vsc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
||||
static int vsc_sata_scr_write(struct ata_link *link,
|
||||
unsigned int sc_reg, u32 val)
|
||||
{
|
||||
if (sc_reg > SCR_CONTROL)
|
||||
return -EINVAL;
|
||||
writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -294,10 +294,10 @@ static void sas_ata_post_internal(struct ata_queued_cmd *qc)
|
||||
}
|
||||
}
|
||||
|
||||
static int sas_ata_scr_write(struct ata_port *ap, unsigned int sc_reg_in,
|
||||
static int sas_ata_scr_write(struct ata_link *link, unsigned int sc_reg_in,
|
||||
u32 val)
|
||||
{
|
||||
struct domain_device *dev = ap->private_data;
|
||||
struct domain_device *dev = link->ap->private_data;
|
||||
|
||||
SAS_DPRINTK("STUB %s\n", __func__);
|
||||
switch (sc_reg_in) {
|
||||
@ -319,10 +319,10 @@ static int sas_ata_scr_write(struct ata_port *ap, unsigned int sc_reg_in,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sas_ata_scr_read(struct ata_port *ap, unsigned int sc_reg_in,
|
||||
static int sas_ata_scr_read(struct ata_link *link, unsigned int sc_reg_in,
|
||||
u32 *val)
|
||||
{
|
||||
struct domain_device *dev = ap->private_data;
|
||||
struct domain_device *dev = link->ap->private_data;
|
||||
|
||||
SAS_DPRINTK("STUB %s\n", __func__);
|
||||
switch (sc_reg_in) {
|
||||
|
@ -772,8 +772,8 @@ struct ata_port_operations {
|
||||
/*
|
||||
* Optional features
|
||||
*/
|
||||
int (*scr_read)(struct ata_port *ap, unsigned int sc_reg, u32 *val);
|
||||
int (*scr_write)(struct ata_port *ap, unsigned int sc_reg, u32 val);
|
||||
int (*scr_read)(struct ata_link *link, unsigned int sc_reg, u32 *val);
|
||||
int (*scr_write)(struct ata_link *link, unsigned int sc_reg, u32 val);
|
||||
void (*pmp_attach)(struct ata_port *ap);
|
||||
void (*pmp_detach)(struct ata_port *ap);
|
||||
int (*enable_pm)(struct ata_port *ap, enum link_pm policy);
|
||||
|
Loading…
Reference in New Issue
Block a user