clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards
This patch introduces PLL_I2S and PLL_SAI. Vco clock of these PLLs can be modify by DT (only n multiplicator, m divider is still fixed by the boot-loader). Each PLL has 3 dividers. PLL should be off when we modify the rate. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Rob Herring <robh@kernel.org> [sboyd@codeaurora.org: Mark stm32f4_pll_div_ops static] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Gabriel Fernandez
Stephen Boyd
parent
f8b5036361
commit
83135ad3c5
@ -28,6 +28,14 @@
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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/*
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* Include list of clocks wich are not derived from system clock (SYSCLOCK)
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* The index of these clocks is the secondary index of DT bindings
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*
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*/
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#include <dt-bindings/clock/stm32fx-clock.h>
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#define STM32F4_RCC_CR 0x00
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#define STM32F4_RCC_PLLCFGR 0x04
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#define STM32F4_RCC_CFGR 0x08
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#define STM32F4_RCC_AHB1ENR 0x30
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@ -37,6 +45,8 @@
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#define STM32F4_RCC_APB2ENR 0x44
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#define STM32F4_RCC_BDCR 0x70
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#define STM32F4_RCC_CSR 0x74
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#define STM32F4_RCC_PLLI2SCFGR 0x84
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#define STM32F4_RCC_PLLSAICFGR 0x88
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struct stm32f4_gate_data {
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u8 offset;
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@ -208,8 +218,6 @@ static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
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{ STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
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};
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enum { SYSTICK, FCLK, CLK_LSI, CLK_LSE, CLK_HSE_RTC, CLK_RTC, END_PRIMARY_CLK };
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/*
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* This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
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* have gate bits associated with them. Its combined hweight is 71.
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@ -324,23 +332,312 @@ static struct clk *clk_register_apb_mul(struct device *dev, const char *name,
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return clk;
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}
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/*
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* Decode current PLL state and (statically) model the state we inherit from
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* the bootloader.
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*/
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static void stm32f4_rcc_register_pll(const char *hse_clk, const char *hsi_clk)
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enum {
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PLL,
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PLL_I2S,
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PLL_SAI,
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};
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static const struct clk_div_table pll_divp_table[] = {
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{ 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 }
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};
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static const struct clk_div_table pll_divr_table[] = {
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{ 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 }
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};
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struct stm32f4_pll {
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spinlock_t *lock;
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struct clk_gate gate;
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u8 offset;
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u8 bit_rdy_idx;
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u8 status;
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u8 n_start;
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};
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#define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate)
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struct stm32f4_vco_data {
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const char *vco_name;
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u8 offset;
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u8 bit_idx;
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u8 bit_rdy_idx;
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};
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static const struct stm32f4_vco_data vco_data[] = {
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{ "vco", STM32F4_RCC_PLLCFGR, 24, 25 },
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{ "vco-i2s", STM32F4_RCC_PLLI2SCFGR, 26, 27 },
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{ "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 },
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};
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struct stm32f4_div_data {
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u8 shift;
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u8 width;
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u8 flag_div;
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const struct clk_div_table *div_table;
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};
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#define MAX_PLL_DIV 3
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static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = {
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{ 16, 2, 0, pll_divp_table },
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{ 24, 4, CLK_DIVIDER_ONE_BASED, NULL },
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{ 28, 3, 0, pll_divr_table },
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};
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struct stm32f4_pll_data {
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u8 pll_num;
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u8 n_start;
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const char *div_name[MAX_PLL_DIV];
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};
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static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = {
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{ PLL, 192, { "pll", "pll48", NULL } },
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{ PLL_I2S, 192, { NULL, "plli2s-q", "plli2s-r" } },
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{ PLL_SAI, 49, { NULL, "pllsai-q", "pllsai-r" } },
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};
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static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
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{ PLL, 50, { "pll", "pll-q", NULL } },
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{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
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{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
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};
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static int stm32f4_pll_is_enabled(struct clk_hw *hw)
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{
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unsigned long pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
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return clk_gate_ops.is_enabled(hw);
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}
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unsigned long pllm = pllcfgr & 0x3f;
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unsigned long plln = (pllcfgr >> 6) & 0x1ff;
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unsigned long pllp = BIT(((pllcfgr >> 16) & 3) + 1);
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const char *pllsrc = pllcfgr & BIT(22) ? hse_clk : hsi_clk;
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unsigned long pllq = (pllcfgr >> 24) & 0xf;
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static int stm32f4_pll_enable(struct clk_hw *hw)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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struct stm32f4_pll *pll = to_stm32f4_pll(gate);
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int ret = 0;
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unsigned long reg;
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clk_register_fixed_factor(NULL, "vco", pllsrc, 0, plln, pllm);
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clk_register_fixed_factor(NULL, "pll", "vco", 0, 1, pllp);
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clk_register_fixed_factor(NULL, "pll48", "vco", 0, 1, pllq);
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ret = clk_gate_ops.enable(hw);
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ret = readl_relaxed_poll_timeout_atomic(base + STM32F4_RCC_CR, reg,
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reg & (1 << pll->bit_rdy_idx), 0, 10000);
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return ret;
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}
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static void stm32f4_pll_disable(struct clk_hw *hw)
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{
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clk_gate_ops.disable(hw);
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}
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static unsigned long stm32f4_pll_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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struct stm32f4_pll *pll = to_stm32f4_pll(gate);
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unsigned long n;
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n = (readl(base + pll->offset) >> 6) & 0x1ff;
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return parent_rate * n;
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}
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static long stm32f4_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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struct stm32f4_pll *pll = to_stm32f4_pll(gate);
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unsigned long n;
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n = rate / *prate;
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if (n < pll->n_start)
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n = pll->n_start;
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else if (n > 432)
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n = 432;
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return *prate * n;
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}
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static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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struct stm32f4_pll *pll = to_stm32f4_pll(gate);
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unsigned long n;
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unsigned long val;
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int pll_state;
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pll_state = stm32f4_pll_is_enabled(hw);
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if (pll_state)
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stm32f4_pll_disable(hw);
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n = rate / parent_rate;
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val = readl(base + pll->offset) & ~(0x1ff << 6);
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writel(val | ((n & 0x1ff) << 6), base + pll->offset);
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if (pll_state)
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stm32f4_pll_enable(hw);
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return 0;
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}
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static const struct clk_ops stm32f4_pll_gate_ops = {
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.enable = stm32f4_pll_enable,
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.disable = stm32f4_pll_disable,
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.is_enabled = stm32f4_pll_is_enabled,
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.recalc_rate = stm32f4_pll_recalc,
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.round_rate = stm32f4_pll_round_rate,
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.set_rate = stm32f4_pll_set_rate,
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};
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struct stm32f4_pll_div {
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struct clk_divider div;
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struct clk_hw *hw_pll;
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};
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#define to_pll_div_clk(_div) container_of(_div, struct stm32f4_pll_div, div)
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static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return clk_divider_ops.recalc_rate(hw, parent_rate);
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}
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static long stm32f4_pll_div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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return clk_divider_ops.round_rate(hw, rate, prate);
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}
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static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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int pll_state, ret;
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struct clk_divider *div = to_clk_divider(hw);
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struct stm32f4_pll_div *pll_div = to_pll_div_clk(div);
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pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll);
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if (pll_state)
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stm32f4_pll_disable(pll_div->hw_pll);
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ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
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if (pll_state)
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stm32f4_pll_enable(pll_div->hw_pll);
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return ret;
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}
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static const struct clk_ops stm32f4_pll_div_ops = {
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.recalc_rate = stm32f4_pll_div_recalc_rate,
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.round_rate = stm32f4_pll_div_round_rate,
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.set_rate = stm32f4_pll_div_set_rate,
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};
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static struct clk_hw *clk_register_pll_div(const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, const struct clk_div_table *table,
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struct clk_hw *pll_hw, spinlock_t *lock)
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{
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struct stm32f4_pll_div *pll_div;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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/* allocate the divider */
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pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL);
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if (!pll_div)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &stm32f4_pll_div_ops;
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init.flags = flags;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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/* struct clk_divider assignments */
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pll_div->div.reg = reg;
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pll_div->div.shift = shift;
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pll_div->div.width = width;
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pll_div->div.flags = clk_divider_flags;
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pll_div->div.lock = lock;
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pll_div->div.table = table;
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pll_div->div.hw.init = &init;
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pll_div->hw_pll = pll_hw;
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/* register the clock */
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hw = &pll_div->div.hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(pll_div);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc,
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const struct stm32f4_pll_data *data, spinlock_t *lock)
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{
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struct stm32f4_pll *pll;
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struct clk_init_data init = { NULL };
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void __iomem *reg;
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struct clk_hw *pll_hw;
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int ret;
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int i;
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const struct stm32f4_vco_data *vco;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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vco = &vco_data[data->pll_num];
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init.name = vco->vco_name;
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init.ops = &stm32f4_pll_gate_ops;
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init.flags = CLK_SET_RATE_GATE;
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init.parent_names = &pllsrc;
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init.num_parents = 1;
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pll->gate.lock = lock;
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pll->gate.reg = base + STM32F4_RCC_CR;
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pll->gate.bit_idx = vco->bit_idx;
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pll->gate.hw.init = &init;
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pll->offset = vco->offset;
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pll->n_start = data->n_start;
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pll->bit_rdy_idx = vco->bit_rdy_idx;
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pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1;
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reg = base + pll->offset;
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pll_hw = &pll->gate.hw;
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ret = clk_hw_register(NULL, pll_hw);
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if (ret) {
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kfree(pll);
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return ERR_PTR(ret);
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}
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for (i = 0; i < MAX_PLL_DIV; i++)
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if (data->div_name[i])
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clk_register_pll_div(data->div_name[i],
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vco->vco_name,
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0,
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reg,
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div_data[i].shift,
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div_data[i].width,
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div_data[i].flag_div,
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div_data[i].div_table,
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pll_hw,
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lock);
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return pll_hw;
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}
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/*
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@ -615,18 +912,21 @@ struct stm32f4_clk_data {
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const struct stm32f4_gate_data *gates_data;
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const u64 *gates_map;
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int gates_num;
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const struct stm32f4_pll_data *pll_data;
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};
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static const struct stm32f4_clk_data stm32f429_clk_data = {
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.gates_data = stm32f429_gates,
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.gates_map = stm32f42xx_gate_map,
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.gates_num = ARRAY_SIZE(stm32f429_gates),
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.pll_data = stm32f429_pll,
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};
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static const struct stm32f4_clk_data stm32f469_clk_data = {
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.gates_data = stm32f469_gates,
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.gates_map = stm32f46xx_gate_map,
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.gates_num = ARRAY_SIZE(stm32f469_gates),
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.pll_data = stm32f469_pll,
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};
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static const struct of_device_id stm32f4_of_match[] = {
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@ -647,6 +947,9 @@ static void __init stm32f4_rcc_init(struct device_node *np)
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int n;
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const struct of_device_id *match;
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const struct stm32f4_clk_data *data;
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unsigned long pllcfgr;
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const char *pllsrc;
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unsigned long pllm;
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base = of_iomap(np, 0);
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if (!base) {
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@ -677,7 +980,21 @@ static void __init stm32f4_rcc_init(struct device_node *np)
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clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0,
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16000000, 160000);
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stm32f4_rcc_register_pll(hse_clk, "hsi");
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pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
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pllsrc = pllcfgr & BIT(22) ? hse_clk : "hsi";
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pllm = pllcfgr & 0x3f;
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clk_hw_register_fixed_factor(NULL, "vco_in", pllsrc,
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0, 1, pllm);
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stm32f4_rcc_register_pll("vco_in", &data->pll_data[0],
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&stm32f4_clk_lock);
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clks[PLL_VCO_I2S] = stm32f4_rcc_register_pll("vco_in",
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&data->pll_data[1], &stm32f4_clk_lock);
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clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in",
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&data->pll_data[2], &stm32f4_clk_lock);
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sys_parents[1] = hse_clk;
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clk_register_mux_table(
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