From 8358491a6cffd4ea4a6951aef12386c4b8b838b3 Mon Sep 17 00:00:00 2001 From: Chunyan Zhang Date: Thu, 21 Dec 2023 17:28:22 +0800 Subject: [PATCH] arm64: dts: sprd: Removed unused clock references from etm nodes Remove these unused clock references to fix dtbs_check warnings: etm@3f740000: clocks: [[11], [35, 34], [36, 8]] is too long etm@3f740000: clock-names:1: 'atclk' was expected etm@3f740000: clock-names: ['apb_pclk', 'clk_cs', 'cs_src'] is too long Link: https://lore.kernel.org/r/20231221092824.1169453-1-chunyan.zhang@unisoc.com Signed-off-by: Chunyan Zhang --- arch/arm64/boot/dts/sprd/ums512.dtsi | 32 ++++++++++++++-------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/sprd/ums512.dtsi b/arch/arm64/boot/dts/sprd/ums512.dtsi index 97ac550af2f1..a4835ec1bb52 100644 --- a/arch/arm64/boot/dts/sprd/ums512.dtsi +++ b/arch/arm64/boot/dts/sprd/ums512.dtsi @@ -682,8 +682,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f040000 0 0x1000>; cpu = <&CPU0>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port { @@ -699,8 +699,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f140000 0 0x1000>; cpu = <&CPU1>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port { @@ -716,8 +716,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f240000 0 0x1000>; cpu = <&CPU2>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port { @@ -733,8 +733,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f340000 0 0x1000>; cpu = <&CPU3>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port { @@ -750,8 +750,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f440000 0 0x1000>; cpu = <&CPU4>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port { @@ -767,8 +767,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f540000 0 0x1000>; cpu = <&CPU5>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port { @@ -784,8 +784,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f640000 0 0x1000>; cpu = <&CPU6>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port { @@ -801,8 +801,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f740000 0 0x1000>; cpu = <&CPU7>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port {