ALSA: hda/cirrus: Add extra 10 ms delay to allow PLL settle and lock.
[ Upstream commit 9fb9fa18fb50d1a33a1bd947681fce96fc2c8db6 ] New HW platforms with multiple CS42L42 parts, faster CPU and i2c requre some extra delay to allow PLL to settle and lock. Adding extra 10ms delay. Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Link: https://lore.kernel.org/r/20221205145713.23852-1-vitalyr@opensource.cirrus.com Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -888,7 +888,7 @@ static void cs42l42_resume(struct sub_codec *cs42l42)
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/* Initialize CS42L42 companion codec */
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cs8409_i2c_bulk_write(cs42l42, cs42l42->init_seq, cs42l42->init_seq_num);
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usleep_range(20000, 25000);
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usleep_range(30000, 35000);
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/* Clear interrupts, by reading interrupt status registers */
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cs8409_i2c_bulk_read(cs42l42, irq_regs, ARRAY_SIZE(irq_regs));
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