Merge branches 'clk-bindings', 'clk-renesas', 'clk-amlogic', 'clk-allwinner' and 'clk-ti' into clk-next
* clk-bindings: dt-bindings: clock: ti,cdce925: Convert to DT schema * clk-renesas: (26 commits) clk: renesas: r8a779f0: Fix Ethernet Switch clocks clk: renesas: r8a779g0: Add Z0 clock support clk: renesas: r8a779g0: Add CMT clocks clk: renesas: r8a779g0: Add TMU and SASYNCRT clocks clk: renesas: r8a779f0: Fix SCIF parent clocks clk: renesas: r8a779f0: Fix HSCIF parent clocks clk: renesas: r9a06g032: Repair grave increment error clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM clk: renesas: rzg2l: Fix typo in struct rzg2l_cpg_priv kerneldoc clk: renesas: r8a779a0: Fix SD0H clock name clk: renesas: r8a779g0: Add RPC-IF clock clk: renesas: r8a779g0: Add SDHI clocks clk: renesas: r8a779f0: Add SASYNCPER internal clock clk: renesas: r8a779f0: Fix SD0H clock name clk: renesas: r9a07g043: Drop WDT2 clock and reset entry clk: renesas: r9a07g044: Drop WDT2 clock and reset entry clk: renesas: r8a779g0: Add TPU clock clk: renesas: r8a779g0: Add PWM clock clk: renesas: r8a779g0: Add SCIF clocks clk: renesas: r9a07g044: Add MTU3a clock and reset entry ... * clk-amlogic: clk: meson: pll: add pcie lock retry workaround clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock() * clk-allwinner: clk: sunxi-ng: f1c100s: Add IR mod clock clk: sunxi-ng: v3s: Correct the header guard of ccu-sun8i-v3s.h * clk-ti: clk: ti: fix typo in ti_clk_retry_init() code comment clk: ti: dra7-atl: don't allocate `parent_names' variable clk: ti: change ti_clk_register[_omap_hw]() API
This commit is contained in:
Stephen Boyd
commit
83907bf316
@ -1,53 +0,0 @@
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Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers.
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Reference
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] https://www.ti.com/product/cdce913
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[3] https://www.ti.com/product/cdce925
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[4] https://www.ti.com/product/cdce937
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[5] https://www.ti.com/product/cdce949
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The driver provides clock sources for each output Y1 through Y5.
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Required properties:
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- compatible: Shall be one of the following:
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- "ti,cdce913": 1-PLL, 3 Outputs
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- "ti,cdce925": 2-PLL, 5 Outputs
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- "ti,cdce937": 3-PLL, 7 Outputs
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- "ti,cdce949": 4-PLL, 9 Outputs
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- reg: I2C device address.
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- clocks: Points to a fixed parent clock that provides the input frequency.
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- #clock-cells: From common clock bindings: Shall be 1.
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Optional properties:
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- xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
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board, or to compensate for external influences.
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- vdd-supply: A regulator node for Vdd
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- vddout-supply: A regulator node for Vddout
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For all PLL1, PLL2, ... an optional child node can be used to specify spread
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spectrum clocking parameters for a board.
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- spread-spectrum: SSC mode as defined in the data sheet.
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- spread-spectrum-center: Use "centered" mode instead of "max" mode. When
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present, the clock runs at the requested frequency on average. Otherwise
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the requested frequency is the maximum value of the SCC range.
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Example:
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clockgen: cdce925pw@64 {
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compatible = "cdce925";
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reg = <0x64>;
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clocks = <&xtal_27Mhz>;
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#clock-cells = <1>;
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xtal-load-pf = <5>;
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vdd-supply = <&1v8-reg>;
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vddout-supply = <&3v3-reg>;
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/* PLL options to get SSC 1% centered */
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PLL2 {
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spread-spectrum = <4>;
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spread-spectrum-center;
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};
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};
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103
Documentation/devicetree/bindings/clock/ti,cdce925.yaml
Normal file
103
Documentation/devicetree/bindings/clock/ti,cdce925.yaml
Normal file
@ -0,0 +1,103 @@
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# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/ti,cdce925.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI CDCE913/925/937/949 programmable I2C clock synthesizers
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maintainers:
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- Alexander Stein <alexander.stein@ew.tq-group.com>
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description: |
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Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction
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- CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
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- CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
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- CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
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- CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
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properties:
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compatible:
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enum:
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- ti,cdce913
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- ti,cdce925
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- ti,cdce937
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- ti,cdce949
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reg:
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maxItems: 1
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clocks:
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items:
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- description: fixed parent clock
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"#clock-cells":
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const: 1
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vdd-supply:
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description: Regulator that provides 1.8V Vdd power supply
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vddout-supply:
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description: |
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Regulator that provides Vddout power supply.
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non-L variant: 2.5V or 3.3V for
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L variant: 1.8V for
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xtal-load-pf:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Crystal load-capacitor value to fine-tune performance on a
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board, or to compensate for external influences.
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patternProperties:
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"^PLL[1-4]$":
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type: object
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description: |
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optional child node can be used to specify spread
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spectrum clocking parameters for a board
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additionalProperties: false
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properties:
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spread-spectrum:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: SSC mode as defined in the data sheet
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spread-spectrum-center:
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type: boolean
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description: |
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Use "centered" mode instead of "max" mode. When
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present, the clock runs at the requested frequency on average.
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Otherwise the requested frequency is the maximum value of the
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SCC range.
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required:
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- compatible
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- reg
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- clocks
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- "#clock-cells"
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additionalProperties: false
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examples:
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- |
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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cdce925: clock-controller@64 {
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compatible = "ti,cdce925";
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reg = <0x64>;
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clocks = <&xtal_27Mhz>;
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#clock-cells = <1>;
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xtal-load-pf = <5>;
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vdd-supply = <®_1v8>;
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vddout-supply = <®_3v3>;
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/* PLL options to get SSC 1% centered */
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PLL2 {
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spread-spectrum = <4>;
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spread-spectrum-center;
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};
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};
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};
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@ -276,15 +276,15 @@ static int meson_clk_pll_wait_lock(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
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int delay = 24000000;
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int delay = 5000;
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do {
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/* Is the clock locked now ? */
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/* Is the clock locked now ? Time out after 100ms. */
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if (meson_parm_read(clk->map, &pll->l))
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return 0;
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delay--;
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} while (delay > 0);
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udelay(20);
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} while (--delay);
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return -ETIMEDOUT;
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}
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@ -319,12 +319,16 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw)
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static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
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{
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meson_clk_pll_init(hw);
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int retries = 10;
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if (meson_clk_pll_wait_lock(hw))
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return -EIO;
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do {
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meson_clk_pll_init(hw);
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if (!meson_clk_pll_wait_lock(hw))
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return 0;
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pr_info("Retry enabling PCIe PLL clock\n");
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} while (--retries);
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return 0;
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return -EIO;
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}
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static int meson_clk_pll_enable(struct clk_hw *hw)
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@ -116,7 +116,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
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DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1),
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DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1),
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DEF_GEN4_SDH("sdh0", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870),
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DEF_GEN4_SDH("sd0h", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870),
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DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870),
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DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
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@ -42,6 +42,7 @@ enum clk_ids {
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CLK_PLL5_DIV4,
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CLK_PLL6_DIV2,
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CLK_S0,
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CLK_SASYNCPER,
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CLK_SDSRC,
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CLK_RPCSRC,
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CLK_OCO,
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@ -71,6 +72,7 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
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DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
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DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1),
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DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
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DEF_RATE(".oco", CLK_OCO, 32768),
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@ -109,11 +111,11 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
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DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1),
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DEF_FIXED("sasyncrt", R8A779F0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1),
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DEF_FIXED("sasyncperd1", R8A779F0_CLK_SASYNCPERD1, CLK_PLL5_DIV4, 3, 1),
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DEF_FIXED("sasyncperd2", R8A779F0_CLK_SASYNCPERD2, R8A779F0_CLK_SASYNCPERD1, 2, 1),
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DEF_FIXED("sasyncperd4", R8A779F0_CLK_SASYNCPERD4, R8A779F0_CLK_SASYNCPERD1, 4, 1),
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DEF_FIXED("sasyncperd1",R8A779F0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
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DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
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DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
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DEF_GEN4_SDH("sdh0", R8A779F0_CLK_SD0H, CLK_SDSRC, 0x870),
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DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, 0x870),
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DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, 0x870),
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DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
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@ -126,10 +128,10 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
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};
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static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
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DEF_MOD("hscif0", 514, R8A779F0_CLK_S0D3),
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DEF_MOD("hscif1", 515, R8A779F0_CLK_S0D3),
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DEF_MOD("hscif2", 516, R8A779F0_CLK_S0D3),
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DEF_MOD("hscif3", 517, R8A779F0_CLK_S0D3),
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DEF_MOD("hscif0", 514, R8A779F0_CLK_SASYNCPERD1),
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DEF_MOD("hscif1", 515, R8A779F0_CLK_SASYNCPERD1),
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DEF_MOD("hscif2", 516, R8A779F0_CLK_SASYNCPERD1),
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DEF_MOD("hscif3", 517, R8A779F0_CLK_SASYNCPERD1),
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DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER),
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DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER),
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DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER),
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@ -142,10 +144,10 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
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DEF_MOD("msiof3", 621, R8A779F0_CLK_MSO),
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DEF_MOD("pcie0", 624, R8A779F0_CLK_S0D2),
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DEF_MOD("pcie1", 625, R8A779F0_CLK_S0D2),
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DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER),
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DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER),
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DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER),
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DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER),
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DEF_MOD("scif0", 702, R8A779F0_CLK_SASYNCPERD4),
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DEF_MOD("scif1", 703, R8A779F0_CLK_SASYNCPERD4),
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DEF_MOD("scif3", 704, R8A779F0_CLK_SASYNCPERD4),
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DEF_MOD("scif4", 705, R8A779F0_CLK_SASYNCPERD4),
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DEF_MOD("sdhi0", 706, R8A779F0_CLK_SD0),
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DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER),
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DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER),
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@ -161,6 +163,8 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
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DEF_MOD("cmt3", 913, R8A779F0_CLK_R),
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DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M),
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DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M),
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DEF_MOD("rswitch2", 1505, R8A779F0_CLK_RSW2),
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DEF_MOD("ether-serdes", 1506, R8A779F0_CLK_S0D2_HSC),
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DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC),
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};
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@ -91,11 +91,12 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
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DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
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DEF_RATE(".oco", CLK_OCO, 32768),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
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DEF_FIXED(".vio", CLK_VIO, CLK_PLL5_DIV2, 3, 1),
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DEF_FIXED(".vc", CLK_VC, CLK_PLL5_DIV2, 3, 1),
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/* Core Clock Outputs */
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DEF_GEN4_Z("z0", R8A779G0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0),
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DEF_FIXED("s0d2", R8A779G0_CLK_S0D2, CLK_S0, 2, 1),
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DEF_FIXED("s0d3", R8A779G0_CLK_S0D3, CLK_S0, 3, 1),
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DEF_FIXED("s0d4", R8A779G0_CLK_S0D4, CLK_S0, 4, 1),
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@ -130,6 +131,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
|
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DEF_FIXED("s0d4_hsc", R8A779G0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1),
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DEF_FIXED("cl16m_hsc", R8A779G0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1),
|
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DEF_FIXED("s0d2_cc", R8A779G0_CLK_S0D2_CC, CLK_S0, 2, 1),
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DEF_FIXED("sasyncrt", R8A779G0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1),
|
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DEF_FIXED("sasyncperd1",R8A779G0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
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||||
DEF_FIXED("sasyncperd2",R8A779G0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
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DEF_FIXED("sasyncperd4",R8A779G0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
|
||||
@ -144,7 +146,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
|
||||
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
|
||||
DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
|
||||
|
||||
DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, CLK_SDSRC, 0x870),
|
||||
DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870),
|
||||
DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870),
|
||||
DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
|
||||
|
||||
DEF_BASE("rpc", R8A779G0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
|
||||
@ -168,7 +171,33 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
|
||||
DEF_MOD("i2c3", 521, R8A779G0_CLK_S0D6_PER),
|
||||
DEF_MOD("i2c4", 522, R8A779G0_CLK_S0D6_PER),
|
||||
DEF_MOD("i2c5", 523, R8A779G0_CLK_S0D6_PER),
|
||||
DEF_MOD("irqc", 611, R8A779G0_CLK_CL16M),
|
||||
DEF_MOD("msi0", 618, R8A779G0_CLK_MSO),
|
||||
DEF_MOD("msi1", 619, R8A779G0_CLK_MSO),
|
||||
DEF_MOD("msi2", 620, R8A779G0_CLK_MSO),
|
||||
DEF_MOD("msi3", 621, R8A779G0_CLK_MSO),
|
||||
DEF_MOD("msi4", 622, R8A779G0_CLK_MSO),
|
||||
DEF_MOD("msi5", 623, R8A779G0_CLK_MSO),
|
||||
DEF_MOD("pwm", 628, R8A779G0_CLK_SASYNCPERD4),
|
||||
DEF_MOD("rpc-if", 629, R8A779G0_CLK_RPCD2),
|
||||
DEF_MOD("scif0", 702, R8A779G0_CLK_SASYNCPERD4),
|
||||
DEF_MOD("scif1", 703, R8A779G0_CLK_SASYNCPERD4),
|
||||
DEF_MOD("scif3", 704, R8A779G0_CLK_SASYNCPERD4),
|
||||
DEF_MOD("scif4", 705, R8A779G0_CLK_SASYNCPERD4),
|
||||
DEF_MOD("sdhi", 706, R8A779G0_CLK_SD0),
|
||||
DEF_MOD("sydm0", 709, R8A779G0_CLK_S0D6_PER),
|
||||
DEF_MOD("sydm1", 710, R8A779G0_CLK_S0D6_PER),
|
||||
DEF_MOD("tmu0", 713, R8A779G0_CLK_SASYNCRT),
|
||||
DEF_MOD("tmu1", 714, R8A779G0_CLK_SASYNCPERD2),
|
||||
DEF_MOD("tmu2", 715, R8A779G0_CLK_SASYNCPERD2),
|
||||
DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2),
|
||||
DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2),
|
||||
DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
|
||||
DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
|
||||
DEF_MOD("cmt0", 910, R8A779G0_CLK_R),
|
||||
DEF_MOD("cmt1", 911, R8A779G0_CLK_R),
|
||||
DEF_MOD("cmt2", 912, R8A779G0_CLK_R),
|
||||
DEF_MOD("cmt3", 913, R8A779G0_CLK_R),
|
||||
DEF_MOD("pfc0", 915, R8A779G0_CLK_CL16M),
|
||||
DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M),
|
||||
DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M),
|
||||
|
||||
@ -412,7 +412,7 @@ static int r9a06g032_attach_dev(struct generic_pm_domain *pd,
|
||||
int error;
|
||||
int index;
|
||||
|
||||
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
|
||||
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i++,
|
||||
&clkspec)) {
|
||||
if (clkspec.np != pd->dev.of_node)
|
||||
continue;
|
||||
@ -425,7 +425,6 @@ static int r9a06g032_attach_dev(struct generic_pm_domain *pd,
|
||||
if (error)
|
||||
return error;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@ -158,10 +158,6 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
|
||||
0x548, 0),
|
||||
DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
|
||||
0x548, 1),
|
||||
DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0,
|
||||
0x548, 4),
|
||||
DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK,
|
||||
0x548, 5),
|
||||
DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,
|
||||
0x550, 0),
|
||||
DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,
|
||||
@ -269,7 +265,6 @@ static struct rzg2l_reset r9a07g043_resets[] = {
|
||||
DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
|
||||
DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
|
||||
DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
|
||||
DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2),
|
||||
DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
|
||||
DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
|
||||
DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
|
||||
|
||||
@ -182,7 +182,7 @@ static const struct {
|
||||
};
|
||||
|
||||
static const struct {
|
||||
struct rzg2l_mod_clk common[76];
|
||||
struct rzg2l_mod_clk common[75];
|
||||
#ifdef CONFIG_CLK_R9A07G054
|
||||
struct rzg2l_mod_clk drp[0];
|
||||
#endif
|
||||
@ -204,6 +204,8 @@ static const struct {
|
||||
0x534, 1),
|
||||
DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
|
||||
0x534, 2),
|
||||
DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0,
|
||||
0x538, 0),
|
||||
DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
|
||||
0x540, 0),
|
||||
DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
|
||||
@ -222,10 +224,6 @@ static const struct {
|
||||
0x548, 2),
|
||||
DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
|
||||
0x548, 3),
|
||||
DEF_MOD("wdt2_pclk", R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0,
|
||||
0x548, 4),
|
||||
DEF_MOD("wdt2_clk", R9A07G044_WDT2_CLK, R9A07G044_OSCCLK,
|
||||
0x548, 5),
|
||||
DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
|
||||
0x550, 0),
|
||||
DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
|
||||
@ -356,6 +354,7 @@ static struct rzg2l_reset r9a07g044_resets[] = {
|
||||
DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
|
||||
DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
|
||||
DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
|
||||
DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0),
|
||||
DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
|
||||
DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0),
|
||||
DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),
|
||||
@ -363,7 +362,6 @@ static struct rzg2l_reset r9a07g044_resets[] = {
|
||||
DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3),
|
||||
DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
|
||||
DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
|
||||
DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),
|
||||
DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
|
||||
DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
|
||||
DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
|
||||
|
||||
@ -95,7 +95,8 @@ struct rzg2l_pll5_mux_dsi_div_param {
|
||||
* @num_resets: Number of Module Resets in info->resets[]
|
||||
* @last_dt_core_clk: ID of the last Core Clock exported to DT
|
||||
* @info: Pointer to platform data
|
||||
* @pll5_mux_dsi_div_params: pll5 mux and dsi div parameters
|
||||
* @genpd: PM domain
|
||||
* @mux_dsi_div_params: pll5 mux and dsi div parameters
|
||||
*/
|
||||
struct rzg2l_cpg_priv {
|
||||
struct reset_controller_dev rcdev;
|
||||
@ -111,6 +112,8 @@ struct rzg2l_cpg_priv {
|
||||
|
||||
const struct rzg2l_cpg_info *info;
|
||||
|
||||
struct generic_pm_domain genpd;
|
||||
|
||||
struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
|
||||
};
|
||||
|
||||
@ -182,7 +185,7 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core,
|
||||
static int rzg2l_cpg_sd_clk_mux_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
return clk_mux_determine_rate_flags(hw, req, 0);
|
||||
return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST);
|
||||
}
|
||||
|
||||
static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
|
||||
@ -1014,8 +1017,8 @@ static const struct clk_ops rzg2l_mod_clock_ops = {
|
||||
};
|
||||
|
||||
static struct mstp_clock
|
||||
*rzg2l_mod_clock__get_sibling(struct mstp_clock *clock,
|
||||
struct rzg2l_cpg_priv *priv)
|
||||
*rzg2l_mod_clock_get_sibling(struct mstp_clock *clock,
|
||||
struct rzg2l_cpg_priv *priv)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
unsigned int i;
|
||||
@ -1101,7 +1104,7 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
|
||||
struct mstp_clock *sibling;
|
||||
|
||||
clock->enabled = rzg2l_mod_clock_is_enabled(&clock->hw);
|
||||
sibling = rzg2l_mod_clock__get_sibling(clock, priv);
|
||||
sibling = rzg2l_mod_clock_get_sibling(clock, priv);
|
||||
if (sibling) {
|
||||
clock->sibling = sibling;
|
||||
sibling->sibling = clock;
|
||||
@ -1223,22 +1226,31 @@ static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
|
||||
return devm_reset_controller_register(priv->dev, &priv->rcdev);
|
||||
}
|
||||
|
||||
static bool rzg2l_cpg_is_pm_clk(const struct of_phandle_args *clkspec)
|
||||
static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
|
||||
const struct of_phandle_args *clkspec)
|
||||
{
|
||||
const struct rzg2l_cpg_info *info = priv->info;
|
||||
unsigned int id;
|
||||
unsigned int i;
|
||||
|
||||
if (clkspec->args_count != 2)
|
||||
return false;
|
||||
|
||||
switch (clkspec->args[0]) {
|
||||
case CPG_MOD:
|
||||
return true;
|
||||
|
||||
default:
|
||||
if (clkspec->args[0] != CPG_MOD)
|
||||
return false;
|
||||
|
||||
id = clkspec->args[1] + info->num_total_core_clks;
|
||||
for (i = 0; i < info->num_no_pm_mod_clks; i++) {
|
||||
if (info->no_pm_mod_clks[i] == id)
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev)
|
||||
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
|
||||
{
|
||||
struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd);
|
||||
struct device_node *np = dev->of_node;
|
||||
struct of_phandle_args clkspec;
|
||||
bool once = true;
|
||||
@ -1248,7 +1260,7 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device
|
||||
|
||||
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
|
||||
&clkspec)) {
|
||||
if (rzg2l_cpg_is_pm_clk(&clkspec)) {
|
||||
if (rzg2l_cpg_is_pm_clk(priv, &clkspec)) {
|
||||
if (once) {
|
||||
once = false;
|
||||
error = pm_clk_create(dev);
|
||||
@ -1298,16 +1310,13 @@ static void rzg2l_cpg_genpd_remove(void *data)
|
||||
pm_genpd_remove(data);
|
||||
}
|
||||
|
||||
static int __init rzg2l_cpg_add_clk_domain(struct device *dev)
|
||||
static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
|
||||
{
|
||||
struct device *dev = priv->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct generic_pm_domain *genpd;
|
||||
struct generic_pm_domain *genpd = &priv->genpd;
|
||||
int ret;
|
||||
|
||||
genpd = devm_kzalloc(dev, sizeof(*genpd), GFP_KERNEL);
|
||||
if (!genpd)
|
||||
return -ENOMEM;
|
||||
|
||||
genpd->name = np->name;
|
||||
genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
|
||||
GENPD_FLAG_ACTIVE_WAKEUP;
|
||||
@ -1377,7 +1386,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
error = rzg2l_cpg_add_clk_domain(dev);
|
||||
error = rzg2l_cpg_add_clk_domain(priv);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
|
||||
@ -256,6 +256,10 @@ struct rzg2l_cpg_info {
|
||||
unsigned int num_mod_clks;
|
||||
unsigned int num_hw_mod_clks;
|
||||
|
||||
/* No PM Module Clocks */
|
||||
const unsigned int *no_pm_mod_clks;
|
||||
unsigned int num_no_pm_mod_clks;
|
||||
|
||||
/* Resets */
|
||||
const struct rzg2l_reset *resets;
|
||||
unsigned int num_resets;
|
||||
|
||||
@ -6,8 +6,8 @@
|
||||
* Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*/
|
||||
|
||||
#ifndef _CCU_SUN8I_H3_H_
|
||||
#define _CCU_SUN8I_H3_H_
|
||||
#ifndef _CCU_SUN8I_V3S_H_
|
||||
#define _CCU_SUN8I_V3S_H_
|
||||
|
||||
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
|
||||
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
|
||||
@ -51,4 +51,4 @@
|
||||
|
||||
#define CLK_PLL_DDR1 74
|
||||
|
||||
#endif /* _CCU_SUN8I_H3_H_ */
|
||||
#endif /* _CCU_SUN8I_V3S_H_ */
|
||||
|
||||
@ -239,7 +239,14 @@ static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents,
|
||||
static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
|
||||
0x0b4, 16, 2, BIT(31), 0);
|
||||
|
||||
/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */
|
||||
static const char * const ir_parents[] = { "osc32k", "osc24M" };
|
||||
static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
|
||||
ir_parents, 0x0b8,
|
||||
0, 4, /* M */
|
||||
16, 2, /* P */
|
||||
24, 2, /* mux */
|
||||
BIT(31), /* gate */
|
||||
0);
|
||||
|
||||
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
|
||||
0x0cc, BIT(1), 0);
|
||||
@ -355,6 +362,7 @@ static struct ccu_common *suniv_ccu_clks[] = {
|
||||
&mmc1_output_clk.common,
|
||||
&i2s_clk.common,
|
||||
&spdif_clk.common,
|
||||
&ir_clk.common,
|
||||
&usb_phy0_clk.common,
|
||||
&dram_ve_clk.common,
|
||||
&dram_csi_clk.common,
|
||||
@ -446,6 +454,7 @@ static struct clk_hw_onecell_data suniv_hw_clks = {
|
||||
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
|
||||
[CLK_I2S] = &i2s_clk.common.hw,
|
||||
[CLK_SPDIF] = &spdif_clk.common.hw,
|
||||
[CLK_IR] = &ir_clk.common.hw,
|
||||
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
|
||||
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
|
||||
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
|
||||
|
||||
@ -29,6 +29,6 @@
|
||||
|
||||
/* All bus gates, DRAM gates and mod clocks are exported */
|
||||
|
||||
#define CLK_NUMBER (CLK_AVS + 1)
|
||||
#define CLK_NUMBER (CLK_IR + 1)
|
||||
|
||||
#endif /* _CCU_SUNIV_F1C100S_H_ */
|
||||
|
||||
@ -160,7 +160,7 @@ static void __init omap_clk_register_apll(void *user,
|
||||
ad->clk_bypass = __clk_get_hw(clk);
|
||||
|
||||
name = ti_dt_clk_name(node);
|
||||
clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
|
||||
clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
kfree(init->parent_names);
|
||||
@ -400,7 +400,7 @@ static void __init of_omap2_apll_setup(struct device_node *node)
|
||||
goto cleanup;
|
||||
|
||||
name = ti_dt_clk_name(node);
|
||||
clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
|
||||
clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
kfree(init);
|
||||
|
||||
@ -163,8 +163,8 @@ static const struct clk_ops atl_clk_ops = {
|
||||
static void __init of_dra7_atl_clock_setup(struct device_node *node)
|
||||
{
|
||||
struct dra7_atl_desc *clk_hw = NULL;
|
||||
struct clk_parent_data pdata = { .index = 0 };
|
||||
struct clk_init_data init = { NULL };
|
||||
const char **parent_names = NULL;
|
||||
const char *name;
|
||||
struct clk *clk;
|
||||
|
||||
@ -188,24 +188,14 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node)
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
|
||||
|
||||
if (!parent_names)
|
||||
goto cleanup;
|
||||
|
||||
parent_names[0] = of_clk_get_parent_name(node, 0);
|
||||
|
||||
init.parent_names = parent_names;
|
||||
|
||||
clk = ti_clk_register(NULL, &clk_hw->hw, name);
|
||||
init.parent_data = &pdata;
|
||||
clk = of_ti_clk_register(node, &clk_hw->hw, name);
|
||||
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
kfree(parent_names);
|
||||
return;
|
||||
}
|
||||
cleanup:
|
||||
kfree(parent_names);
|
||||
kfree(clk_hw);
|
||||
}
|
||||
CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup);
|
||||
|
||||
@ -263,7 +263,7 @@ static LIST_HEAD(retry_list);
|
||||
|
||||
/**
|
||||
* ti_clk_retry_init - retries a failed clock init at later phase
|
||||
* @node: device not for the clock
|
||||
* @node: device node for the clock
|
||||
* @user: user data pointer
|
||||
* @func: init function to be called for the clock
|
||||
*
|
||||
@ -475,7 +475,7 @@ void __init ti_clk_add_aliases(void)
|
||||
clkspec.np = np;
|
||||
clk = of_clk_get_from_provider(&clkspec);
|
||||
|
||||
ti_clk_add_alias(NULL, clk, ti_dt_clk_name(np));
|
||||
ti_clk_add_alias(clk, ti_dt_clk_name(np));
|
||||
}
|
||||
}
|
||||
|
||||
@ -528,7 +528,6 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
|
||||
|
||||
/**
|
||||
* ti_clk_add_alias - add a clock alias for a TI clock
|
||||
* @dev: device alias for this clock
|
||||
* @clk: clock handle to create alias for
|
||||
* @con: connection ID for this clock
|
||||
*
|
||||
@ -536,7 +535,7 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
|
||||
* and assigns the data to it. Returns 0 if successful, negative error
|
||||
* value otherwise.
|
||||
*/
|
||||
int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con)
|
||||
int ti_clk_add_alias(struct clk *clk, const char *con)
|
||||
{
|
||||
struct clk_lookup *cl;
|
||||
|
||||
@ -550,8 +549,6 @@ int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con)
|
||||
if (!cl)
|
||||
return -ENOMEM;
|
||||
|
||||
if (dev)
|
||||
cl->dev_id = dev_name(dev);
|
||||
cl->con_id = con;
|
||||
cl->clk = clk;
|
||||
|
||||
@ -561,8 +558,8 @@ int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con)
|
||||
}
|
||||
|
||||
/**
|
||||
* ti_clk_register - register a TI clock to the common clock framework
|
||||
* @dev: device for this clock
|
||||
* of_ti_clk_register - register a TI clock to the common clock framework
|
||||
* @node: device node for this clock
|
||||
* @hw: hardware clock handle
|
||||
* @con: connection ID for this clock
|
||||
*
|
||||
@ -570,17 +567,18 @@ int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con)
|
||||
* alias for it. Returns a handle to the registered clock if successful,
|
||||
* ERR_PTR value in failure.
|
||||
*/
|
||||
struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
|
||||
const char *con)
|
||||
struct clk *of_ti_clk_register(struct device_node *node, struct clk_hw *hw,
|
||||
const char *con)
|
||||
{
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
clk = clk_register(dev, hw);
|
||||
if (IS_ERR(clk))
|
||||
return clk;
|
||||
ret = of_clk_hw_register(node, hw);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
ret = ti_clk_add_alias(dev, clk, con);
|
||||
clk = hw->clk;
|
||||
ret = ti_clk_add_alias(clk, con);
|
||||
if (ret) {
|
||||
clk_unregister(clk);
|
||||
return ERR_PTR(ret);
|
||||
@ -590,8 +588,8 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
|
||||
}
|
||||
|
||||
/**
|
||||
* ti_clk_register_omap_hw - register a clk_hw_omap to the clock framework
|
||||
* @dev: device for this clock
|
||||
* of_ti_clk_register_omap_hw - register a clk_hw_omap to the clock framework
|
||||
* @node: device node for this clock
|
||||
* @hw: hardware clock handle
|
||||
* @con: connection ID for this clock
|
||||
*
|
||||
@ -600,13 +598,13 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
|
||||
* Returns a handle to the registered clock if successful, ERR_PTR value
|
||||
* in failure.
|
||||
*/
|
||||
struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw,
|
||||
const char *con)
|
||||
struct clk *of_ti_clk_register_omap_hw(struct device_node *node,
|
||||
struct clk_hw *hw, const char *con)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_hw_omap *oclk;
|
||||
|
||||
clk = ti_clk_register(dev, hw, con);
|
||||
clk = of_ti_clk_register(node, hw, con);
|
||||
if (IS_ERR(clk))
|
||||
return clk;
|
||||
|
||||
|
||||
@ -305,7 +305,7 @@ _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
|
||||
init.ops = ops;
|
||||
init.flags = 0;
|
||||
|
||||
clk = ti_clk_register(NULL, clk_hw, init.name);
|
||||
clk = of_ti_clk_register(node, clk_hw, init.name);
|
||||
if (IS_ERR_OR_NULL(clk)) {
|
||||
ret = -EINVAL;
|
||||
goto cleanup;
|
||||
@ -682,7 +682,7 @@ clkdm_found:
|
||||
init.ops = &omap4_clkctrl_clk_ops;
|
||||
hw->hw.init = &init;
|
||||
|
||||
clk = ti_clk_register_omap_hw(NULL, &hw->hw, init.name);
|
||||
clk = of_ti_clk_register_omap_hw(node, &hw->hw, init.name);
|
||||
if (IS_ERR_OR_NULL(clk))
|
||||
goto cleanup;
|
||||
|
||||
|
||||
@ -199,12 +199,12 @@ extern const struct omap_clkctrl_data dm816_clkctrl_data[];
|
||||
|
||||
typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
|
||||
|
||||
struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
|
||||
const char *con);
|
||||
struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw,
|
||||
const char *con);
|
||||
struct clk *of_ti_clk_register(struct device_node *node, struct clk_hw *hw,
|
||||
const char *con);
|
||||
struct clk *of_ti_clk_register_omap_hw(struct device_node *node,
|
||||
struct clk_hw *hw, const char *con);
|
||||
const char *ti_dt_clk_name(struct device_node *np);
|
||||
int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
|
||||
int ti_clk_add_alias(struct clk *clk, const char *con);
|
||||
void ti_clk_add_aliases(void);
|
||||
|
||||
void ti_clk_latch(struct clk_omap_reg *reg, s8 shift);
|
||||
|
||||
@ -176,7 +176,7 @@ static void __init _register_composite(void *user,
|
||||
&ti_composite_gate_ops, 0);
|
||||
|
||||
if (!IS_ERR(clk)) {
|
||||
ret = ti_clk_add_alias(NULL, clk, name);
|
||||
ret = ti_clk_add_alias(clk, name);
|
||||
if (ret) {
|
||||
clk_unregister(clk);
|
||||
goto cleanup;
|
||||
|
||||
@ -326,7 +326,7 @@ static struct clk *_register_divider(struct device_node *node,
|
||||
div->hw.init = &init;
|
||||
|
||||
/* register the clock */
|
||||
clk = ti_clk_register(NULL, &div->hw, name);
|
||||
clk = of_ti_clk_register(node, &div->hw, name);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
kfree(div);
|
||||
|
||||
@ -187,7 +187,7 @@ static void __init _register_dpll(void *user,
|
||||
|
||||
/* register the clock */
|
||||
name = ti_dt_clk_name(node);
|
||||
clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
|
||||
clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
|
||||
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
@ -259,7 +259,7 @@ static void _register_dpll_x2(struct device_node *node,
|
||||
#endif
|
||||
|
||||
/* register the clock */
|
||||
clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
|
||||
clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
kfree(clk_hw);
|
||||
|
||||
@ -54,7 +54,7 @@ static void __init of_ti_fixed_factor_clk_setup(struct device_node *node)
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
of_ti_clk_autoidle_setup(node);
|
||||
ti_clk_add_alias(NULL, clk, clk_name);
|
||||
ti_clk_add_alias(clk, clk_name);
|
||||
}
|
||||
}
|
||||
CLK_OF_DECLARE(ti_fixed_factor_clk, "ti,fixed-factor-clock",
|
||||
|
||||
@ -85,7 +85,7 @@ static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct clk *_register_gate(struct device *dev, const char *name,
|
||||
static struct clk *_register_gate(struct device_node *node, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
struct clk_omap_reg *reg, u8 bit_idx,
|
||||
u8 clk_gate_flags, const struct clk_ops *ops,
|
||||
@ -115,7 +115,7 @@ static struct clk *_register_gate(struct device *dev, const char *name,
|
||||
|
||||
init.flags = flags;
|
||||
|
||||
clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
|
||||
clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
kfree(clk_hw);
|
||||
@ -158,7 +158,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node,
|
||||
clk_gate_flags |= INVERT_ENABLE;
|
||||
|
||||
name = ti_dt_clk_name(node);
|
||||
clk = _register_gate(NULL, name, parent_name, flags, ®,
|
||||
clk = _register_gate(node, name, parent_name, flags, ®,
|
||||
enable_bit, clk_gate_flags, ops, hw_ops);
|
||||
|
||||
if (!IS_ERR(clk))
|
||||
|
||||
@ -24,7 +24,8 @@ static const struct clk_ops ti_interface_clk_ops = {
|
||||
.is_enabled = &omap2_dflt_clk_is_enabled,
|
||||
};
|
||||
|
||||
static struct clk *_register_interface(struct device *dev, const char *name,
|
||||
static struct clk *_register_interface(struct device_node *node,
|
||||
const char *name,
|
||||
const char *parent_name,
|
||||
struct clk_omap_reg *reg, u8 bit_idx,
|
||||
const struct clk_hw_omap_ops *ops)
|
||||
@ -49,7 +50,7 @@ static struct clk *_register_interface(struct device *dev, const char *name,
|
||||
init.num_parents = 1;
|
||||
init.parent_names = &parent_name;
|
||||
|
||||
clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
|
||||
clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
kfree(clk_hw);
|
||||
@ -80,7 +81,7 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node,
|
||||
}
|
||||
|
||||
name = ti_dt_clk_name(node);
|
||||
clk = _register_interface(NULL, name, parent_name, ®,
|
||||
clk = _register_interface(node, name, parent_name, ®,
|
||||
enable_bit, ops);
|
||||
|
||||
if (!IS_ERR(clk))
|
||||
|
||||
@ -118,7 +118,7 @@ const struct clk_ops ti_clk_mux_ops = {
|
||||
.restore_context = clk_mux_restore_context,
|
||||
};
|
||||
|
||||
static struct clk *_register_mux(struct device *dev, const char *name,
|
||||
static struct clk *_register_mux(struct device_node *node, const char *name,
|
||||
const char * const *parent_names,
|
||||
u8 num_parents, unsigned long flags,
|
||||
struct clk_omap_reg *reg, u8 shift, u32 mask,
|
||||
@ -148,7 +148,7 @@ static struct clk *_register_mux(struct device *dev, const char *name,
|
||||
mux->table = table;
|
||||
mux->hw.init = &init;
|
||||
|
||||
clk = ti_clk_register(dev, &mux->hw, name);
|
||||
clk = of_ti_clk_register(node, &mux->hw, name);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
kfree(mux);
|
||||
@ -207,7 +207,7 @@ static void of_mux_clk_setup(struct device_node *node)
|
||||
mask = (1 << fls(mask)) - 1;
|
||||
|
||||
name = ti_dt_clk_name(node);
|
||||
clk = _register_mux(NULL, name, parent_names, num_parents,
|
||||
clk = _register_mux(node, name, parent_names, num_parents,
|
||||
flags, ®, shift, mask, latch, clk_mux_flags,
|
||||
NULL);
|
||||
|
||||
|
||||
@ -67,4 +67,6 @@
|
||||
#define CLK_CODEC 65
|
||||
#define CLK_AVS 66
|
||||
|
||||
#define CLK_IR 67
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user