diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt index b7b55a964f65..f488b0f77406 100644 --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt @@ -45,8 +45,9 @@ to specify in a pinconf subnode: Valid values for groups are: ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp, - qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp, - spi0_1_grp - spi0_2_grp, spi1_0_grp - spi1_3_grp, sdio0_0_grp - sdio0_2_grp, + qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp - spi0_2_grp, + spi0_X_ssY (X=0..2, Y=0..2), spi1_0_grp - spi1_3_grp, + spi1_X_ssY (X=0..3, Y=0..2), sdio0_0_grp - sdio0_2_grp, sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp, sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand, can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp, @@ -59,7 +60,7 @@ to specify in a pinconf subnode: Valid values for function are: ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1, - spi0, spi1, sdio0, sdio0_pc, sdio0_cd, sdio0_wp, + spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc, sdio0_cd, sdio0_wp, sdio1, sdio1_pc, sdio1_cd, sdio1_wp, smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1, i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1 diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index 22280bddb9e2..af726b906656 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -101,6 +101,8 @@ enum zynq_pinmux_functions { ZYNQ_PMUX_qspi_cs1, ZYNQ_PMUX_spi0, ZYNQ_PMUX_spi1, + ZYNQ_PMUX_spi0_ss, + ZYNQ_PMUX_spi1_ss, ZYNQ_PMUX_sdio0, ZYNQ_PMUX_sdio0_pc, ZYNQ_PMUX_sdio0_cd, @@ -196,13 +198,35 @@ static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6}; static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13}; static const unsigned int qspi_cs1_pins[] = {0}; static const unsigned int qspi_fbclk_pins[] = {8}; -static const unsigned int spi0_0_pins[] = {16, 17, 18, 19, 20, 21}; -static const unsigned int spi0_1_pins[] = {28, 29, 30, 31, 32, 33}; -static const unsigned int spi0_2_pins[] = {40, 41, 42, 43, 44, 45}; -static const unsigned int spi1_0_pins[] = {10, 11, 12, 13, 14, 15}; -static const unsigned int spi1_1_pins[] = {22, 23, 24, 25, 26, 27}; -static const unsigned int spi1_2_pins[] = {34, 35, 36, 37, 38, 39}; -static const unsigned int spi1_3_pins[] = {46, 47, 48, 49, 40, 51}; +static const unsigned int spi0_0_pins[] = {16, 17, 21}; +static const unsigned int spi0_0_ss0_pins[] = {18}; +static const unsigned int spi0_0_ss1_pins[] = {19}; +static const unsigned int spi0_0_ss2_pins[] = {20,}; +static const unsigned int spi0_1_pins[] = {28, 29, 33}; +static const unsigned int spi0_1_ss0_pins[] = {30}; +static const unsigned int spi0_1_ss1_pins[] = {31}; +static const unsigned int spi0_1_ss2_pins[] = {32}; +static const unsigned int spi0_2_pins[] = {40, 41, 45}; +static const unsigned int spi0_2_ss0_pins[] = {42}; +static const unsigned int spi0_2_ss1_pins[] = {43}; +static const unsigned int spi0_2_ss2_pins[] = {44}; +static const unsigned int spi1_0_pins[] = {10, 11, 12}; +static const unsigned int spi1_0_ss0_pins[] = {13}; +static const unsigned int spi1_0_ss1_pins[] = {14}; +static const unsigned int spi1_0_ss2_pins[] = {15}; +static const unsigned int spi1_1_pins[] = {22, 23, 24}; +static const unsigned int spi1_1_ss0_pins[] = {25}; +static const unsigned int spi1_1_ss1_pins[] = {26}; +static const unsigned int spi1_1_ss2_pins[] = {27}; +static const unsigned int spi1_2_pins[] = {34, 35, 36}; +static const unsigned int spi1_2_ss0_pins[] = {37}; +static const unsigned int spi1_2_ss1_pins[] = {38}; +static const unsigned int spi1_2_ss2_pins[] = {39}; +static const unsigned int spi1_3_pins[] = {46, 47, 48, 49}; +static const unsigned int spi1_3_ss0_pins[] = {49}; +static const unsigned int spi1_3_ss1_pins[] = {50}; +static const unsigned int spi1_3_ss2_pins[] = {51}; + static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21}; static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33}; static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45}; @@ -379,12 +403,33 @@ struct zynq_pctrl_group zynq_pctrl_groups[] = { DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk), DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1), DEFINE_ZYNQ_PINCTRL_GRP(spi0_0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi0_1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi0_2), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_2), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_3), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss2), DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0), DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1), DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2), @@ -552,6 +597,15 @@ static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp", "spi0_2_grp"}; static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp", "spi1_2_grp", "spi1_3_grp"}; +static const char * const spi0_ss_groups[] = {"spi0_0_ss0_grp", + "spi0_0_ss1_grp", "spi0_0_ss2_grp", "spi0_1_ss0_grp", + "spi0_1_ss1_grp", "spi0_1_ss2_grp", "spi0_2_ss0_grp", + "spi0_2_ss1_grp", "spi0_2_ss2_grp"}; +static const char * const spi1_ss_groups[] = {"spi1_0_ss0_grp", + "spi1_0_ss1_grp", "spi1_0_ss2_grp", "spi1_1_ss0_grp", + "spi1_1_ss1_grp", "spi1_1_ss2_grp", "spi1_2_ss0_grp", + "spi1_2_ss1_grp", "spi1_2_ss2_grp", "spi1_3_ss0_grp", + "spi1_3_ss1_grp", "spi1_3_ss2_grp"}; static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp", "sdio0_2_grp"}; static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp", @@ -742,6 +796,8 @@ static const struct zynq_pinmux_function zynq_pmux_functions[] = { DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1), DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50), DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50), + DEFINE_ZYNQ_PINMUX_FUNCTION(spi0_ss, 0x50), + DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc), DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 130, ZYNQ_SDIO_WP_MASK,